Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect

In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device-level simulation. The results demonstrate that, under the combined influence of these two effects, the circuit’s upset threshold and critical charge decreased by 15.4% and 23.5%, respectively. This indicates that the charge sharing effect exacerbates the single event effects. By analyzing the incident conditions of two different incident radius particles, it is concluded that the particles with a smaller incident radius have a worse impact on the SRAM circuit, and are more likely to cause the single event upset in the circuit, indicating that the ionization distribution generated by the incident particle affects the charge collection.


Introduction
As a storage circuit, static random access memory (SRAM) has been widely used in the field of integrated circuits due to its advantages of fast speed and stable operation.Its reliability has always been the focus of researchers.In the space environment, a SRAM circuit is subjected to a single event effect (SEE) due to the incident of high energy particles.As a common soft error, single event upset (SEU) causes the node potential of SRAM to flip, destroying the original storage logic and affecting the normal operation of the circuit [1].To improve the single event resistance of SRAM, researchers have proposed various reinforcement schemes.A fully depleted silicon-on-insulator (FDSOI) has an ultrathin top layer of silicon and a buried oxide layer (BOX) composed of silicon dioxide, which can effectively isolate the collection of charges by the electrode and improve the anti-single event capability of the device.Experiments show [2] that FDSOIs have low SEE sensitivity and a high total ionizing dose (TID) resistance, which is very suitable for applications in the space environment.
With the increasing integration of circuits, the number of transistors per unit area on the wafer is increasing, and the distance between devices is shrinking, aggravating the charge sharing effect [3].Studies have shown that although FDSOI devices provide better resistance to SEU than comparable bulk technologies, there is also a charge sharing effect in the circuit which will lead to single event multi-bit upset (SEMU) in the circuit [4].The most direct way to study the SEE of SRAM is to verify the circuit through satellite in orbit or ground test experiments, but the experimental verification is not only expensive, but also the impact on the SEE cannot be observed the first time.Therefore, it is particularly important to establish accurate simulation models for the study of SEE.
As shown in Figure 1, the SEU simulation research of SRAM can be divided into device level, mixed level and circuit level, according to the research methods.Each of the three research methods has its own advantages and disadvantages [5,6].The circuit-level simulation simulates the single event transient (SET) current generated by adding a pulsed current source model to the sensitive nodes to obtain the voltage variation at each node of the circuit during single-particle incidence [7].The advantage of this approach is its fast simulation speed and simplicity.However, it neglects the impact of the changing electrode voltages of the irradiated device on the bipolar amplification effect, which in turn affects the magnitude of the SET current.The electrode voltage of the incident device affects the magnitude of the SET current.The incident of single particle makes the electrode voltage of the device change dynamically, which leads to a dynamic change in the SET current.Therefore, it is deficient to describe the single event transient pulse current only by a fixed pulse current source.Based on the circuit level simulation, the mixed level simulation replaces the model of the incident device with the device level model, and the remaining devices adopt the circuit level model [8].This method takes into account the influence of the device electrode voltage on the SET current while ensuring the speed of circuit simulation.
Compared with the circuit level simulation, the results are more realistic.However, since only the incident devices in the circuit are modeled at the device level and the devices are connected to each other by electrodes, the charge sharing effect and SEMU cannot be described.The device level simulation is achieved by unified device level modeling of the SRAM circuit as a whole [9].Among the three methods, device level simulation provides the most accurate and realistic results.However, device level simulation is the slowest and requires a lot of time, and complex models may lead to non-convergence of the simulation.As shown in Figure 1, the SEU simulation research of SRAM can be divided into device level, mixed level and circuit level, according to the research methods.Each of the three research methods has its own advantages and disadvantages [5,6].The circuit-level simulation simulates the single event transient (SET) current generated by adding a pulsed current source model to the sensitive nodes to obtain the voltage variation at each node of the circuit during single-particle incidence [7].The advantage of this approach is its fast simulation speed and simplicity.However, it neglects the impact of the changing electrode voltages of the irradiated device on the bipolar amplification effect, which in turn affects the magnitude of the SET current.The electrode voltage of the incident device affects the magnitude of the SET current.The incident of single particle makes the electrode voltage of the device change dynamically, which leads to a dynamic change in the SET current.Therefore, it is deficient to describe the single event transient pulse current only by a fixed pulse current source.Based on the circuit level simulation, the mixed level simulation replaces the model of the incident device with the device level model, and the remaining devices adopt the circuit level model [8].This method takes into account the influence of the device electrode voltage on the SET current while ensuring the speed of circuit simulation.Compared with the circuit level simulation, the results are more realistic.However, since only the incident devices in the circuit are modeled at the device level and the devices are connected to each other by electrodes, the charge sharing effect and SEMU cannot be described.The device level simulation is achieved by unified device level modeling of the SRAM circuit as a whole [9].Among the three methods, device level simulation provides the most accurate and realistic results.However, device level simulation is the slowest and requires a lot of time, and complex models may lead to nonconvergence of the simulation.In this paper, an SEU simulation at SRAM circuit level and device level is implemented by Hspice and Synopsys technology computer aided design (TCAD) Sentaurus simulator.The results of the two methods are compared to analyze the effect of charge sharing on the flip threshold of a 22 nm FDSOI SRAM cell.This paper can improve the accuracy of SEU prediction and lay a foundation for the SRAM reinforcement design of advanced technology.

Device Structure
The NMOS (N-type Metal-Oxide-Semiconductor), Field Effect Transistor (NFET), and PMOS (P-type Metal-Oxide-Semiconductor) Field Effect Transistor (PFET) with FDSOI structure are built by Synopsys TCAD Sentaurus simulator based on the layout size parameters of process design kits (PDK) in 22 nm FDSOI process provided by Global Foundries, and Figure 2 shows the three-dimensional (3D) structure of the devices.The source and drain regions of the device adopt Gaussian doping distribution, and HfO2 with high dielectric constant is added to thin silicon dioxide (SiO2) gate oxide to reduce gate In this paper, an SEU simulation at SRAM circuit level and device level is implemented by Hspice and Synopsys technology computer aided design (TCAD) Sentaurus simulator.The results of the two methods are compared to analyze the effect of charge sharing on the flip threshold of a 22 nm FDSOI SRAM cell.This paper can improve the accuracy of SEU prediction and lay a foundation for the SRAM reinforcement design of advanced technology.

Device Structure
The NMOS (N-type Metal-Oxide-Semiconductor), Field Effect Transistor (NFET), and PMOS (P-type Metal-Oxide-Semiconductor) Field Effect Transistor (PFET) with FDSOI structure are built by Synopsys TCAD Sentaurus simulator based on the layout size parameters of process design kits (PDK) in 22 nm FDSOI process provided by Global Foundries, and Figure 2 shows the three-dimensional (3D) structure of the devices.The source and drain regions of the device adopt Gaussian doping distribution, and HfO 2 with high dielectric constant is added to thin silicon dioxide (SiO 2 ) gate oxide to reduce gate leakage current and improve channel mobility.More detailed parameters are listed in Table 1.
The transfer characteristic curve of PDK is obtained by calling the 22 nm FDSOI process library using Hspice (Version R-2020.12)simulation software to calibrate the device model.The calibration results are shown in Figure 3, and the direct current (DC) parameters extracted from the curve are shown in Table 2.
leakage current and improve channel mobility.More detailed parameters are listed in Table 1.The transfer characteristic curve of PDK is obtained by calling the 22 nm FDSOI process library using Hspice (Version R-2020.12)simulation software to calibrate the device model.The calibration results are shown in Figure 3, and the direct current (DC) parameters extracted from the curve are shown in Table 2.The transfer characteristic curve of PDK is obtained by calling the 22 nm FDS cess library using Hspice (Version R-2020.12)simulation software to calibrate the model.The calibration results are shown in Figure 3, and the direct current (DC) p ters extracted from the curve are shown in Table 2.According to the layout structure of 6T-SRAM in PDK, the 6T-SRAM device model is established in 1:1 ratio.The 6T-SRAM device model uses the same doping settings as the FDSOI NFET and PFET.As shown in Figure 4, in an SRAM layout, adjacent NEFTs merge their active regions based on the circuit's connectivity, forming a source-drain sharing structure [10].This is a key distinction between the single-device model and the multi-device model.The read and write simulation of SRAM is carried out, and the noise tolerance of SRAM is further obtained as shown in Figure 5.By simulating the read and write of SRAM, the noise tolerance of SRAM is shown in Figure 5.According to the layout structure of 6T-SRAM in PDK, the 6T-SRAM device model is established in 1:1 ratio.The 6T-SRAM device model uses the same doping settings as the FDSOI NFET and PFET.As shown in Figure 4, in an SRAM layout, adjacent NEFTs merge their active regions based on the circuit's connectivity, forming a source-drain sharing structure [10].This is a key distinction between the single-device model and the multidevice model.The read and write simulation of SRAM is carried out, and the noise tolerance of SRAM is further obtained as shown in Figure 5.By simulating the read and write of SRAM, the noise tolerance of SRAM is shown in Figure 5.

SET Current Extraction
For FDSOI devices, the direction, angle, energy, and ambient temperature of the single particle incident have an effect on the SET current.In the study of SET, a linear energy According to the layout structure of 6T-SRAM in PDK, the 6T-SRAM is established in 1:1 ratio.The 6T-SRAM device model uses the same dopi the FDSOI NFET and PFET.As shown in Figure 4, in an SRAM layout, ad merge their active regions based on the circuit's connectivity, forming a sour ing structure [10].This is a key distinction between the single-device model device model.The read and write simulation of SRAM is carried out, and th ance of SRAM is further obtained as shown in Figure 5.By simulating the r of SRAM, the noise tolerance of SRAM is shown in Figure 5.

SET Current Extraction
For FDSOI devices, the direction, angle, energy, and ambient temperat gle particle incident have an effect on the SET current.In the study of SET, a

SET Current Extraction
For FDSOI devices, the direction, angle, energy, and ambient temperature of the single particle incident have an effect on the SET current.In the study of SET, a linear energy transfer (LET) is introduced to describe the energy lost per unit length of the particle passing through the target material.The expression is shown in Equation ( 1): where ρ is the density of the semiconductor material, E is the energy of the incident particle, and x is the trajectory distance generated by the incident particle.The common units of LET are MeV • cm 2 /mg and pc/µm, and the conversion relationship is shown in Equation ( 2): The density of silicon is 2.33 g/cm 3 , and the ions produce one electron-hole pair for every 3.6 eV of energy lost on the silicon substrate [11].The electron-hole pair produced by a single particle incidence can be expressed by Equation (3): It is shown that the peak value of the SET current generated by the single particle at the position of high field strength and long particle trajectory is the largest [8,12].As shown in Figure 6, when the incident position is selected as the drain to channel junction, the incident angle is 60 • oblique incidence and the device is in an off-state state; with an incident radius of 15 nm, the obtained SET current is the worst case.The incident radius corresponds to the scattering radius within the device.Under this condition, the SET current under a different LET is simulated, and the results are shown in Figure 7.
transfer (LET) is introduced to describe the energy lost per unit length of the particle passing through the target material.The expression is shown in Equation ( 1): where ρ is the density of the semiconductor material, E is the energy of the incident particle, and x is the trajectory distance generated by the incident particle.
The density of silicon is 2.33 g/cm 3 , and the ions produce one electron-hole pair for every 3.6 eV of energy lost on the silicon substrate [11].The electron-hole pair produced by a single particle incidence can be expressed by Equation (3): It is shown that the peak value of the SET current generated by the single particle at the position of high field strength and long particle trajectory is the largest [8,12].As shown in Figure 6, when the incident position is selected as the drain to channel junction, the incident angle is 60° oblique incidence and the device is in an off-state state; with an incident radius of 15 nm, the obtained SET current is the worst case.The incident radius corresponds to the scattering radius within the device.Under this condition, the SET current under a different LET is simulated, and the results are shown in Figure 7.With the increase in LET, the peak current of the SET currents is also increasing, and the pulse width is also larger [13].There is a positive correlation between the LET and SET transfer (LET) is introduced to describe the energy lost per unit length of the particle passing through the target material.The expression is shown in Equation ( 1): where ρ is the density of the semiconductor material, E is the energy of the incident particle, and x is the trajectory distance generated by the incident particle.
The density of silicon is 2.33 g/cm 3 , and the ions produce one electron-hole pair for every 3.6 eV of energy lost on the silicon substrate [11].The electron-hole pair produced by a single particle incidence can be expressed by Equation (3): It is shown that the peak value of the SET current generated by the single particle at the position of high field strength and long particle trajectory is the largest [8,12].As shown in Figure 6, when the incident position is selected as the drain to channel junction, the incident angle is 60° oblique incidence and the device is in an off-state state; with an incident radius of 15 nm, the obtained SET current is the worst case.The incident radius corresponds to the scattering radius within the device.Under this condition, the SET current under a different LET is simulated, and the results are shown in Figure 7.With the increase in LET, the peak current of the SET currents is also increasing, and the pulse width is also larger [13].There is a positive correlation between the LET and SET With the increase in LET, the peak current of the SET currents is also increasing, and the pulse width is also larger [13].There is a positive correlation between the LET and SET currents.This can be attributed to the fact that as the LET increases, heavier ions lose more energy per unit length within the device.Consequently, this results in a higher generation of electron-hole pairs, thereby enhancing the charge collection at the drain and ultimately leading to an improved peak current of SET.
The single particle current is fitted by the Weibull model.The Weibull function has great flexibility in fitting random data, and can well describe the complex transient current waveform caused by SET [14], as expressed in Equation (4).
The three-parameter Weibull model is used, where t is the time, and a, b, c are the three parameters introduced.As shown in Figure 8, for any SET current, H represents the pulse peak, t p represents the time when the current pulse reaches the peak, A represents the integration of the current pulse and time, and A p represents the integration of the current pulse in the period of 0~t p .The Weibull function is described by three important parameters a, b and c, and the expression is shown in Equation (5).
Micromachines 2023, 14, x FOR PEER REVIEW 6 of 13 currents.This can be attributed to the fact that as the LET increases, heavier ions lose more energy per unit length within the device.Consequently, this results in a higher generation of electron-hole pairs, thereby enhancing the charge collection at the drain and ultimately leading to an improved peak current of SET.
The single particle current is fitted by the Weibull model.The Weibull function has great flexibility in fitting random data, and can well describe the complex transient current waveform caused by SET [14], as expressed in Equation ( 4).
The three-parameter Weibull model is used, where t is the time, and a, b, c are the three parameters introduced.As shown in Figure 8, for any SET current, H represents the pulse peak, tp represents the time when the current pulse reaches the peak, A represents the integration of the current pulse and time, and Ap represents the integration of the current pulse in the period of 0~tp.The Weibull function is described by three important parameters a, b and c, and the expression is shown in Equation ( 5). ( )

6T-SRAM Single Event Upset
The 6T-SRAM circuit is built by a Hspice simulator.As shown in Figure 9, the circuit consists of six transistors, of which M2 and M4 are PFETs, and the remaining transistors are NFETs.The transistor parameter settings are shown in Table 3.The voltage of the circuit node is determined by the word line (WL) and the bit lines (BL, BLN).When the WL is high, M5 and M6 conduct, making the potential of the Q and Qn points change.M1 and M2, M3, and M4 constitute two inverters, respectively.They form a head-to-tail structure to ensure that the potentials of Q and Qn are always opposite.When the Q is high, the Qn is bound to be low, and vice versa.

6T-SRAM Single Event Upset
The 6T-SRAM circuit is built by a Hspice simulator.As shown in Figure 9, the circuit consists of six transistors, of which M2 and M4 are PFETs, and the remaining transistors are NFETs.The transistor parameter settings are shown in Table 3.The voltage of the circuit node is determined by the word line (WL) and the bit lines (BL, BLN).When the WL is high, M5 and M6 conduct, making the potential of the Q and Q n points change.M1 and M2, M3, and M4 constitute two inverters, respectively.They form a head-to-tail structure to ensure that the potentials of Q and Q n are always opposite.When the Q is high, the Q n is bound to be low, and vice versa.As shown in Figure 10, Q, as a sensitive node in SRAM circuit, is vulnerable to single event bombardment, resulting in logic flipping of the circuit [15].M3 is selected as the single event injection device, and the Weibull current source model is added at the Q to simulate the SET current.The variation of the SRAM node voltage is shown in Figure 11.As shown in Figure 10, Q, as a sensitive node in SRAM circuit, is vulnerable to single event bombardment, resulting in logic flipping of the circuit [15].M3 is selected as the single event injection device, and the Weibull current source model is added at the Q to simulate the SET current.The variation of the SRAM node voltage is shown in Figure 11.As shown in Figure 10, Q, as a sensitive node in SRAM circuit, is vulnerable to single event bombardment, resulting in logic flipping of the circuit [15].M3 is selected as the single event injection device, and the Weibull current source model is added at the Q to simulate the SET current.The variation of the SRAM node voltage is shown in Figure 11.As shown in Figure 10, Q, as a sensitive node in SRAM circuit, is vulnerable to event bombardment, resulting in logic flipping of the circuit [15].M3 is selected single event injection device, and the Weibull current source model is added at th simulate the SET current.The variation of the SRAM node voltage is shown in Figu  When the LET = 0.01 pc/µm SET current is added to the Q node, the voltage of the Q and Q n nodes changes but finally returns to the initial state, and the level logic does not change.The whole process lasts about 25 ns.It shows that the 6T SRAM circuit has the ability to resist SET, and can recover itself to its original state without SEU under the SET current of LET = 0.024 pc/µm.When using a current model with a LET greater than or equal to 0.026 pc/µm, the potentials of the Q and Q n nodes in the SRAM do not return to their initial potentials, and SEU occurs.The current is integrated to obtain the charge collected by the device during the single-particle incident period, which is the critical charge of the device.When the charge collected by the device is greater than the critical charge, the circuit will initiate SEU.Table 4 is the accumulated under a different LET value.From the analysis of Figures 11 and 12, it can be seen that the LET upset threshold of the 6T SRAM circuit is in the range of 0.024~0.026pc/µm, and the critical charge range is 0.274~0.298fC.their initial potentials, and SEU occurs.The current is integrated to obtain the cha lected by the device during the single-particle incident period, which is the critica of the device.When the charge collected by the device is greater than the critical the circuit will initiate SEU.Table 4 is the accumulated charge under a different LE From the analysis of Figures 11 and 12, it can be seen that the LET upset threshol 6T SRAM circuit is in the range of 0.024~0.026pc/μm, and the critical charge 0.274~0.298fC.

SRAM Device Level SEE Simulation
SRAM device level simulation uses the same single-event incidence condition circuit level simulation.As shown in Figure 13, the voltage variation of the SRA considering the charge sharing case is obtained by performing a 60° oblique incid the junction of the drain and channel of the M3 device.The voltage change in the is shown in Figure 14, and the heavy ion charge density is shown in Figure 15.

SRAM Device Level SEE Simulation
SRAM device level simulation uses the same single-event incidence conditions as the circuit level simulation.As shown in Figure 13, the voltage variation of the SRAM node considering the charge sharing case is obtained by performing a 60 • oblique incidence at the junction of the drain and channel of the M3 device.The voltage change in the Q node is shown in Figure 14, and the heavy ion charge density is shown in Figure 15.The results show that the charge sharing effect causes the SRAM circuit to be more prone to SEU.In the SRAM device level simulation, the logic flip occurs when the Q node is incident by a single particle with an LET of 0.022 pc/μm.Comparing the current of the Q node in the SRAM circuit with the SET current of FDSOI, the results are shown in Figure 16.The LET flip threshold is in the range of 0.02~0.022pc/μm, and the critical charge is in the range of 0.211~0.228fC.Compared with the circuit level simulation results, the LET flip threshold is reduced by 15.4%, and the critical charge is reduced by 23.5%.The sharing of active regions in an SRAM circuit leads to an increased area of sensitive regions (the drain regions of M1 and M3), indirectly raising the probability of being impacted by a single particle.When a single particle enters M5 (or M6), the electron-hole pairs generated in the drain region of M5 (or M6) will be collected by the drain electrode of M1 (or M3).This phenomenon occurs due to the sharing of active regions in the SRAM layout.Due to the presence of a BOX layer, the impact of electron-hole pairs in the substrate on the transistor is minimal.However, for the top silicon layer, the electrons and holes generated by the incident device can move through the shared active region, enabling charge sharing.The results show that the charge sharing effect causes the SRAM circuit to be more prone to SEU.In the SRAM device level simulation, the logic flip occurs when the Q node is incident by a single particle with an LET of 0.022 pc/μm.Comparing the current of the Q node in the SRAM circuit with the SET current of FDSOI, the results are shown in Figure 16.The LET flip threshold is in the range of 0.02~0.022pc/μm, and the critical charge is in the range of 0.211~0.228fC.Compared with the circuit level simulation results, the LET flip threshold is reduced by 15.4%, and the critical charge is reduced by 23.5%.The sharing of active regions in an SRAM circuit leads to an increased area of sensitive regions (the drain regions of M1 and M3), indirectly raising the probability of being impacted by a single particle.When a single particle enters M5 (or M6), the electron-hole pairs generated in the drain region of M5 (or M6) will be collected by the drain electrode of M1 (or M3).This phenomenon occurs due to the sharing of active regions in the SRAM layout.Due to the presence of a BOX layer, the impact of electron-hole pairs in the substrate on the transistor is minimal.However, for the top silicon layer, the electrons and holes generated by the incident device can move through the shared active region, enabling charge sharing.The results show that the charge sharing effect causes the SRAM circuit to be more prone to SEU.In the SRAM device level simulation, the logic flip occurs when the Q node is incident by a single particle with an LET of 0.022 pc/µm.Comparing the current of the Q node in the SRAM circuit with the SET current of FDSOI, the results are shown in Figure 16.The LET flip threshold is in the range of 0.02~0.022pc/µm, and the critical charge is in the range of 0.211~0.228fC.Compared with the circuit level simulation results, the LET flip threshold is reduced by 15.4%, and the critical charge is reduced by 23.5%.The sharing of active regions in an SRAM circuit leads to an increased area of sensitive regions (the drain regions of M1 and M3), indirectly raising the probability of being impacted by a single particle.When a single particle enters M5 (or M6), the electron-hole pairs generated in the drain region of M5 (or M6) will be collected by the drain electrode of M1 (or M3).This phenomenon occurs due to the sharing of active regions in the SRAM layout.Due to the presence of a BOX layer, the impact of electron-hole pairs in the substrate on the transistor is minimal.However, for the top silicon layer, the electrons and holes generated by the incident device can move through the shared active region, enabling charge sharing.
At the same LET, the pulse current generated by the single-event incidence of the FDSOI device is greater than the current obtained from the SRAM device-level simulation.This discrepancy is caused by the bipolar amplification effect.In addition to the incident angle, position, and direction of particles, the bias state of the device being irradiated also influences the bipolar amplification effect, thereby indirectly affecting the SET current.At the same LET, the pulse current generated by the single-event incidence of the FDSOI device is greater than the current obtained from the SRAM device-level simulation.This discrepancy is caused by the bipolar amplification effect.In addition to the incident angle, position, and direction of particles, the bias state of the device being irradiated also influences the bipolar amplification effect, thereby indirectly affecting the SET current.When an SRAM circuit is in the hold state, assuming the Q node voltage is Vdd, both M6 and M3 are in an off state since the drain of M6 is connected to the drain of M3.When a single particle impacts M6, the ionization generates electrons that drift under the influence of the applied electric field and eventually get collected by the drain (Q).The holes generated within the bulk region, due to their low mobility, partly recombine with electrons in the bulk region, while the remaining portion remains in the bulk region.This causes an increase in the potential of the bulk region, lowering the source/bulk junction barrier and allowing electron injection from the source region into the channel.These electrons can also be collected by the drain, increasing the total amount of charge collected at the drain and resulting in bipolar amplification.This highlights the inadequacy of using non-coupled circuit-level simulations and emphasizes the necessity of employing coupled device-level simulations or hybrid-level simulations to accurately evaluate the circuit's resistance to SEU.Circuit-level simulations, which do not account for these factors, fail to properly assess the ability of the circuit to withstand SEU.Due to the shared active region in the SRAM layout, neighboring devices are also influenced when a single particle enters an individual device [16,17].The sharing of active regions in an SRAM circuit leads to an increased area of sensitive regions (the drain regions of M1 and M3), indirectly raising the probability of being impacted by a single particle.When a single particle enters M5 (or M6), the electron-hole pairs generated in the drain region of M5 (or M6) will be collected by the drain electrode of M1 (or M3).This phenomenon occurs due to the sharing of active regions in the SRAM layout.Due to the presence of a BOX layer, the impact of electron-hole pairs in the substrate on the transistor is minimal.However, for the top silicon layer, the electrons and holes generated by the incident device can move through the shared active region, enabling charge sharing.Furthermore, experimental results [18] also demonstrate the existence of charge-sharing effects in FDSOI SRAM.This indicates that the decrease in the LET upset threshold observed in device level simulations of SRAM is a result of the combined effects of charge sharing and bipolar amplification.
To study the effect of the trajectory radius of particle incidence on the SEU of SRAM, heavy ion with radii of 15 nm and 50 nm are used for incidence.The incidence position is the junction of the M3 device drain and channel, the incidence direction is vertical incidence, and the heavy ion charge density is shown in Figure 18, and the Q node voltage and current of SRAM are shown in Figures 19 and 20  When an SRAM circuit is in the hold state, assuming the Q node voltage is Vdd, both M6 and M3 are in an off state since the drain of M6 is connected to the drain of M3.When a single particle impacts M6, the ionization generates electrons that drift under the influence of the applied electric field and eventually get collected by the drain (Q).The holes generated within the bulk region, due to their low mobility, partly recombine with electrons in the bulk region, while the remaining portion remains in the bulk region.This causes an increase in the potential of the bulk region, lowering the source/bulk junction barrier and allowing electron injection from the source region into the channel.These electrons can also be collected by the drain, increasing the total amount of charge collected at the drain and resulting in bipolar amplification.This highlights the inadequacy of using non-coupled circuit-level simulations and emphasizes the necessity of employing coupled device-level simulations or hybrid-level simulations to accurately evaluate the circuit's resistance to SEU.Circuit-level simulations, which do not account for these factors, fail to properly assess the ability of the circuit to withstand SEU.
Due to the shared active region in the SRAM layout, neighboring devices are also influenced when a single particle enters an individual device [16,17].The sharing of active regions in an SRAM circuit leads to an increased area of sensitive regions (the drain regions of M1 and M3), indirectly raising the probability of being impacted by a single particle.When a single particle enters M5 (or M6), the electron-hole pairs generated in the drain region of M5 (or M6) will be collected by the drain electrode of M1 (or M3).This phenomenon occurs due to the sharing of active regions in the SRAM layout.Due to the presence of a BOX layer, the impact of electron-hole pairs in the substrate on the transistor is minimal.However, for the top silicon layer, the electrons and holes generated by the incident device can move through the shared active enabling charge sharing.Furthermore, experimental results [18] also demonstrate the existence of charge-sharing effects in FDSOI SRAM.This indicates that the decrease in the LET upset threshold observed in device level simulations of SRAM is a result of the combined effects of charge sharing and bipolar amplification.
To study the effect of the trajectory radius of particle incidence on the SEU of SRAM, heavy ion with radii of 15 nm and 50 nm are used for incidence.The incidence position is the junction of the M3 device drain and channel, the incidence direction is vertical incidence, and the heavy ion charge density is shown in Figure 18, and the Q node voltage and current of SRAM are shown in Figures 19 and 20.
regions in an SRAM circuit leads to an increased area of sensitive regions (the drain regions of M1 and M3), indirectly raising the probability of being impacted by a single particle.When a single particle enters M5 (or M6), the electron-hole pairs generated in the drain region of M5 (or M6) will be collected by the drain electrode of M1 (or M3).This phenomenon occurs due to the sharing of active regions in the SRAM layout.Due to the presence of a BOX layer, the impact of electron-hole pairs in the substrate on the transistor is minimal.However, for the top silicon layer, the electrons and holes generated by the incident device can move through the shared active region, enabling charge sharing.Furthermore, experimental results [18] also demonstrate the existence of charge-sharing effects in FDSOI SRAM.This indicates that the decrease in the LET upset threshold observed in device level simulations of SRAM is a result of the combined effects of charge sharing and bipolar amplification.
To study the effect of the trajectory radius of particle incidence on the SEU of SRAM, heavy ion with radii of 15 nm and 50 nm are used for incidence.The incidence position is the junction of the M3 device drain and channel, the incidence direction is vertical incidence, and the heavy ion charge density is shown in Figure 18, and the Q node voltage and current of SRAM are shown in Figures 19 and 20    At the same incident energy, the incident particles with a small radius can worse results.Because the particle radius is smaller, the generated heavy ion charg sity is larger, and the peak of the SET current will be larger, resulting in the SRAM being more prone to logic flip.

Conclusions
In this paper, the circuit level and device level simulation of 6T-SRAM SEU ar pared.It is found that the SEU threshold of the SRAM circuit obtained by the Hspi  At the same incident energy, the incident particles with a small radius can cause worse results.Because the particle radius is smaller, the generated heavy ion charge density is larger, and the peak of the SET current will be larger, resulting in the SRAM circuit being more prone to logic flip.

Conclusions
In this paper, the circuit level and device level simulation of 6T-SRAM SEU are compared.It is found that the SEU threshold of the SRAM circuit obtained by the Hspice sim- At the same incident energy, the incident particles with a small radius can cause worse results.Because the particle radius is smaller, the generated heavy ion charge density is larger, and the peak of the SET current will be larger, resulting in the SRAM circuit being more prone to logic flip.

Figure 1 .
Figure 1.Simulation method of SRAM single event effect: (a) circuit level; (b) mixed level; (c) device level.

Figure 1 .
Figure 1.Simulation method of SRAM single event effect: (a) circuit level; (b) mixed level; (c) device level.

Figure 3 .
Figure 3.Comparison of transfer characteristics of drain current for (a) NFET and (b) PFET with the PDK data.

Figure 3 .
Figure 3.Comparison of transfer characteristics of drain current for (a) NFET and (b) PFET PDK data.

Figure 3 .
Figure 3.Comparison of transfer characteristics of drain current for (a) NFET and (b) PFET with the PDK data.

Figure 6 .
Figure 6.The worst condition of single particle incidence.

Figure 7 .
Figure 7. SET currents with different LET values under the worst-case condition.

Figure 6 .
Figure 6.The worst condition of single particle incidence.

Figure 6 .
Figure 6.The worst condition of single particle incidence.

Figure 7 .
Figure 7. SET currents with different LET values under the worst-case condition.

Figure 7 .
Figure 7. SET currents with different LET values under the worst-case condition.

Figure 8 .
Figure 8. Schematic diagram of SET current.

Figure 8 .
Figure 8. Schematic diagram of SET current.

Figure 12 .
Figure 12.Collected charge for different pulse currents.

Figure 15 .
Figure 15.The charge density of heavy ions produced by particle incidence.

Figure 14 .
Figure 14.SRAM node voltage variation considering charge sharing effect.

Figure 14 .
Figure 14.SRAM node voltage variation considering charge sharing effect.

Figure 15 .
Figure 15.The charge density of heavy ions produced by particle incidence.

Figure 15 .
Figure 15.The charge density of heavy ions produced by particle incidence.
Figure 17 presents SET currents generated by heavy ion irradiation in FDSOI under different drain biases.The results demonstrate that varying drain bias voltages result in different peak values of the SET current.During simulations of FDSOI devices, the drain voltage of the device is fixed.In the simulation, the drain voltage of the FDSOI (equivalent to the Q node in SRAM circuit) and the added current model are independent of each other, and the change in the Q point voltage has no effect on the pulse current.But in fact, with the change in the Q point voltage, the SET current also changes.The larger the drain voltage of the device, the larger the SET current, and vice versa.

Figure 16 .
Figure 16.The comparison the Q node current of SRAM circuit and the SET current of FDSOI.
Figure 17 presents SET currents generated by heavy ion irradiation in FDSOI under different drain biases.The results demonstrate that varying drain bias voltages result in different peak values of the SET current.During simulations of FDSOI devices, the drain voltage of the device is fixed.In the simulation, the drain voltage of the FDSOI (equivalent to the Q node in SRAM circuit) and the added current model are independent of each other, and the change in the Q point voltage has no effect on the pulse current.But in fact, with the change in the Q point voltage, the SET current also changes.The larger the drain voltage of the device, the larger the SET current, and vice versa.

Figure 16 . 13 Figure 17 .
Figure 16.The comparison between the Q node current of SRAM circuit and the SET current of FDSOI.Micromachines 2023, 14, x FOR PEER REVIEW 11 of 13 .

Figure 17 .
Figure 17.The SET current of FDSOI devices with different drain voltage biases. .

Figure 20 .
Figure 20.Q node voltage variation of SRAM circuits with different incidence radii: (a) 15 50 nm.

Table 1 .
Device parameters used for simulation of NFET and PFET devices.

Table 1 .
Device parameters used for simulation of NFET and PFET devices.

Table 1 .
Device parameters used for simulation of NFET and PFET devices.

Table 2 .
DC parameters of the devices.

Table 4 .
Collected charge for different pulse currents.

Table 4 .
Collected charge for different pulse currents.
Figure 12.Collected charge for different pulse currents.