Research on Surface Morphology of Gold Micro Bumps Based on Monte Carlo Method

In advanced packaging technology, the micro bump has become an important means of chip stacking and wafer interconnection. The reliability of micro bumps, which plays an important role in mechanical support, electrical connection, signal transmission and heat dissipation, determines the quality of chip packaging. Surface morphological defects are one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. In this paper, the electrodeposition process of preparing gold bumps is simulated at the atomic scale using the Kinetic Monte Carlo method. The differences in surface morphology and roughness of the plated layer are studied from a microscopic perspective under different deposition parameters. The results show that the gold micro bumps prepared by electrodeposition have better surface quality under conditions of lower deposition voltage, lower ion concentration and higher plating temperature, which can provide significant guidance for engineering applications.


Introduction
As the level of technology continues to increase, the feature size of transistors is approaching the physical limit and it is becoming increasingly difficult to follow Moore's law [1,2]. Although integrated circuit manufacturers have adopted new technology development and other means, they still cannot meet the current demand for high-performance, miniaturization, intelligence, and low power consumption in electronic devices. The emergence of microsystems provides an important pathway from monolithic integrated planar structure to multi-chip integrated three-dimensional structure. The development of advanced packaging technology provides a technical guarantee for microsystems, and the technical route has evolved from three-dimensional system-level packaging (3D-SiP) to threedimensional wafer-level packaging (3D-WLP), which has reached the three-dimensional integrated circuit stage (3D-IC) [3]. Advanced packaging, compared with traditional packaging, has characteristics of increased interconnect density, reduced interconnect distance and package level system reconfiguration, etc. [4]. The advanced packaging technical route and characteristics are shown in Figure 1.
The micro bump has become a key technology in advanced packaging structures. Due to its fine pitch and micro-size characteristics, it is widely used in the packaging and integration of CMOS image sensors, HB LED modules, stacked memories, Logic + MemorySiP, Logic and Analog 3D SOC/Sip, etc. [5][6][7][8]. Taking a typical 2.5 D advanced package as an example, CoWoS (chip on wafer on substrate) is a packaging structure based on a silicon adapter board and TSV technology and launched by TSMC in 2012 [9,10]. As shown in Figure 2, logic chips with the same or different functions are interconnected at ultra-short intervals through micro bumps to reduce heat generation and parasitic resistors and capacitors, to achieve the goal of small size, low power consumption, and fewer pins.  Micro bumps play an important role in mechanical support, electrical connection, signal transmission, and heat dissipation in advanced packaging, and their reliability determines the quality of chip packages and even electronic products. Surface morphological defect is one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. The bump formation process is influenced by the coupling effect of multiple physical fields such as heat, force, and electricity. With the development of micro bump bonding towards high-density and ultrafine spacing, the microscale effect becomes more apparent [11,12]. With the new features such as lead-free materials and Low K materials, the thermal stress mismatch during the bonding process becomes more severe, which further affects the surface quality of the bumps. The performance of bumps is determined mainly by the material, and selecting the appropriate material is particularly important for improving the reliability and quality of the bumps. Generally, the surface morphology of the micro bump should be flat and consistent. Surface morphology defects of micro bumps refer to rough grain morphology at the interface of micro bumps, resulting in significant IMC coarsening and poor shear performance of micro bumps. Due to periodic changes in temperature during the service of electronic products, the upper and lower surfaces of micro bumps will experience relative motion. As the shear performance of the micro bumps is poor, it will lead to a poor ability to withstand the thermal mismatch between the chip and the substrate, resulting in a decrease in thermal fatigue reliability.
According to the material, bumps can be divided into solder bumps and non-solder bumps. Solder bumps are mainly made of tin-based materials, including SnPb solder and lead-free solders such as SnCu, SnAg, and SnZn; non-solder bumps mainly include Au bumps, Cu bumps, and In bumps [13,14]. The main methods of micro bump preparation include electrodeposition, screen printing, solder injection and evaporation [15,16]. The  parasitic resistors and capacitors, to achieve the goal of small size, low power consumption, and fewer pins.  Micro bumps play an important role in mechanical support, electrical connection, signal transmission, and heat dissipation in advanced packaging, and their reliability determines the quality of chip packages and even electronic products. Surface morphological defect is one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. The bump formation process is influenced by the coupling effect of multiple physical fields such as heat, force, and electricity. With the development of micro bump bonding towards high-density and ultrafine spacing, the microscale effect becomes more apparent [11,12]. With the new features such as lead-free materials and Low K materials, the thermal stress mismatch during the bonding process becomes more severe, which further affects the surface quality of the bumps. The performance of bumps is determined mainly by the material, and selecting the appropriate material is particularly important for improving the reliability and quality of the bumps. Generally, the surface morphology of the micro bump should be flat and consistent. Surface morphology defects of micro bumps refer to rough grain morphology at the interface of micro bumps, resulting in significant IMC coarsening and poor shear performance of micro bumps. Due to periodic changes in temperature during the service of electronic products, the upper and lower surfaces of micro bumps will experience relative motion. As the shear performance of the micro bumps is poor, it will lead to a poor ability to withstand the thermal mismatch between the chip and the substrate, resulting in a decrease in thermal fatigue reliability.
According to the material, bumps can be divided into solder bumps and non-solder bumps. Solder bumps are mainly made of tin-based materials, including SnPb solder and lead-free solders such as SnCu, SnAg, and SnZn; non-solder bumps mainly include Au bumps, Cu bumps, and In bumps [13,14]. The main methods of micro bump preparation include electrodeposition, screen printing, solder injection and evaporation [15,16]. The Micro bumps play an important role in mechanical support, electrical connection, signal transmission, and heat dissipation in advanced packaging, and their reliability determines the quality of chip packages and even electronic products. Surface morphological defect is one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. The bump formation process is influenced by the coupling effect of multiple physical fields such as heat, force, and electricity. With the development of micro bump bonding towards high-density and ultra-fine spacing, the microscale effect becomes more apparent [11,12]. With the new features such as lead-free materials and Low K materials, the thermal stress mismatch during the bonding process becomes more severe, which further affects the surface quality of the bumps. The performance of bumps is determined mainly by the material, and selecting the appropriate material is particularly important for improving the reliability and quality of the bumps. Generally, the surface morphology of the micro bump should be flat and consistent. Surface morphology defects of micro bumps refer to rough grain morphology at the interface of micro bumps, resulting in significant IMC coarsening and poor shear performance of micro bumps. Due to periodic changes in temperature during the service of electronic products, the upper and lower surfaces of micro bumps will experience relative motion. As the shear performance of the micro bumps is poor, it will lead to a poor ability to withstand the thermal mismatch between the chip and the substrate, resulting in a decrease in thermal fatigue reliability.
According to the material, bumps can be divided into solder bumps and non-solder bumps. Solder bumps are mainly made of tin-based materials, including SnPb solder and lead-free solders such as SnCu, SnAg, and SnZn; non-solder bumps mainly include Au bumps, Cu bumps, and In bumps [13,14]. The main methods of micro bump preparation include electrodeposition, screen printing, solder injection and evaporation [15,16]. The electrodeposition method has been widely used in practical production because of its simple process, low cost, easy mass production, and high adaptability [17,18].
The effects of different process parameters on electrodeposition were investigated experimentally by Xiaobo Liang et al., Ren et al., and Lee et al. [19][20][21]. Due to limits in experimental techniques, it is not feasible to continuously monitor and capture all the information of the plating growth process dynamically [22][23][24], so experimental methods cannot fully reveal the microscopic process of electrodeposition. However, molecular simulation methods on the atomic scale can help us study the metal crystal growth process from a microscopic perspective. Liu et al. and Treeratanaphitak et al. have simulated the electrodeposition process of Cu and Ag using computer models [25,26]. In this paper, based on molecular simulation theory, the electrodeposition process of Au bumps is simulated by the Kinetic Monte Carlo (KMC) method. The bumps' deposition growth process and the morphological structure changes under different process parameters are simulated and analyzed, which can optimize the process parameters and enhance the quality of micro bumps.

Simulation Method
The KMC method has become an important for simulating the study of various problems at the atomic scale. It is widely used by researchers in the fields of annealing and recrystallization, metal crystal growth, biochemical reactions, and heat transfer [27][28][29].
To study the influence of electrodeposition parameters on the growth mechanism of gold bump plating layers, the KMC algorithm model is proposed for simulating the electrodeposition growth of gold bumps in this paper. The kinetic processes of deposition adsorption and diffusion migration of deposited atoms on the surface are considered to recast the growth process of bump electrodeposition at the atomic scale in the early stage. Furthermore, the effects of different process parameters on the growth process and surface morphology are analyzed.
The use of Kinetic Monte Carlo to study the atomic deposition process is based on the assumptions that (1) the position of the atoms in each state can be considered as a point on the ideal lattice during the evolution of the model; (2) the state of motion of each atom in the model is only related to its immediate environment and depends on the action of the immediate neighbors on it. Based on these two points, it is possible to build a probabilistic model consistent with the simulated system and to calculate the rate constants for all possible events.

Deposition Event
There are two important parameters in the algorithm, including deposition rate R d and migration rate R h . The deposition process refers to the reduction of Au+ into Au atoms, which continuously fall down until reaching a stable atomic layer. The deposition rate represents the number of particles deposited on the substrate surface per unit time. In the KMC simulation of the metal electrodeposition process, its calculation formula is as follows [30]: where, K m is the chemical reaction rate constant, C m is the concentration of Au ion in solution, α is the conversion coefficient of metal atoms in the process of base surface deposition, n is the number of ion charges, F a the Faraday constant, V is the deposition voltage, R is the ideal gas constant, and T is the plating temperature.

Migration Event
Atomic migration means that when Au atoms are deposited in a stable atomic layer, they will also move into the gaps of the layer until it is completely filled with Au atoms. Atomic migration rates are calculated using the Arenius formula: where, ν 0 is the transition frequency, usually taken as 10 12 s −1 or 10 13 s −1 in the KMC simulation; ν 0 is selected as 10 12 s −1 in this model. E ik represents the energy barrier to be overcome for the first particle to migrate in k directions, T is the substrate temperature, K B is the Boltzmann constant. The energy barrier that needs to be overcome during the migration process of particles is calculated by embedding the embedded atom model (EAM) [31]. The energy of an atomic system can be expressed as: where F is the energy of an atom embedded in an electron cloud of density ρ i ;ρ i can be viewed as a linear superposition of electron clouds density near the i-th atom in the system; f (r ij ) is the electron clouds density generated by the atom j at the distance r ij ; and r ij is the distance between atoms i and j.
The parameters A 1 , A 2 , c 1 , c 2 and D required in the EAM model can be obtained by fitting the lattice constant, atomic volume, cohesive energy, single vacancy formation energy, bulk modulus and shear modulus. The EAM model selected in this article was proposed by Doyama et al. [32], and the model parameters are shown in Table 1.

Calculation Method for Deposition and Migration Event Probability
The essence of the KMC method is to randomly select the current occurrence of an event at a certain moment based on the weight of the probability of occurrence of each event [33].
The probability of occurrence of the deposition process P d is: The probability of occurrence of the migration process P h is: Micromachines 2023, 14, 1345

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After the migration process occurs, the probability of the i-th migration event occurring among all migration events is: In the program model, the probabilities of all events in the system are calculated first, and then a random number is generated to determine whether the system undergoes deposition or migration [34][35][36]. If a deposition process occurs, the continued generation of random numbers determines the initial position and falling direction of the deposition atoms; If a migration process occurs, a certain atom in the system is randomly selected to complete the migration process based on the probability of each migration event occurring.

Simulation Algorithm Flow
The atom deposition process algorithm based on the KMC method is written in C# using the Visual Studio development platform. The algorithm process can be described as follows. The algorithm flowchart is shown in Figure 3.

Computation Models
As the deposition of the bump plating layer mainly occurs on the UBM (Under Bump Metallization) infiltrating layer, the substrate model of the Au infiltrating layer is constructed in the model first. Then, the deposition and growth of the Au plating layer are simulated and studied based on the model above. The physical evolution behavior between particles in the model includes the diffusion migration behavior of Au + in solution due to electrochemical reduction to atoms deposited on the substrate surface and the diffusion migration behavior of deposited Au atoms on the substrate surface. As the dissolution of deposited atoms is difficult, and as it has little effect on the deposition process, it is not considered in the model. The structure of the deposited atoms is shown in Figure 4, with three colored balls representing three different atomic layers. In the face-centered cubic structure, atoms in different layers are staggered. In the simulation, the size of the substrate is set as 14.419 nm × 14.419 nm. A total of 50,000 Au atoms are deposited on the substrate. The values of the parameters in the simulation are shown in Table 2.  (1) Initialize the substrate structure and calculate the deposition rate R d and migration rate R h arrays. (2) Calculate the probability of each event P i .
(3) Generate a random number 0 < rand 1 < 1 by a random number algorithm. (4) Compare the deposition event probability P d with the random number rand 1 , and if rand 1 < P d , select the deposition event; otherwise, the migration event is selected.

Computation Models
As the deposition of the bump plating layer mainly occurs on the UBM (Under Bump Metallization) infiltrating layer, the substrate model of the Au infiltrating layer is constructed in the model first. Then, the deposition and growth of the Au plating layer are simulated and studied based on the model above. The physical evolution behavior between particles in the model includes the diffusion migration behavior of Au + in solution due to electrochemical reduction to atoms deposited on the substrate surface and the diffusion migration behavior of deposited Au atoms on the substrate surface. As the dissolution of deposited atoms is difficult, and as it has little effect on the deposition process, it is not considered in the model. The structure of the deposited atoms is shown in Figure 4, with three colored balls representing three different atomic layers. In the face-centered cubic structure, atoms in different layers are staggered. In the simulation, the size of the substrate is set as 14.419 nm × 14.419 nm. A total of 50,000 Au atoms are deposited on the substrate. The values of the parameters in the simulation are shown in Table 2.  The process in which Au + in the plating solution is reduced to atoms and deposited on the substrate surface is called a deposition event [37]. Figure 5 shows the different numbers of vacancies in the lower layer of deposited atoms and the direction in which the deposited atoms may fall. The green atoms indicate the deposited atoms in the upper layer, the white atoms indicate that there are no atoms in the lower layer at this position; and the orange atoms indicate that there are atoms in the lower layer of this position.

Analysis and Results
In the simulation model, three process factors on the growth and surface morphology of the electroplated layer are considered, namely the deposition voltage, the temperature of the plating solution and the ion concentration. After the deposition of all the atoms is completed, the coordinate information of all the atoms is counted and output. Then, the three-dimensional topography of the coating atoms is obtained, and the influence of different electrodeposition parameters on the topography of the coating is analyzed.
In the simulation, the surface roughness is used to characterize the surface quality of the deposited film. After the deposition is completed, the coordinate height values of all the surface atoms of the film are extracted, and then the surface roughness is calculated by two measurement methods in precision metrology. The calculation formula are as fol-  The process in which Au + in the plating solution is reduced to atoms and deposited on the substrate surface is called a deposition event [37]. Figure 5 shows the different numbers of vacancies in the lower layer of deposited atoms and the direction in which the deposited atoms may fall. The green atoms indicate the deposited atoms in the upper layer, the white atoms indicate that there are no atoms in the lower layer at this position; and the orange atoms indicate that there are atoms in the lower layer of this position. on the substrate surface is called a deposition event [37]. Figure 5 shows the different numbers of vacancies in the lower layer of deposited atoms and the direction in which the deposited atoms may fall. The green atoms indicate the deposited atoms in the upper layer, the white atoms indicate that there are no atoms in the lower layer at this position and the orange atoms indicate that there are atoms in the lower layer of this position.

Analysis and Results
In the simulation model, three process factors on the growth and surface morphology of the electroplated layer are considered, namely the deposition voltage, the temperature of the plating solution and the ion concentration. After the deposition of all the atoms is completed, the coordinate information of all the atoms is counted and output. Then, the three-dimensional topography of the coating atoms is obtained, and the influence of different electrodeposition parameters on the topography of the coating is analyzed.
In the simulation, the surface roughness is used to characterize the surface quality of the deposited film. After the deposition is completed, the coordinate height values of al the surface atoms of the film are extracted, and then the surface roughness is calculated by two measurement methods in precision metrology. The calculation formula are as follows [38,39]

Analysis and Results
In the simulation model, three process factors on the growth and surface morphology of the electroplated layer are considered, namely the deposition voltage, the temperature of the plating solution and the ion concentration. After the deposition of all the atoms is completed, the coordinate information of all the atoms is counted and output. Then, the three-dimensional topography of the coating atoms is obtained, and the influence of different electrodeposition parameters on the topography of the coating is analyzed.
In the simulation, the surface roughness is used to characterize the surface quality of the deposited film. After the deposition is completed, the coordinate height values of all the surface atoms of the film are extracted, and then the surface roughness is calculated by two measurement methods in precision metrology. The calculation formula are as follows [38,39]: where, R a is the average roughness, R q is the root mean square roughness, Z i is the coordinate height of the i th atom on the film surface, Z is the average of the coordinate heights of all surface atoms, and N is the number of all surface atoms.

Effect of Deposition Voltage on Surface Morphology
In the simulation, the ion concentration C m is set to 0.05 mol/L, the plating temperature (T) is 328 K, and the deposition voltage (V) ranges from −0.8 V to −1.4 V. Figure 6 is a cross-sectional view of the coating atoms along with the x-axis and y-axis directions after the simulation. It can be found that when the deposition voltage is −0.8 V, the atom height distribution on the surface of the deposition layer is relatively uniform, and the surface structure is flat and smooth. As the voltage increases to −1.0 V, small bumps start to appear on the surface of the deposited layer. When the voltage continues to increase to −1.2 V and −1.4 V, the difference in the height of surface atoms increases. The phenomenon of an obvious island-like structure appears, with a large number of vacancies and defects.
cross-sectional view of the coating atoms along with the x-axis and y-axis directions after the simulation. It can be found that when the deposition voltage is −0.8 V, the atom height distribution on the surface of the deposition layer is relatively uniform, and the surface structure is flat and smooth. As the voltage increases to −1.0 V, small bumps start to appear on the surface of the deposited layer. When the voltage continues to increase to −1.2 V and −1.4 V, the difference in the height of surface atoms increases. The phenomenon of an obvious island-like structure appears, with a large number of vacancies and defects.

Effect of Plating Temperature on Surface Morphology
In the simulation, the concentration C m is 0.075 mo1/L, the deposition voltage (V) is 1.0 V, and the variation of the plating temperature (T) is from 298 K to 353 K. The cross-sectional shape of the plating layer after deposition is shown in Figure 8. When the temperature is 298 K, the height distribution of the surface deposition atom is very uneven. A large number of bumps and pits appear, producing a large number of "gullies". As the temperature rises to 323 K, the surface gradually becomes flat, but there is still a certain number of vacancies and defects. As the temperature continues to increase to 343 K and 353 K, the smoothest cross-sections are deposited, with significantly reduced roughness and highly uniform distribution of surface atoms.    Figure 9 shows the results of the simulation surface morphology by the KMC method in this paper compared with those microscopic morphology of the Au layers preparing by Pan Jianling et al. [41] in their Au plating experiments at different plating temperatures. Figure 9a 1 -a 3 show the surface morphologies of the coating obtained at different plating temperatures in the KMC simulation in this paper; Figure 9b 1 -b 3 show the SEM scanning electron surface topography obtained Pan Jianling et al. when preparing Au coatings under different voltages. It can be observed that when the electroplating temperature is 323 K, there are more pores between the grains of the Au coating surface, and the surface morphology is rough, as shown in Figure 9a 1 ,b 1 ; as the plating temperature increases to 343 K, the coating structure becomes dense and flat, and the roughness decreases as shown in Figure 9a 2 ,b 2 ; when the temperature reaches 353 K, the obtained coating surface is the smoothest and the flattest, and the surface quality is the best, as shown in Figure 9a 3

Effect of Ion Concentration on Surface Morphology
Based on the simulation model, the deposition voltage (V) is set as −0.8 V and t temperature of the plating solution (T) is set as 328 K. The Au + concentration in the platin solution is varied to study the effect of different ion concentrations on the electrodepo tion process. Figure 10 shows the cross-sectional view of the coating structure and t image of the surface atom height obtained after the simulation at different concentration The results show that at concentrations of 0.025 mol/L and 0.05 mol/L, the atoms on t surface of the films are uniformly distributed, the number of vacancies and isolated lands is less, and the surface quality is good, as shown in Figure 10a,b. As the concentr tion increases to 0.1 mol/L, the bumps and pits on the surface of the plating are increas and the surface atomic distribution starts to become uneven, as shown in Figure 10c. Wh the concentration reaches 0.125 mol/L, the roughness of the plating surface increases si nificantly, producing more "gullies", and the number of vacant sites increases signi cantly, showing island-like pattern growth, as shown in Figure 10d. This is mainly becau the electrodeposition rate is influenced by the concentration factor, where an increase concentration increases the deposition rate of atoms, and atoms deposited onto the ele trode surface are easily buried by the newly deposited atoms and cannot migrate. It c be seen that the ion concentration does not affect the surface morphology to the sam extent as the deposition voltage and the temperature of the plating solution.

Effect of Ion Concentration on Surface Morphology
Based on the simulation model, the deposition voltage (V) is set as −0.8 V and the temperature of the plating solution (T) is set as 328 K. The Au + concentration in the plating solution is varied to study the effect of different ion concentrations on the electrodeposition process. Figure 10 shows the cross-sectional view of the coating structure and the image of the surface atom height obtained after the simulation at different concentrations. The results show that at concentrations of 0.025 mol/L and 0.05 mol/L, the atoms on the surface of the films are uniformly distributed, the number of vacancies and isolated islands is less, and the surface quality is good, as shown in Figure 10a,b. As the concentration increases to 0.1 mol/L, the bumps and pits on the surface of the plating are increased and the surface atomic distribution starts to become uneven, as shown in Figure 10c. When the concentration reaches 0.125 mol/L, the roughness of the plating surface increases significantly, producing more "gullies", and the number of vacant sites increases significantly, showing island-like pattern growth, as shown in Figure 10d. This is mainly because the electrodeposition rate is influenced by the concentration factor, where an increase in concentration increases the deposition rate of atoms, and atoms deposited onto the electrode surface are easily buried by the newly deposited atoms and cannot migrate. It can be seen that the ion concentration does not affect the surface morphology to the same extent as the deposition voltage and the temperature of the plating solution.

The Effect of Multiple Parameters on Surface Roughness
The root mean square (RMS) roughness Rq of the plated surface is calculated by equation after the simulation. In this paper, the effect of two-parameter coupling on surface roughness is analyzed. In the KMC simulation, the deposition voltage varied from −0.8 V to −1.4 V, the ion concentration varied from 0.025 mol/L to 0.125 mol/L, and the plating solution temperature varied from 298 K to 358 K.

Effect of Deposition Voltage and Ion Concentration on Roughness
The plating temperature is constant at 328 K while the values of the deposition voltage and ion concentration vary to calculate and analyze the RMS roughness of the coating surface. The data are shown in Table 3, and the variation of roughness with voltage versus concentration is plotted in Figure 11.

The Effect of Multiple Parameters on Surface Roughness
The root mean square (RMS) roughness R q of the plated surface is calculated by equation after the simulation. In this paper, the effect of two-parameter coupling on surface roughness is analyzed. In the KMC simulation, the deposition voltage varied from −0.8 V to −1.4 V, the ion concentration varied from 0.025 mol/L to 0.125 mol/L, and the plating solution temperature varied from 298 K to 358 K.

Effect of Deposition Voltage and Ion Concentration on Roughness
The plating temperature is constant at 328 K while the values of the deposition voltage and ion concentration vary to calculate and analyze the RMS roughness of the coating surface. The data are shown in Table 3, and the variation of roughness with voltage versus concentration is plotted in Figure 11. Overall, the coatings have better surface quality at lower ion concentrations and lower deposition voltages. The effect of changing deposition voltages on roughness is more pronounced at lower concentrations. Under the same ion concentration, as the deposition voltage increases from −0.8 V to −1.4 V, when the ion concentration is 0.025 mol/L, the surface roughness increases by 38.8%. As the deposition voltage increases from −0.8 V to −1.4 V, the surface roughness increases by 25.5%. Under the same deposition voltage, when the deposition voltage is −1.4 V, as the ion concentration decreases from 0.125 mol/L to 0.025 mol/L, the surface roughness decreases by 0.75%. When the deposition voltage is −0.8 V, the surface roughness decreases by 2.6%. In general, when the deposition voltage is −0.8 V and the ion concentration is 0.025 mol/L, the surface quality of the coating is the best, and the RMS roughness is the smallest. The minimum value is 2.3631 Å. Overall, the coatings have better surface quality at lower ion concentrations and lower deposition voltages. The effect of changing deposition voltages on roughness is more pronounced at lower concentrations. Under the same ion concentration, as the deposition voltage increases from −0.8 V to −1.4 V, when the ion concentration is 0.025 mol/L, the surface roughness increases by 38.8%. As the deposition voltage increases from −0.8 V to −1.4 V, the surface roughness increases by 25.5%. Under the same deposition voltage, when the deposition voltage is −1.4 V, as the ion concentration decreases from 0.125 mol/L to 0.025 mol/L, the surface roughness decreases by 0.75%. When the deposition voltage is −0.8 V, the surface roughness decreases by 2.6%. In general, when the deposition voltage is −0.8 V and the ion concentration is 0.025 mol/L, the surface quality of the coating is the best, and the RMS roughness is the smallest. The minimum value is 2.3631 Å.

Effect of Deposition Voltage and Plating Temperature on Roughness
The ion concentration constant at 0.05 mol/L in the model, and the values of plating solution temperature and deposition voltage are set to vary to calculate and analyze the RMS roughness of the coating surface. The data are shown in Table 4 and the variation of roughness with voltage and temperature is plotted in Figure 12.

Effect of Deposition Voltage and Plating Temperature on Roughness
The ion concentration constant at 0.05 mol/L in the model, and the values of plating solution temperature and deposition voltage are set to vary to calculate and analyze the RMS roughness of the coating surface. The data are shown in Table 4 and the variation of roughness with voltage and temperature is plotted in Figure 12. Overall, the coating has better surface quality at lower deposition voltage and higher temperature, and the effect of changing deposition voltage on surface roughness is more pronounced at higher temperatures. When the deposition voltage is the same, the surface roughness decreases with the increasing of temperature. When the deposition voltage is −0.8 V, the temperature increases from 298 K to 358 K, and the surface roughness decreases by 23.2%. When the deposition voltage is −1.4 V, the temperature increases from 298 K to 358 K, and the surface roughness decreases by 5.7%. When the temperature is the same, Overall, the coating has better surface quality at lower deposition voltage and higher temperature, and the effect of changing deposition voltage on surface roughness is more pronounced at higher temperatures. When the deposition voltage is the same, the surface roughness decreases with the increasing of temperature. When the deposition voltage is −0.8 V, the temperature increases from 298 K to 358 K, and the surface roughness decreases by 23.2%. When the deposition voltage is −1.4 V, the temperature increases from 298 K to 358 K, and the surface roughness decreases by 5.7%. When the temperature is the same, the surface roughness decreases with the increasing of deposition voltage. When the temperature is 298 K, the deposition voltage increases from −0.8 V to −1.4 V, and the surface roughness increases by 15.9%; when the temperature is 358 K, the deposition voltage increases from −0.8 V to −1.4 V, and the surface roughness increases by 42.4%. On the whole, when the deposition voltage is −0.8 V and the plating temperature is 358 K, the surface quality of the coating is the best, and the RMS roughness is the smallest. The minimum RMS roughness is 2.2179 Å.

Effect of Plating Solution Temperature and Ion Concentration on Roughness
In the model, the value of the deposition voltage (V) is kept unchanged at −1.0 V. The values of the plating temperature and ion concentration are set as variable to calculate and analyze the RMS roughness of the coating surface. The data are shown in Table 5. The variation of roughness with plating solution temperature and ion concentration is plotted in Figure 13.

Conclusions
In this paper, the process of preparing gold bumps by electrodeposition was simulated by the Kinetic Monte Carlo method. From the microscale perspective, the mechanism of the bump growth process was investigated, and the effects of different deposition parameters on the layer growth process were studied. Furthermore, the differences in the surface morphology and roughness of the layers under different deposition parameters

Conclusions
In this paper, the process of preparing gold bumps by electrodeposition was simulated by the Kinetic Monte Carlo method. From the microscale perspective, the mechanism of the bump growth process was investigated, and the effects of different deposition parameters on the layer growth process were studied. Furthermore, the differences in the surface morphology and roughness of the layers under different deposition parameters were compared and analyzed. The main conclusions are as follows: (1) From the perspective of the single-factor, lower deposition voltage, lower ion concentration and higher plating solution temperature can help reduce the number of empty spaces and isolated islands on the surface of the electrodeposited layer, resulting in a flat and smooth surface topography.