A Novel Non-Isolated High-Gain Non-Inverting Interleaved DC–DC Converter

High-gain DC–DC converters are being drastically utilized in renewable energy generation systems, such as photovoltaic (PV) and fuel cells (FC). Renewable energy sources (RES) persist with low-level output voltage; therefore, high-gain DC–DC converters are essentially integrated with RES for satisfactory performance. This paper proposes a non-isolated high-gain non-inverting interleaved DC–DC boost converter. The proposed DC–DC converter topology is comprised of two inductors and these are charging and discharging in series and parallel circuit configurations. The voltage multiplier technique is being utilized to produce high gain. The proposed topology is designed to operate in three modes of operation. Three switches are operated utilizing two distinct duty ratios to avoid the extreme duty ratio while having high voltage gain. Owing to its intelligent design, the voltage stress on the switches is also significantly reduced where the maximum stress is only 50% of the output voltage. The proposed converter’s steady-state analysis with two distinct duty ratios is thoroughly explored. Furthermore, a 160 W 20/400 V prototype is developed for performance analysis and validation. The converter topology can generate output voltage with a very high voltage gain of 20, which is verified by the prototype. Moreover, a high efficiency of 93.2% is attained by the proposed converter’s hardware prototype.


Introduction
In recent years, energy generation using renewable energy sources (RES) has significantly contributed to sustainable development globally [1,2]. Photovoltaic (PV) has gained remarkable popularity among other renewable energy sources. PV systems have already outperformed with both on-grid and off-grid-connected systems [3,4]. Power generation systems utilizing RES generates a low-level output voltage; therefore, requisite effective DC-DC converters having higher voltage gain capability [5]. Other than renewable power conversion, numerous other applications utilize DC-DC converters, such as electric vehicles, electric traction systems, power back-up systems, surgical equipment, and lighting applications [6,7]. In earlier times, conventional DC-DC converters were opted for voltage-boosting applications. However, conventional DC-DC boost converters persist with high switching stress that is equivalent to the output voltage [8]. Therefore, it requires switches with higher power ratings that ultimately increase the conduction losses to cater to the higher switching stress. Furthermore, choosing higher duty ratios to acquire high voltage gain induces high voltage spikes, conduction losses, and generates diode reverse recovery issues [9].
Nowadays, various DC-DC converter topologies with high-gain capabilities are available as per the application requirements [10]. High-gain DC-DC converters are further distributed within two clusters, named as isolated and non-isolated converter topologies [11].
Numerous isolated converter topologies to acquire high voltage gain are elaborated in the literature [12]. However, isolated converter topologies have substantial problems that include thermal impact, high voltage ripples on the power switches, leakage inductance, core saturation, and their large size makes them more expensive [11,13]. Thus, non-isolated converter topologies are opted for instead, for higher voltage gain; these are smaller in size and cost-effective, considering that no galvanic isolation is required [14,15].
Non-isolated converter topologies are also designed for specific applications, such as electric vehicles (EV). In ref. [16], three-phase interleaved parallel bi-directional converter topology is integrated with EV that offer multi-phase circuit topology, and the operation is based on multiple stages with different duty cycle ranges in order to fulfil the EV power requirements in a smooth manner. Another multi-phase interleaved boost converter topology using an auxiliary resonant circuit is presented in ref. [17]; it has the capability of soft switching and high voltage gain. For fuel cell integration non-isolated interleaved high-gain converter topologies are presented in ref. [18,19]; these interleaved topologies offer an improved DC bus regulation for the fuel cell irrespective of the intermittent source voltage. Furthermore, within the category of non-isolated high-gain converters most widely utilized, the topologies are quadratic boost [20], with a wide range of duty cycle ratios usually operated with a single switch; however, it has higher switching and diode stress in comparison to other non-isolated converter topologies. In ref. [21], a cascaded boost converter utilizes the initial stage for voltage boosting with a higher duty ratio, whereas the second stage operates with a nominal duty ratio with lower switching stress in comparison to the first stage of the converter topology. Besides high-gain capability, it persists with some severe issues that include higher component count that results in poor efficiency, and it also possesses a diode reverse-recovery issue. Coupled inductor cascaded boost is presented in ref. [22], and significantly high voltage gain could be attained by utilizing an extreme duty ratio for the operation of the converter or through increasing the coupled inductor's turns ratio; it is considered a design tradeoff. Due to excessive current stress across the switch, it is incompatible with the high-power applications. Another converter topology utilizing the voltage lifting approach is demonstrated in ref. [23]; it overcomes the effect of parasitic elements in DC-DC converters and has improved power transfer efficiency. However, it has high switching stress and high passive component count, and is, therefore, not suitable for high-power applications. In ref. [24], an active-passive inductor cell (APIC) converter topology is presented. Higher voltage gain along with optimal duty cycle are the highlighted merits for the proposed topology. In contrast, the high-power application requires higher active-passive inductor cells that will increase the complexity of the converter and will have high stress on the switches. However, with the addition of a switched-capacitor or switched-capacitor inductor, a power converter's complexity, along with the cost, increases significantly.
Various coupled inductor integrated DC-DC converter topologies are capable of generating higher gain factor along with less or optimum switching stress switches relying on the duty cycle ratio variation [25]. In certain cases, to attain the requisite voltage conversion set-point, the inductor turns ratio is increased; this results in an excessive input current ripple [26]. Therefore, the input current ripple requires optimization utilizing the filter at the input side, as depicted in ref. [27]. In ref. [28], a single-switch and singleinductor cascaded converter topology is presented, to acquire higher gain factor along with less input current ripple; however, it has quite a high component count and also possess harmonics due to capacitors; hence, it is not advisable for high-power loads. Furthermore, high-gain factor hybrid converter topologies are discussed in refs. [24,29,30].
This paper presents, a high-gain non-inverting interleaved boost converter topology to resolve the aforementioned issues. By using appropriate component values and suitable duty ratios, the proposed topology produces higher voltage gain. Furthermore, the proposed topology has these subsequent advantages: (1) The proposed converter topology is operated utilizing two distinct duty cycle ratios to achieve higher voltage gain. (2) The energy stored in the inductor is delivered to the voltage multiplier and supplied to the load. (3) The proposed converter topology achieves significantly higher voltage gain factor in comparison to the conventional boost and other high-gain converter topologies proposed in refs. [8,22,23,[30][31][32][33][34]. (4) Voltage stress is significantly lower across the diodes and the switches as compared to the voltage output percentage.
Section 2 discusses the circuit arrangement of the proposed boost converter topology in detail. Steady-state analysis for the proposed DC-DC boost converter topology is illustrated in Section 3. Section 4 elaborates on the efficiency evaluation of the proposed topology. A performance evaluation of the proposed topology with respect to the voltage stress across the diodes, switches, and voltage gain is discussed in Section 5. Hardware results of the proposed converter topology is described in Section 6. Furthermore, a conclusion of the results for the proposed topology is highlighted in Section 7.

Circuit Configuration
The circuit of the proposed converter topology is demonstrated in Figure 1, which is comprised of three power switches, S X , S Y , and S Z , two inductors, L X and L Y , four diodes, D 1 , D 2 , D 3 , and D 4 , and three capacitors, C 1 , C 2 , C o . The power switches, S X , S Y , and S Z , are operated with a switching frequency f sw . The switches, S X and S Y , are operated with a duty ratio denoted as D 1 , whereas S Z is operated with a duty ratio D 2 .
suitable duty ratios, the proposed topology produces higher voltage gain. Furthermore, the proposed topology has these subsequent advantages: (1) The proposed converter topology is operated utilizing two distinct duty cycle ratios to achieve higher voltage gain. (2) The energy stored in the inductor is delivered to the voltage multiplier and supplied to the load. (3) The proposed converter topology achieves significantly higher voltage gain factor in comparison to the conventional boost and other high-gain converter topologies proposed in refs. [8,22,23,[30][31][32][33][34]. (4) Voltage stress is significantly lower across the diodes and the switches as compared to the voltage output percentage.
Section 2 discusses the circuit arrangement of the proposed boost converter topology in detail. Steady-state analysis for the proposed DC-DC boost converter topology is illustrated in Section 3. Section 4 elaborates on the efficiency evaluation of the proposed topology. A performance evaluation of the proposed topology with respect to the voltage stress across the diodes, switches, and voltage gain is discussed in Section 5. Hardware results of the proposed converter topology is described in Section 6. Furthermore, a conclusion of the results for the proposed topology is highlighted in Section 7.

Circuit Configuration
The circuit of the proposed converter topology is demonstrated in Figure 1, which is comprised of three power switches, SX, SY, and SZ, two inductors, LX and LY, four diodes, D1, D2, D3, and D4, and three capacitors, C1, C2, Co. The power switches, SX, SY, and SZ, are operated with a switching frequency fsw. The switches, SX and SY, are operated with a duty ratio denoted as D1, whereas SZ is operated with a duty ratio D2.    Some suppositions are considered while explaining the proposed converter topology's steady-state operation, including: (1) All of the components in the circuit are ideal. The impact of forward voltage drop, switch ON state resistance, and equivalent series resistance (ESR) for the capacitors and the inductors are ignored; (2) To maintain the stable output voltage, the output capacitor C o is adequately large. Assume that the two inductors have an equivalent number of turn ratios.
Therefore, a similar voltage is across both the inductors, V LX and V LY , depicted in Equations (2) and (3).

Proposed Converter's Steady-State Analysis
This section elaborates on the operating modes in continuous conduction mode (CCM) of the proposed boost converter topology. There are three operational modes with two

Working in Continuous Conduction Mode
Mode I: The mode I time interval is [t o − t 1 ]; switches S X and S Y are turned ON, whereas the third switch S Z remains in the OFF state. Throughout this operation, the circuit's current direction is illustrated in Figure 3a. Here, the input energy will be supplied to the two inductors L X and L Y , and the capacitor C o will supply stored energy at the output. The diodes D 1 and D 4 remains in reversed bias, whereas the inner diode of the third switch S Z remains in the forward-biased state. Thus, even if the third switch S Z remains in an OFF state, the conduction voltage will be present across it. As the inductors and the source are parallel to each other in this mode, the inductor voltages are presented as follows: To obtain Equations (5), (2) and (3) are substituted into Equation (4) Mode II: The mode II time interval is [t 1 − t 2 ]; the third switch S Z is turned ON, whereas the two switches S X and S Y remains in the OFF state. Thus, the current direction of the circuit in mode II is demonstrated in Figure 3b. The two inductors L X , and L Y are fed by the input source, and the circuit current flows through L X , D 1 , D 4 , and L Y . The switching stress on S X and S Y in this mode is half of the supplied voltage. Furthermore, the output capacitor C o delivers the accumulated energy at the output load as D 4 is not in a forward-biased condition. The two inductors and the input source are connected in this mode. Expressions for calculating the inductor current and voltage are as follows: Since the two inductors L X and L Y are coupled in series to the source voltage V in , and i L current flowing through the inductors L X and L Y . By substitution of (2) and (3) into (8), the subsequent expression is attained: Mode III: The mode III time interval is [t 2 − t 3 ]; and all three switches S X , S Y , and S Z are in the OFF state. Figure 3c depicts the circuit's current path in mode III. Thus, in mode III, the input source together with the both inductors feed the output load. The diode D 1 is under the non-conduction state, being reverse-biased. Additionally, D 2 is in the forward-biased state that enables output capacitor C o to be charged in this mode. The switching stress across S X and S Y is half of the average of source voltage and the output voltage, while for the voltage stress, the third switch S Z is half related to the output voltage.
The two inductors L X and L Y are coupled in series to the input source in this mode. Expressions for calculating the inductor current and voltage are as follows: Micromachines 2023, 14, 585 where the converter's output voltage is V out . By substitution of Equations (2) and (3) into Equation (13) and simplifying Equation (14), the following expression (15) is attained: voltage. Both the inductors are coupled in a series connection to the input source in this mode. Expressions for calculating the inductor's current and voltage is attained as follows: (15) to the two inductors LX and LY, and the capacitor Co will supply stored energy at the output. The diodes D1 and D4 remains in reversed bias, whereas the inner diode of the third switch SZ remains in the forward-biased state. Thus, even if the third switch SZ remains in an OFF state, the conduction voltage will be present across it. As the inductors and the source are parallel to each other in this mode, the inductor voltages are presented as follows: To obtain Equations (5), (2) and (3) are substituted into Equation (4) Mode II: The mode II time interval is [t1 − t2]; the third switch SZ is turned ON, whereas the two switches SX and SY remains in the OFF state. Thus, the current direction of the circuit in mode II is demonstrated in Figure 3b. The two inductors LX, and LY are fed by the input source, and the circuit current flows through LX, D1, D4, and LY. The switching stress on SX and SY in this mode is half of the supplied voltage. Furthermore, the output capacitor Co delivers the accumulated energy at the output load as D4 is not in a forward- By implying the state-space averaging technique, the subsequent expressions are attained from Equations (7), (11) and (15): Simplifying Equation (16), the voltage gain expression is obtained:

Switching Stress
The switching stress on all three switches V DSX , V DSY , and V DSZ is depicted in Figure 2, correspondingly, and is expressed as follows:

Diode Voltage Stress
The diode voltage stress V D1 , V D2 , V D3 , and V D4 on the diodes D 1 , D 2 , D 3 , and D 4 is expressed as follows:

Component Selection
To obtain the appropriate performance of converter topology, adequate component selection is critical. The proposed converter topology's component selection comprises suitable inductor and capacitor calculations.

For Inductor
The appropriate inductor selection [35] relies on the input voltage V in , duty ratio D 1 , ripple current ∆i L , and the switching frequency f sw . For the optimum operation of proposed converter topology in CCM mode, an appropriate inductor value is determined by the following equation:

For Capacitor
Obtain optimum values for the selection of the output capacitor C o relies on the output voltage V out , ripple voltage ∆V c , switching frequency f sw , and the output power of the converter P out . These are attained by using the following expression: Respectively, the capacitance value for C 1 and C 2 are similar in order to avoid voltage distortions.

Efficiency Evaluation
The efficiency evaluation of the proposed converter topology is discussed with details for each of the operational modes. Figure 4. depicts the proposed converter's equivalent circuit. Thus, equivalent series resistance (ESR) for both of the inductors L X and L Y are denoted as r LX and r LY . Furthermore, ESR for the two capacitors C 1 and C 2 are denoted by r C1 , r C2 . Correspondingly, for the diodes D 1 , D 2 , D 3 , and D 4 , their internal resistances are represented by r D1 , r D2 , r D3 and, r D4 and the voltage drop on the diodes are denoted by V D1 , V D2 , V D3 and V D4 . Similarly, ON-state resistance for all the three switches S X , S Y and S Z are indicated by r SX , r SY , and, r SZ .
MODE II: The time interval for mode II is D2Ts; the two switches SX and SY are in an OFF state, whereas the third switch SZ is in an ON state; the average capacitor current Icout and the inductor voltage VLX are expressed as:  MODE I: The time interval for mode I is D 1 Ts; the two switches S X and S Y are in an ON state while the third switch S Z remains in an OFF state; the average capacitor current I cout and the inductor voltage V LX are expressed as: MODE II: The time interval for mode II is D 2 Ts; the two switches S X and S Y are in an OFF state, whereas the third switch S Z is in an ON state; the average capacitor current I cout and the inductor voltage V LX are expressed as: MODE III: The time interval for mode III is (1 − D 1 − D 2 ); all the switches S X , S Y , and S Z are in an OFF state, while the average capacitor current I cout and the inductor voltage V LX are expressed as: To obtain Equation (28), an ampere-second balance approach is implemented for the output capacitor C o .
Inductor current through I LX is obtained by simplifying Equation (28): By implementing a volt-second balance approach to the inductor L X , expression (30) is attained.
The output voltage obtained in (31) is achieved by simplifying (30). where, The expressions for the input and output powers are as follows: The input power is attained by substituting (29) into (33).
The efficiency evaluation of the proposed converter topology related to conduction losses is expressed in Equation (37), and calculated by using Equations (31), (34) and (35).
Considering the switching losses (P sw ), expression (38) is derived for the output power for the proposed converter topology.
Thus, V DS is the MOSFET's voltage from drain to source, I D represents the drain current of the MOSFET, f sw represents switching frequency, and t rise and t fall are the MOSFET's rise time and fall time. The proposed converter's efficiency is expressed in Equation (40), which is calculated by using Equations (31), (32), (34) and (39).
Considering the capacitor losses for the proposed converter, the output power is attained as: P rc = P rc1 + P rc2 + P rco (46) Power losses for all the three capacitors C 1 , C 2 , and C o are expressed in Equations (42), (43) and (44), respectively, whereas the total capacitor power losses P rc is expressed in Equation (48). The proposed converter's efficiency considering the capacitor losses is expressed in (47).

Comparative Performance Analysis
The proposed converter's characteristics comparison is determined in Table 1 with conventional and high-gain converter topologies. Comparative performance analysis of the proposed converter topology is mainly dependent on the fundamental parameters: voltage gain, switching stress, diode stress, and the quantity components. Table 1 includes converter topologies with one power switch and single duty ratio D presented in ref. [22] and [8] and two power switches and double duty ratios D 1 and D 2 [33], whereas [34] is based on two power switches and single duty ratio D, and three power switches and double duty ratio D 1 and D 2 are included in refs. [23,[30][31][32]. Table 1 depicts the voltage gain equation of the proposed converter topology. It is evident that converter topologies with double duty ratios have higher gain factor and satisfactory switching stress. Similarly, the proposed topology utilizes three power switches that are operated by two distinct duty ratios, and it has a higher voltage gain, as depicted in Table 1. The calculated value of duty ratios D new[p] is 85% where D 1 = 50% and D 2 = 35%. By splitting the duty ratio into two, it becomes convenient to operate the converter topology utilizing a higher duty cycle ratio within optimum operational limits; converter topologies with a single duty ratio cannot be operated by using extreme duty ratios. Moreover, the switching stress and diode stress for the proposed converter topology is less in contrast to converter topologies depicted in refs. [23,[30][31][32]. Furthermore, Figure 5 depicts the assessment of the proposed converter topology and the established converter topologies with respect to voltage gain versus duty ratio. The plot depicted in Figure 5 determines the output response of the proposed topology by iterating the duty ratio D 1 , whereas another duty ratio D 2 remains fixed at 0.35. The proposed converter has achieved a higher voltage gain factor of 50 with a duty ratio of D 1 0.6 and D 2 0.35. Whereas, converter topologies in refs. [8,22,30,34] have acquired a voltage gain of less than 15, and converter topologies in refs. [23,31,32] have obtained a voltage gain between 3 and 11. However, all the converter topologies were tested with a similar duty cycle ratio of 0.6. Moreover, Figure 6 illustrates the voltage gain response for the proposed converter topology under multiple variations in both duty ratios D 1 and D 2 . Thus, it is shown that by applying suitable duty ratios D 1 and D 2 , the proposed converter topology is competent for generating significant voltage gain.
Converter in ref. [23] ( Converter in ref. [31] (1+D 1 ) Converter in ref. [32] ( Converter in ref. [34] (1+D) Micromachines 2023, 14, x FOR PEER REVIEW 11 of 1 double duty ratio D1 and D2 are included in refs. [23,[30][31][32]. Table 1 depicts the voltag gain equation of the proposed converter topology. It is evident that converter topologie with double duty ratios have higher gain factor and satisfactory switching stress. Sim larly, the proposed topology utilizes three power switches that are operated by two dis tinct duty ratios, and it has a higher voltage gain, as depicted in Table 1. The calculate value of duty ratios Dnew[p] is 85% where D1 = 50% and D2 = 35%. By splitting the duty rati into two, it becomes convenient to operate the converter topology utilizing a higher dut cycle ratio within optimum operational limits; converter topologies with a single duty ra tio cannot be operated by using extreme duty ratios. Moreover, the switching stress an diode stress for the proposed converter topology is less in contrast to converter topologie depicted in refs. [23,[30][31][32]. Furthermore, Figure 5 depicts the assessment of the propose converter topology and the established converter topologies with respect to voltage gai versus duty ratio. The plot depicted in Figure 5 determines the output response of th proposed topology by iterating the duty ratio D1, whereas another duty ratio D2 remain fixed at 0.35. The proposed converter has achieved a higher voltage gain factor of 50 wit a duty ratio of D1 0.6 and D2 0.35. Whereas, converter topologies in refs. [8,22,30,34] hav acquired a voltage gain of less than 15, and converter topologies in refs. [23,31,32] hav obtained a voltage gain between 3 and 11. However, all the converter topologies wer tested with a similar duty cycle ratio of 0.6. Moreover, Figure 6 illustrates the voltage gai response for the proposed converter topology under multiple variations in both duty ra tios D1 and D2. Thus, it is shown that by applying suitable duty ratios D1 and D2, the pro posed converter topology is competent for generating significant voltage gain.  Hence, the overall voltage stress for the proposed converter topology remains relatively low; for the power switches S X and S Y , the voltage stress is 25% with respect to the output voltage, whereas the power switch S Z has 50% voltage stress with respect to the output voltage. Moreover, the switching stress for the converters presented in ref. [8,22] is 100% of the output voltage. For converters presented in ref. [33,34], the voltage stress for switches S X and S Y is 50% of the output voltage. Whereas, the converter topologies presented in refs. [23,[30][31][32] persist with a different switching voltage stress pattern; two of the switches S X and S Y have 50% voltage stress of the output voltage, and the switch S Z has 100% voltage stress of the output voltage. However, it is evident for the proposed converter topology that it has significantly low switching voltage stress related to the converter topologies discussed in Table 1. Similarly, the voltage stress on the diodes is also low related to the converter topologies discussed in Table 1. Furthermore, the number of component counts for the converter topologies includes the quantity of switches, inductors, diodes, and capacitors. The measure of component counts for the converter topologies is between 4 and 15, since conventional and high-gain converter topologies are considered to persist with a slightly higher number of component counts. However, the component count for the proposed topology is 12, which includes three switches, three inductors, four diodes, and three capacitors. Whereas in ref. [22], the component count is 15, and the similar high-gain converter topology presented in ref. [33] has a component count of 12, equivalent to the proposed converter topology. Theoretical efficiency under varying duty ratios D 1 and D 2 is demonstrated in Figure 7. Thus, the efficacy of the proposed converter topology is evaluated, and remained higher than 90%. Additionally, the voltage gain for the proposed converter topology is higher than the converter topologies discussed in Table 1. Moreover, to acquire high voltage gain with optimum efficiency, the duty cycle ratio must be adequately selected considering the following limitations: (1) both the duty ratios D 1 and D 2 must not be equivalent to 0.5, and (2) the total duty ratios D 1 and D 2 must be less than 1.
proposed topology by iterating the duty ratio D1, whereas another duty ratio D2 remai fixed at 0.35. The proposed converter has achieved a higher voltage gain factor of 50 wi a duty ratio of D1 0.6 and D2 0.35. Whereas, converter topologies in refs. [8,22,30,34] ha acquired a voltage gain of less than 15, and converter topologies in refs. [23,31,32] ha obtained a voltage gain between 3 and 11. However, all the converter topologies we tested with a similar duty cycle ratio of 0.6. Moreover, Figure 6 illustrates the voltage ga response for the proposed converter topology under multiple variations in both duty r tios D1 and D2. Thus, it is shown that by applying suitable duty ratios D1 and D2, the pr posed converter topology is competent for generating significant voltage gain.   considered to persist with a slightly higher number of component counts. However, th component count for the proposed topology is 12, which includes three switches, thre inductors, four diodes, and three capacitors. Whereas in ref. [22], the component count i 15, and the similar high-gain converter topology presented in ref. [33] has a componen count of 12, equivalent to the proposed converter topology. Theoretical efficiency unde varying duty ratios D1 and D2 is demonstrated in Figure 7. Thus, the efficacy of the pro posed converter topology is evaluated, and remained higher than 90%. Additionally, th voltage gain for the proposed converter topology is higher than the converter topologie discussed in Table 1. Moreover, to acquire high voltage gain with optimum efficiency, th duty cycle ratio must be adequately selected considering the following limitations: (1 both the duty ratios D1 and D2 must not be equivalent to 0.5, and (2) the total duty ratio D1 and D2 must be less than 1.

Experimental Results
To verify and evaluate the theoretical results of the proposed converter topology, 160 W prototype has been developed, as depicted in Figure 8. The design parameters and

Experimental Results
To verify and evaluate the theoretical results of the proposed converter topology, a 160 W prototype has been developed, as depicted in Figure 8. The design parameters and component specifications are illustrated in Table 2. To operate the proposed converter topology with appropriate switching gate pulses, phase delay, and duty ratio, an Arduino UNO is integrated in the hardware setup. The gate pulses V GSX , V GSY , and V GSZ to regulate the switches S X , S Y , and S Z are depicted in Figure 9a. The two switches S X and S Y are operated by gate pulses V GSX and V GSY using a switching frequency of 50 kHz with a duty ratio D 1 of 0.5. The switch S Z is operated by gate pulse V GSZ with a 180 • phase shift, a similar switching frequency of 50 kHz, and a duty ratio D 2 of 0.35. The input voltage and input current results V in and I in, along with the gate pulses are shown in Figure 9b. The proposed converter topology achieved a voltage gain of 19.7 and a voltage ripple of 2.2% while the input voltage is 20 V. During the converter operation, the average input is observed to be 10 A. Furthermore, the theoretical calculation of voltage gain is substantiated by the experimental setup. Figure 9c depicts the output response of the voltage and output current V o and i o , along with the gate pulses. The observed average output current is 400 mA. Additionally, the current ripple for both the inductors L X and L Y is observed to be 8%. Figure 9d illustrates the voltage stress across the S X and S Y along with the gate pulse; it is evident that the switching stress is 25% related the output voltage. Whereas, for the switch S Z , switching stress is half or 50% related the output voltage. Figure 9e depicts the response of inductor currents I LX and I LY along with the gate pulses; the inductor currents are observed to be continuous. For the ON-state duration of the two switches S X and S Y , the source current is almost double the inductor current I LX or I LY , and for the OFF-state duration of the two switches S X and S Y , the inductor current I LX or I LY is similar to the input current. Considering the topologies presented in Table 1, the proposed converter topology persists with a significantly low switching stress percentage in comparison to the output voltage. Diode stress V D1 and V D2 are shown in Figure 9f. For the diode D 1 , the maximum voltage stress is similar to the input voltage; for diode D 2 the maximum voltage stress is equivalent to the average source voltage and the output voltage. Figure 10 depicts the output power and efficiency comparison. The analysis is based on the theoretical and experimental setup; the observed deviation is about 1.08%, between the theoretical and experimental investigation. The hardware prototype results validate the efficacy of the proposed converter; it is capable of generating high voltage gain with minimum voltage stress on the diodes and the switches.

Conclusions
A novel non-isolated high-gain non-inverting interleaved converter topology is proposed in this paper. DC-DC converters utilizing a single duty ratio D persist with implications while operating at excessive duty cycle ratios. Considering this issue, the proposed

Conclusions
A novel non-isolated high-gain non-inverting interleaved converter topology is proposed in this paper. DC-DC converters utilizing a single duty ratio D persist with implications while operating at excessive duty cycle ratios. Considering this issue, the proposed

Conclusions
A novel non-isolated high-gain non-inverting interleaved converter topology is proposed in this paper. DC-DC converters utilizing a single duty ratio D persist with implications while operating at excessive duty cycle ratios. Considering this issue, the proposed converter includes three switches and these switches are operated with two distinct duty ratios, avoiding excessive duty cycle ratios. The proposed converter topology also has some limitations that include: a slightly higher component count, and it is not recommended for applications that require lower voltage gain or lower loads that operate the converter in discontinuous conduction mode (DCM). However, in contrast, the proposed converter topology is designed to generate a higher voltage gain with a nominal voltage stress, and it is suitable for high power applications and to operate in continuous conduction mode (CCM). Theoretical and practical analyses for the proposed converter topology were carried out considering the crucial parameters, such as voltage stress, on the diodes and switches, voltage gain, and efficiency. Thus, to validate the performance analysis practically, a prototype model 160 W 20/400 V of the proposed converter was built for experimental setup. The voltage gain percentage for the proposed converter is significantly higher with lower voltage stress on the switches and diodes with respect to the recently developed DC-DC converter topologies. The maximum efficiency of the proposed converter is well above 90%. Therefore, the pivotal features of the proposed converter determine it to be an appropriate choice for voltage boosting applications, such as renewable energy applications, energy management of the microgrid, fuel cell-based energy generation, and electric automobiles. Further improvements can be made in the proposed converter topology by designing it for low power applications by changing the positions of the switches and their operation, provided that if offers low voltage stress on the components, as compared to established converter topologies. Acknowledgments: The authors would like to acknowledge their kind appreciation to the Department of Electrical and Electronics Engineering, Universiti Teknologi PETRONAS, Malaysia for conducting this research work. The authors also wish to extend their sincere thanks to the support of the Faculty of Data Science and Information Technology, INTI International University, Malaysia for providing the state-of-the-art research support to carry on this work. Parasitic resistance of inductor L X I C2 Capacitor current C 2 r LY Parasitic resistance of inductor L Y P in Input power r SX Parasitic resistance of switch S X P out Output power r SY Parasitic resistance of switch S Y P sw Switching power losses r SZ Parasitic resistance of switch S Z P rc Capacitor power losses r D1

Conflicts of
Parasitic resistance of diode D 1 η Efficiency