A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design’s robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network.


Introduction
A number of efforts have been made to explore RF integrated circuits (RFICs) for wireless communication applications since global demand is rising rapidly. CMOS technology has been has attracted significant attention in integrated circuit design due to its low cost of implementation and to achieve the goal of realizing complete system-on-chip (SoC) implementation. CMOS-based PAs have numerous limitations because of their low breakdown voltage, the low-quality factor of passive components, high silicon-substrate loss, and the inaccessibility of back via holes for the ground, in which they restrict the attainable linear In addition, to provide an optimum impedance transformation at the output of the main PA, a π-structured matching network consisting of C15, L7, C16, and C17 was implemented prior to the tunable-output impedance matching. The π-network matching stage converts the low output impedance of the main PA into a higher impedance value. The employed tunable-output impedance matching with the transformer eliminates the requirement of an additional multistage matching network for wideband operation and PVT reconfiguration. The tunable-output impedance matching offers an impedance tuning characteristic which produces an optimum impedance for a wide frequency bandwidth and PVT variations. Referring to Figure 1, the designed tunable-output impedance matching consists of T1, C18, C19, Q10, Q11, R13, and R14. T1 is realized with a patterned ground shield (PGS) for the enhancement of the transformer's Q factor. The impedance at the primary winding side of T1 is varied by controlling VTUNE1, while the impedance of the secondary winding side of T1 is controlled via VTUNE2. In addition, to provide an optimum impedance transformation at the output of the main PA, a π-structured matching network consisting of C 15 , L 7 , C 16 , and C 17 was implemented prior to the tunable-output impedance matching. The π-network matching stage converts the low output impedance of the main PA into a higher impedance value. The employed tunable-output impedance matching with the transformer eliminates the requirement of an additional multistage matching network for wideband operation and PVT reconfiguration. The tunable-output impedance matching offers an impedance tuning characteristic which produces an optimum impedance for a wide frequency bandwidth and PVT variations. Referring to Figure 1, the designed tunable-output impedance matching consists of T 1 , C 18 , C 19 , Q 10 , Q 11 , R 13 , and R 14 . T 1 is realized with a patterned ground shield (PGS) for the enhancement of the transformer's Q factor. The impedance at the primary winding side of T 1 is varied by controlling V TUNE1 , while the impedance of the secondary winding side of T 1 is controlled via V TUNE2 .

Digital Linearizer
As illustrated in Figure 2, the digital linearizer (DL) comprises a seven-stage voltage generator which produces digitally varied coarse and fine voltage tuning. The DL is constructed via the binary-weighted current sources (Y 2 :Y 5 and Y 20 :Y 22 ). Utilizing the current sources, a stable current is supplied to the load resistor (R O ). The PMOS current sources (Y 2 :Y 5 ) are employed to supply a stable current to the resistor (R O ) which performs coarse voltage tuning using bits A 0 to A 3 . Meanwhile, the NMOS (Y 20 :Y 22 ) is employed to divert the current away from the output node and it performs fine voltage tuning using bits represented by S 0 to S 2 . The total current going through R o is adjusted by the digital bits [A0:A3] and [S0:S2]. [A0:A3] bits conduct coarse voltage tuning with larger voltage changes for each bit. Bit A3 is the most significant bit (MSB), while bit A0 is the least-significant-bit (LSB).

Digital Linearizer
As illustrated in Figure 2, the digital linearizer (DL) comprises a seven-stage voltage generator which produces digitally varied coarse and fine voltage tuning. The DL is constructed via the binary-weighted current sources (Y2:Y5 and Y20:Y22). Utilizing the current sources, a stable current is supplied to the load resistor (RO). The PMOS current sources (Y2:Y5) are employed to supply a stable current to the resistor (RO) which performs coarse voltage tuning using bits A0 to A3. Meanwhile, the NMOS (Y20:Y22) is employed to divert the current away from the output node and it performs fine voltage tuning using bits represented by S0 to S2. The total current going through Ro is adjusted by the digital bits [A0:A3] and [S0:S2]. [A0:A3] bits conduct coarse voltage tuning with larger voltage changes for each bit. Bit A3 is the most significant bit (MSB), while bit A0 is the leastsignificant-bit (LSB). In addition, [S0:S2] bits conduct fine voltage tuning with small voltage variations between each bit. Bit S2 is the MSB while bit S0 is the LSB. In general, the DL has 128 states of different voltage levels, of which 120 generate usable output voltages which can vary the operating region of the transistors. Moreover, the bandgap reference employed in the digital linearizer offers a stable voltage reference across PVT variations. Referring to Figure 2, by utilizing the bandgap reference voltage, a constant current reference is produced for the seven-stage voltage generator through the op-amp (OA2), Y7 and R7. OA2 is employed in a closed-loop system in order to achieve a constant current reference (IREF) for the current mirrors in the seven-stage voltage generator. In addition, unity gain buffers (UGB1 and UGB2) are employed to provide a high impedance path so that a very small current will be drawn from the nodes. UGB2 also provides an isolation from the RF signal in the PA when it is integrated to it. By applying KCL at node X in Figure 2 and taking RO generates voltage: where Figure 2. The complete schematic of the integrated digital linearizer.
In addition, [S0:S2] bits conduct fine voltage tuning with small voltage variations between each bit. Bit S2 is the MSB while bit S0 is the LSB. In general, the DL has 128 states of different voltage levels, of which 120 generate usable output voltages which can vary the operating region of the transistors. Moreover, the bandgap reference employed in the digital linearizer offers a stable voltage reference across PVT variations. Referring to Figure 2, by utilizing the bandgap reference voltage, a constant current reference is produced for the seven-stage voltage generator through the op-amp (OA2), Y 7 and R 7 . OA 2 is employed in a closed-loop system in order to achieve a constant current reference (I REF ) for the current mirrors in the seven-stage voltage generator. In addition, unity gain buffers (UGB1 and UGB2) are employed to provide a high impedance path so that a very small current will be drawn from the nodes. UGB2 also provides an isolation from the RF signal in the PA when it is integrated to it. By applying KCL at node X in Figure 2 and taking R O generates voltage: where Figure 3 shows the plot of the simulated output voltage levels across the digital bits.  Figure 3 shows the plot of the simulated output voltage levels across the digital bits.

Tunable-Output Impedance Matching Network Design
The tunability of the output impedance matching network is realized via a tuner circuit consisting of a deep triode common-source transistor, a stabilizer resistor, and a capacitor. The current source tuner (CST) is applied at the transformer in both primary and secondary windings, as depicted in Figure 4. As shown in Figure 4, the primary side of the transformer, Lp, has a deep triode common source transistor, Q1, which controls its impedance via the tuning voltage (VTUNE1). The resistor (R1) functions as a stabilizer which prevents Q1 from oscillating because of the escalating input RF signal through the transformer. The capacitor, C1, acts as the reactance tuner of the transformer. The tuner circuit consists of Q2, R2, and C2 at the secondary winding; Ls has the same purpose as previously mentioned. As illustrated in Figure 5a, it can be observed that when VTUNE1 is varied, the current that flows into node X is controlled, i1 flows into the primary winding of the transformer (Lp) while i2 flows into the tuner. The same event occurs following the secondary winding of the transformer (Ls), when VTUNE2 is varied. The current flow is represented by i3 and i4 at node Y in the secondary winding. Figure 5a,b depicts the simulated current flow at node X and Y, respectively. Figure 6 shows the equivalent circuit of the tunable-output

Tunable-Output Impedance Matching Network Design
The tunability of the output impedance matching network is realized via a tuner circuit consisting of a deep triode common-source transistor, a stabilizer resistor, and a capacitor. The current source tuner (CST) is applied at the transformer in both primary and secondary windings, as depicted in Figure 4. As shown in Figure 4, the primary side of the transformer, L p , has a deep triode common source transistor, Q 1, which controls its impedance via the tuning voltage (V TUNE1 ). The resistor (R 1 ) functions as a stabilizer which prevents Q 1 from oscillating because of the escalating input RF signal through the transformer. The capacitor, C 1 , acts as the reactance tuner of the transformer. The tuner circuit consists of Q 2 , R 2 , and C 2 at the secondary winding; L s has the same purpose as previously mentioned. Figure 3 shows the plot of the simulated output voltage levels across the digital bits.

Tunable-Output Impedance Matching Network Design
The tunability of the output impedance matching network is realized via a tuner circuit consisting of a deep triode common-source transistor, a stabilizer resistor, and a capacitor. The current source tuner (CST) is applied at the transformer in both primary and secondary windings, as depicted in Figure 4. As shown in Figure 4, the primary side of the transformer, Lp, has a deep triode common source transistor, Q1, which controls its impedance via the tuning voltage (VTUNE1). The resistor (R1) functions as a stabilizer which prevents Q1 from oscillating because of the escalating input RF signal through the transformer. The capacitor, C1, acts as the reactance tuner of the transformer. The tuner circuit consists of Q2, R2, and C2 at the secondary winding; Ls has the same purpose as previously mentioned. As illustrated in Figure 5a, it can be observed that when VTUNE1 is varied, the current that flows into node X is controlled, i1 flows into the primary winding of the transformer (Lp) while i2 flows into the tuner. The same event occurs following the secondary winding of the transformer (Ls), when VTUNE2 is varied. The current flow is represented by i3 and i4 at node Y in the secondary winding. Figure 5a,b depicts the simulated current flow at node X and Y, respectively. Figure 6 shows the equivalent circuit of the tunable-output As illustrated in Figure 5a, it can be observed that when V TUNE1 is varied, the current that flows into node X is controlled, i 1 flows into the primary winding of the transformer (L p ) while i 2 flows into the tuner. The same event occurs following the secondary winding of the transformer (L s ), when V TUNE2 is varied. The current flow is represented by i 3 and i 4 at node Y in the secondary winding. Figure 5a,b depicts the simulated current flow at node X and Y, respectively. Figure 6 shows the equivalent circuit of the tunable-output impedance matching network. The impedances of both the primary and secondary sides of the transformer are tuned using the CST.  It can be deduced that the rate of change in current (i1 in primary and i3 in secondary) into Lp and Ls are reduced. Therefore, this accords with the increment in inductance values of the transformer windings, as defined by: where VX and VY are the voltages at nodes X and Y, respectively. Furthermore, based on Figure 6, the parameters from the transformer are Lsn, Rsn, Csn, Coxn, Csin, and Rsin. The external parameters introduced into the transformer are the capacitors (C1 and C2) and resistors (RO1 and RO2) from the CST at the primary and secondary windings. The RO1 and RO2 are the output resistances of Q1 and Q2, respectively.   It can be deduced that the rate of change in current (i1 in primary and i3 in secondary) into Lp and Ls are reduced. Therefore, this accords with the increment in inductance values of the transformer windings, as defined by: where VX and VY are the voltages at nodes X and Y, respectively. Furthermore, based on Figure 6, the parameters from the transformer are Lsn, Rsn, Csn, Coxn, Csin, and Rsin. The external parameters introduced into the transformer are the capacitors (C1 and C2) and resistors (RO1 and RO2) from the CST at the primary and secondary windings. The RO1 and RO2 are the output resistances of Q1 and Q2, respectively. It can be deduced that the rate of change in current (i 1 in primary and i 3 in secondary) into L p and L s are reduced. Therefore, this accords with the increment in inductance values of the transformer windings, as defined by: where V X and V Y are the voltages at nodes X and Y, respectively. Furthermore, based on Figure 6, the parameters from the transformer are Lsn, Rsn, Csn, Coxn, Csin, and Rsin. The external parameters introduced into the transformer are the capacitors (C 1 and C 2 ) and resistors (R O1 and R O2 ) from the CST at the primary and secondary windings. The R O1 and R O2 are the output resistances of Q 1 and Q 2 , respectively. The admittance following the primary and secondary windings of the transformer are expressed in terms of Y 11 and Y 33 , respectively [17][18][19]. When simulating or measuring the impedance of the transformer, the parameters of the primary winding are obtained by keeping the secondary winding open [20]. The inverse is performed when obtaining the parameters of the secondary winding. From Figure 6, Y 11 and Y 33 are derived and expressed as follows: where R O1 and R O2 are expressed as: where µ nn is the electron mobility, C oxn is the oxide capacitance, W n is the width of the transistor, L n is the length of the transistors, V TUNEn is the gate voltage, V THn is the threshold voltage, and λ n is the channel length modulation of the transistors. The subscripted n represents the transistors (Q 1 and Q 2 ) from the CST. It can be deduced from (8) and (9) that V TUNEn is inversely proportional to R On , where it contributes to the impedance tunability. The simulated impedance values of the tunableoutput impedance matching network are depicted in Figure 7. It can be observed that the impedance locations on the Smith chart vary when the CST is tuned for different frequencies.
The variation in the impedance value is helpful in realizing a tunable impedance matching network for the PA.
The admittance following the primary and secondary windings of the transformer are ex-pressed in terms of Y11 and Y33, respectively [17][18][19]. When simulating or measuring the impedance of the transformer, the parameters of the primary winding are obtained by keeping the secondary winding open [20]. The inverse is performed when obtaining the parameters of the secondary winding. From Figure 6, Y11 and Y33 are derived and expressed as follows: where RO1 and RO2 are expressed as: where μnn is the electron mobility, Coxn is the oxide capacitance, Wn is the width of the transistor, Ln is the length of the transistors, VTUNEn is the gate voltage, VTHn is the threshold voltage, and λn is the channel length modulation of the transistors. The subscripted n represents the transistors (Q1 and Q2) from the CST. It can be deduced from (8) and (9) that VTUNEn is inversely proportional to ROn, where it contributes to the impedance tunability. The simulated impedance values of the tunable-output impedance matching network are depicted in Figure 7. It can be observed that the impedance locations on the Smith chart vary when the CST is tuned for different frequencies. The variation in the impedance value is helpful in realizing a tunable impedance matching network for the PA.

DAWPD Mechanism
In a PA, the transconductance (g m ) of the transistor, especially the third-order transconductance (g m3 ) is one of the primary contributors to distortions. The third-order distortions occurring at the frequencies of 2ω 1 -ω 2 and 2ω 2 -ω 1 are highly focused because they appear in-band and are extremely difficult to filter out. The transfer function of a PA can be derived using the Taylor series expansion, which is given by [21]: where v in (t) is the input voltage, g mn is the n th -order coefficient of the transconductance and i out is the output current. As seen in (10), the g m3 is the third-order transconductance coefficient contributing to IMD3 generation.
To delineate the cancellation operation of the IMD3 products in the spectrum domain, a two-tone test can be utilized in which the input signal is represented by: By assuming the upper and lower IMD signals are equal and considering only the upper IMD3 components of the DAWPD and main PA at 2ω 2 -ω 1 , the I out (v in ) is given as [22]: where θ main and θ dawpd are the phases of the IMD3 product, while g m3,main and g m3,dawpd are the third-order transconductance of the main and DAWPD. Referring to (12) and (13), it can be concluded that to minimize the IMD3 distortions, the g m3 and θ of both the DAWPD and main PA stages should be in contrast to each other, as in (14): Based on (14), it is deduced that to attain the ideal IMD3 cancellation, the third-order components produced at the DAWPD's output need to have a 180 • out-of-phase response compared to the third-order components produced at the main PA's output [23]. The opposite characteristic between the stages can be perceived in terms of opposite AM-AM and AM-PM behavior based on the fundamental components. Referring to Figure 8, the g m3 of the DAWPD is varied utilizing the DL employed at the gate of the Q 6 . The transconductances of the DAWPD and main PA are determined, and optimum operating conditions are selected. From (14), it can be seen that to conduct the IMD3 cancellation, the g m6,3 should be in contrast to g m9, 3 . Thus, the selected operating region for the DAWPD and main PA is shown in Figure 8. Herein, it can be seen that the g m3 of both DAWPD and main PA contrast with each other. The main PA's g m3 is −7.3 A/V 3 at V GS = 0.8 V. On the other hand, the DAWPD's g m3 was selected to be +7.3 A/V 3 at V GS = 0.42 V or V GS = 0.58 V, since both of these V GS values can be utilized to provide the cancellation. However, since the higher V GS provides a higher gain, the V GS = 0.58 V was selected here.
The V GS of the DAWPD was selected via the digital bits combination from the digital linearizer. Here, the A-bits are represented by the first four bits, while the S-bits are represented by the last three bits. For example, the V GS = 0.58 V was selected by tuning the A-bits to 0100 and S-bits to 010, which gives a full combination of 0100010. It can be observed that the DAWPD can be operated at two different regions which generate equal opposite g m3 to that of the main PA. The operating region of the DAWPD can be varied via the digital linearizer to achieve optimum performance across the wideband operation and PVT variations. Furthermore, the small-signal equivalent circuit of the DAWPD and main PA is depicted in Figure 9a,b, respectively. The output impedances of DAWPD and the main PA stages are derived based on the equivalent circuit. The output impedances of the DAWPD (Z dawpd ) and main PA (Z main ) stages are shown in (15) and (16), respectively. The output impedance of the DAWPD is inclusive of C gs9 from the main stage as its load, since it is in a cascade with the main stage. The C gs9 is also a part of the fully capacitive response in the DAWPD. The VGS of the DAWPD was selected via the digital bits combination from the digital linearizer. Here, the A-bits are represented by the first four bits, while the S-bits are represented by the last three bits. For example, the VGS = 0.58 V was selected by tuning the Abits to 0100 and S-bits to 010, which gives a full combination of 0100010. It can be observed that the DAWPD can be operated at two different regions which generate equal opposite gm3 to that of the main PA. The operating region of the DAWPD can be varied via the digital linearizer to achieve optimum performance across the wideband operation and PVT variations. Furthermore, the small-signal equivalent circuit of the DAWPD and main PA is depicted in Figure 9a,b, respectively. The output impedances of DAWPD and the main PA stages are derived based on the equivalent circuit. The output impedances of the DAWPD (Zdawpd) and main PA (Zmain) stages are shown in (15) and (16), respectively. The output impedance of the DAWPD is inclusive of Cgs9 from the main stage as its load, since it is in a cascade with the main stage. The Cgs9 is also a part of the fully capacitive response in the DAWPD.

( )
(a)  The VGS of the DAWPD was selected via the digital bits combination from the digital linearizer. Here, the A-bits are represented by the first four bits, while the S-bits are represented by the last three bits. For example, the VGS = 0.58 V was selected by tuning the Abits to 0100 and S-bits to 010, which gives a full combination of 0100010. It can be observed that the DAWPD can be operated at two different regions which generate equal opposite gm3 to that of the main PA. The operating region of the DAWPD can be varied via the digital linearizer to achieve optimum performance across the wideband operation and PVT variations. Furthermore, the small-signal equivalent circuit of the DAWPD and main PA is depicted in Figure 9a,b, respectively. The output impedances of DAWPD and the main PA stages are derived based on the equivalent circuit. The output impedances of the DAWPD (Zdawpd) and main PA (Zmain) stages are shown in (15) and (16), respectively. The output impedance of the DAWPD is inclusive of Cgs9 from the main stage as its load, since it is in a cascade with the main stage. The Cgs9 is also a part of the fully capacitive response in the DAWPD. As observed in (15), a capacitive response influences DAWPD' Meanwhile, the main PA's output impedance is dominated by an which is contributed by the large L5 and L6 values from the design Both stages' exhibited capacitive and inductive responses provide th phase characteristics. The interstage impedance between the DAWPD tal since it reflects the characteristic of the pre-distorted signal, which PA's input in which it impacts the linearity of the PA across the wide o [24,25]. Hence, the interstage impedance is beneficial in attaining a tion. Since the operating region of Q4 in the active load is tuned, it impedance at the DAWPD's output (Zdawpd). The tuning of Q4 varies which Ro4 represents, as in (15). Based on (15), Ro4 and Ro6, which a tuning of the digital linearizer, appear as part of the DAWPD's out tributing to the configurability of the impedance which is beneficial fo tuning.

( )
The opposite response of the PA is simulated across the operat 1.7 to 2.7 GHz. The results are at 1.7, 2.45, and 2.7 GHz, where the optimum. The opposite AM-AM response is depicted in Figure 10a. AM-AM profiles expand across output power at different operat DAWPD is tuned to exhibit a contrary compressed AM-AM profile. A As observed in (15), a capacitive response influences DAWPD's output impedance. Meanwhile, the main PA's output impedance is dominated by an inductive response which is contributed by the large L 5 and L 6 values from the designed parallel LC stack. Both stages' exhibited capacitive and inductive responses provide the required opposite-phase characteristics. The interstage impedance between the DAWPD and main PA is vital since it reflects the characteristic of the pre-distorted signal, which is fed into the main PA's input in which it impacts the linearity of the PA across the wide operating bandwidth [24,25]. Hence, the interstage impedance is beneficial in attaining a wideband linearization. Since the operating region of Q 4 in the active load is tuned, it provides a variable impedance at the DAWPD's output (Z dawpd ). The tuning of Q 4 varies the output resistance which R o4 represents, as in (15). Based on (15), R o4 and R o6, which are dependent on the tuning of the digital linearizer, appear as part of the DAWPD's output impedance, contributing to the configurability of the impedance which is beneficial for wideband linearity tuning.
The opposite response of the PA is simulated across the operating bandwidth from 1.7 to 2.7 GHz. The results are at 1.7, 2.45, and 2.7 GHz, where the PA's performance is optimum. The opposite AM-AM response is depicted in Figure 10a. Since the main PA's AM-AM profiles expand across output power at different operating frequencies, the DAWPD is tuned to exhibit a contrary compressed AM-AM profile. As seen in Figure 10a, the digital bits variations in the DAWPD generate the optimum compressing responses needed to cancel out the expanding gain of the main PA.
impedance at the DAWPD's output (Zdawpd). The tuning of Q4 varies the output resistance which Ro4 represents, as in (15). Based on (15), Ro4 and Ro6, which are dependent on the tuning of the digital linearizer, appear as part of the DAWPD's output impedance, contributing to the configurability of the impedance which is beneficial for wideband linearity tuning.
The opposite response of the PA is simulated across the operating bandwidth from 1.7 to 2.7 GHz. The results are at 1.7, 2.45, and 2.7 GHz, where the PA's performance is optimum. The opposite AM-AM response is depicted in Figure 10a. Since the main PA's AM-AM profiles expand across output power at different operating frequencies, the DAWPD is tuned to exhibit a contrary compressed AM-AM profile. As seen in Figure 10a, the digital bits variations in the DAWPD generate the optimum compressing responses needed to cancel out the expanding gain of the main PA.  Moreover, the AM-PM responses are also analyzed across the frequencies mentioned above. The DAWPD can produce a phase response opposite to the phase response of the main PA. The opposite-phase responses between the stages are compensated by each other, through which a flat phase response across output power is achieved. The opposite phase responses and their resultant AM-PM are illustrated in Figure 11a,b, respectively. Figure 11b shows that the resultant AM-PM deviation is about 4 • up to the output power of 26 dBm at 1.7 GHz. Deviations by 4 • in AM-PM are achieved up to 27.6 and 27.3 dBm at 2.45 and 2.7 GHz, respectively. An AM-PM deviation by 5 • or more is approximately equivalent to a gain compression of 1 dB or more [26]. The AM-PM flatness achieved indicates the linearization mechanism using DAWPD is effective.
The DAWPD's effectiveness on wideband linearization is also further validated through the simulation of IMD3. The IMD3 simulation was carried out across the operating bandwidth and is presented before and after DAWPD integration in Figure 12. By adopting the IMD3 specification of −30 dBc, it is observed that with DAWPD's integration, the PA can meet the specification up to 25.5 dBm output power at 2.45 GHz. Meanwhile, at 1.7 and 2.7 GHz, the PA can meet the specification up to 24 and 23.5 dBm, respectively. After integrating and tuning the DAWPD, it is observed that the IMD3 was significantly enhanced at high output power levels. The IMD3 is extended up to 28 dBm at 2.45 GHz, 27.2 dBm at 1.7 GHz, and 27 dBm at 2.7 GHz. The digital bits of the DAWPD were tuned to achieve the low peaks of IMD3, which occur from −50 to −60 dBc at high output-power levels across the frequency. The low peaks of the IMD3 are regarded as the "sweet spot," which reflects the region of the maximum IMD3 product cancellation. phase responses and their resultant AM-PM are illustrated in Figure 11a,b, respectively. Figure 11b shows that the resultant AM-PM deviation is about 4° up to the output power of 26 dBm at 1.7 GHz. Deviations by 4° in AM-PM are achieved up to 27.6 and 27.3 dBm at 2.45 and 2.7 GHz, respectively. An AM-PM deviation by 5° or more is approximately equivalent to a gain compression of 1 dB or more [26]. The AM-PM flatness achieved indicates the linearization mechanism using DAWPD is effective. The DAWPD's effectiveness on wideband linearization is also further validated through the simulation of IMD3. The IMD3 simulation was carried out across the operating bandwidth and is presented before and after DAWPD integration in Figure 12. By adopting the IMD3 specification of −30 dBc, it is observed that with DAWPD's integration, the PA can meet the specification up to 25.5 dBm output power at 2.45 GHz. Meanwhile, at 1.7 and 2.7 GHz, the PA can meet the specification up to 24 and 23.5 dBm, respectively. After integrating and tuning the DAWPD, it is observed that the IMD3 was significantly enhanced at high output power levels. The IMD3 is extended up to 28 dBm at 2.45 GHz, 27.2 dBm at 1.7 GHz, and 27 dBm at 2.7 GHz. The digital bits of the DAWPD were tuned to achieve the low peaks of IMD3, which occur from −50 to −60 dBc at high output-power levels across the frequency. The low peaks of the IMD3 are regarded as the "sweet spot," which reflects the region of the maximum IMD3 product cancellation.

Tunable-Output Impedance Matching Network
As aforementioned, the main PA stage was designed with a size of 5 mm to achieve a maximum output power of 30 dBm. However, the PA delivers the maximum output power at its lowest output impedance, as illustrated in the load-pull analysis in Figure 13. The load-pull analysis was conducted at 2.45 GHz. Referring to the load-pull analysis, the PA delivers the maximum output power of 30 dBm at an impedance of 3 Ω. Hence, the output impedance of the main PA needs to be precisely matched to the output load impedance of 50 Ω for maximum power transfer. It is complicated to design a simple impedance transformation matching network which transforms directly from 3 to 50 Ω. This commonly requires multiple stages of a matching network which gradually transform the impedance, especially for wideband applications. The multistage matching network increases the area consumption on-chip and its implementation cost. Thus, the proposed tunable-output impedance matching network eradicates the need for higher order multistage matching networks. The π network shifts the low output impedance (3 Ω) of the main PA to a higher impedance (22 Ω) so that the tunable-output impedance matching network can be designed with low complexity to further shift the output impedance close to the port impedance (50 Ω). The locations of the impedance points are shown in a block diagram as in Figure 14, and its impedance transformation process is illustrated using the Smith chart in Figure 15.

Tunable-Output Impedance Matching Network
As aforementioned, the main PA stage was designed with a size of 5 mm to achieve a maximum output power of 30 dBm. However, the PA delivers the maximum output power at its lowest output impedance, as illustrated in the load-pull analysis in Figure 13. The load-pull analysis was conducted at 2.45 GHz. Referring to the load-pull analysis, the PA delivers the maximum output power of 30 dBm at an impedance of 3 Ω. Hence, the output impedance of the main PA needs to be precisely matched to the output load impedance of 50 Ω for maximum power transfer. It is complicated to design a simple impedance transformation matching network which transforms directly from 3 to 50 Ω. This commonly requires multiple stages of a matching network which gradually transform the impedance, especially for wideband applications. The multistage matching network increases the area consumption on-chip and its implementation cost. Thus, the proposed tunable-output impedance matching network eradicates the need for higher order multistage matching networks. The π network shifts the low output impedance (3 Ω) of the main PA to a higher impedance (22 Ω) so that the tunable-output impedance matching network can be designed with low complexity to further shift the output impedance close to the port impedance (50 Ω). The locations of the impedance points are shown in a block diagram as in Figure 14, and its impedance transformation process is illustrated using the Smith chart in Figure 15.
stage matching networks. The π network shifts the low output impedance (3 Ω) of the main PA to a higher impedance (22 Ω) so that the tunable-output impedance matching network can be designed with low complexity to further shift the output impedance close to the port impedance (50 Ω). The locations of the impedance points are shown in a block diagram as in Figure 14, and its impedance transformation process is illustrated using the Smith chart in Figure 15.  The impedance transformation for maximum output power at 2.45 GHz is taken as an example for delineation. Based on the aforementioned figures, the impedance location at the drain of the PA is represented by Zmain, and the impedance location after the πnetwork is shown by Zπ-net. Meanwhile, the impedance location after implementing the tunable-output impedance matching network is represented by ZL. Overall, the output matching network shifts the location of the impedance from Zmain to ZL. The wideband operation and the PVT robustness of the DAWPD-PA is realized via the tunable-output impedance matching network in which the output impedance, ZL, across the frequencies is shifted near to 50 Ω by varying the VTUNE1 and VTUNE2. This gives tunability of the impedance at the primary and secondary sides of the transformer. As delineated in Figure 16, it can be observed that the output matching network can only provide an impedance near to 50 Ω for limited frequencies. Based on Figure 16, it is also observed that the impedance location for 1.7, 2.45, and 2.7 GHz can be brought near to 50 Ω with tuning, which reflects the effectiveness of the tunable-output impedance matching network at tuning the output impedance of the DAWPD-PA. The impedance transformation for maximum output power at 2.45 GHz is taken as an example for delineation. Based on the aforementioned figures, the impedance location at the drain of the PA is represented by Zmain, and the impedance location after the πnetwork is shown by Zπ-net. Meanwhile, the impedance location after implementing the tunable-output impedance matching network is represented by ZL. Overall, the output matching network shifts the location of the impedance from Zmain to ZL. The wideband operation and the PVT robustness of the DAWPD-PA is realized via the tunable-output impedance matching network in which the output impedance, ZL, across the frequencies is shifted near to 50 Ω by varying the VTUNE1 and VTUNE2. This gives tunability of the impedance at the primary and secondary sides of the transformer. As delineated in Figure 16, it can be observed that the output matching network can only provide an impedance near to 50 Ω for limited frequencies. Based on Figure 16, it is also observed that the impedance location for 1.7, 2.45, and 2.7 GHz can be brought near to 50 Ω with tuning, which reflects the effectiveness of the tunable-output impedance matching network at tuning the output impedance of the DAWPD-PA. The impedance transformation for maximum output power at 2.45 GHz is taken as an example for delineation. Based on the aforementioned figures, the impedance location at the drain of the PA is represented by Z main, and the impedance location after the π-network is shown by Z π-net . Meanwhile, the impedance location after implementing the tunableoutput impedance matching network is represented by Z L . Overall, the output matching network shifts the location of the impedance from Z main to Z L .
The wideband operation and the PVT robustness of the DAWPD-PA is realized via the tunable-output impedance matching network in which the output impedance, Z L , across the frequencies is shifted near to 50 Ω by varying the V TUNE1 and V TUNE2. This gives tunability of the impedance at the primary and secondary sides of the transformer. As delineated in Figure 16, it can be observed that the output matching network can only provide an impedance near to 50 Ω for limited frequencies. Based on Figure 16, it is also observed that the impedance location for 1.7, 2.45, and 2.7 GHz can be brought near to 50 Ω with tuning, which reflects the effectiveness of the tunable-output impedance matching network at tuning the output impedance of the DAWPD-PA. tunability of the impedance at the primary and secondary sides of the transformer. As delineated in Figure 16, it can be observed that the output matching network can only provide an impedance near to 50 Ω for limited frequencies. Based on Figure 16, it is also observed that the impedance location for 1.7, 2.45, and 2.7 GHz can be brought near to 50 Ω with tuning, which reflects the effectiveness of the tunable-output impedance matching network at tuning the output impedance of the DAWPD-PA.  The Z L is derived based on the equivalent circuit depicted in Figure 17. Referring to Figure 17, the Z main is the main PA's output impedance, expressed in (16). C 15 , L 7 , C 16, and C 17 are the π network implemented before the tunable-output impedance matching network. C 18 and R O10 are the primary CST components, in which R O10 is the output resistance of Q 10 while L p is the inductance of the primary winding. On the secondary side, C 19 and R O11 are the secondary CST components in which R O11 is the output resistance of Q 11 while L s is the inductance of the secondary winding. The k is the coupling factor of the transformer. To simplify the analysis, the transformer in the circuit is replaced with a T-model equivalent circuit, and the schematic is modified, as illustrated in Figure 18 [27]. The ZL is derived based on the equivalent circuit depicted in Figure 17. Referring to Figure 17, the Zmain is the main PA's output impedance, expressed in (16). C15, L7, C16, and C17 are the π network implemented before the tunable-output impedance matching network. C18 and RO10 are the primary CST components, in which RO10 is the output resistance of Q10 while Lp is the inductance of the primary winding. On the secondary side, C19 and RO11 are the secondary CST components in which RO11 is the output resistance of Q11 while Ls is the inductance of the secondary winding. The k is the coupling factor of the transformer. To simplify the analysis, the transformer in the circuit is replaced with a T-model equivalent circuit, and the schematic is modified, as illustrated in Figure 18 [27].
For simplicity of analysis, the ZL is derived stage by stage. The impedance after the implementation of the π network, Zπ-net is derived as: Hence, ZL is derived as in (19). Referring to (19), it can be perceived that the CST components appear in both the real and imaginary parts of the equation, in which they provide the variation in the magnitude and phase of the ZL. When the CST is turned off, the effect of C18, C19, RO10, and RO11 will not vary ZL and, thus, can be eliminated from (19). The ZL is derived based on the equivalent circuit depicted in Figure 17. Referring to Figure 17, the Zmain is the main PA's output impedance, expressed in (16). C15, L7, C16, and C17 are the π network implemented before the tunable-output impedance matching network. C18 and RO10 are the primary CST components, in which RO10 is the output resistance of Q10 while Lp is the inductance of the primary winding. On the secondary side, C19 and RO11 are the secondary CST components in which RO11 is the output resistance of Q11 while Ls is the inductance of the secondary winding. The k is the coupling factor of the transformer. To simplify the analysis, the transformer in the circuit is replaced with a T-model equivalent circuit, and the schematic is modified, as illustrated in Figure 18 [27].  Referring to Figure 18, the transformer is now represented by the inductors (Lp-M), (Ls-M), and M, in which M is the mutual inductance between the primary and secondary windings and can be derived as [28]: For simplicity of analysis, the ZL is derived stage by stage. The impedance after the implementation of the π network, Zπ-net is derived as: Hence, ZL is derived as in (19). Referring to (19), it can be perceived that the CST components appear in both the real and imaginary parts of the equation, in which they provide the variation in the magnitude and phase of the ZL. When the CST is turned off, the effect of C18, C19, RO10, and RO11 will not vary ZL and, thus, can be eliminated from (19). Referring to Figure 18, the transformer is now represented by the inductors (L p -M), (L s -M), and M, in which M is the mutual inductance between the primary and secondary windings and can be derived as [28]: For simplicity of analysis, the Z L is derived stage by stage. The impedance after the implementation of the π network, Z π-net is derived as: Hence, Z L is derived as in (19). Referring to (19), it can be perceived that the CST components appear in both the real and imaginary parts of the equation, in which they provide the variation in the magnitude and phase of the Z L . When the CST is turned off, the effect of C 18 , C 19 , R O10 , and R O11 will not vary Z L and, thus, can be eliminated from (19). Therefore, Z L when the CST is turned off is simplified as derived in (20). Figure 19a shows the simulated S parameters of the DAWPD-PA with the tunableoutput impedance matching network. The simulated performances were obtained from the optimum settings of both the digital bits of the DAWPD and the tunable-output impedance matching network. It can be observed that the resonance points of S 11 and S 22 shifted across the frequency by tuning the tunable-output impedance matching network. The S 11 and S 22 are made to achieve −10 dB across the operating bandwidth to provide optimum input and output return losses, respectively. Referring to Figure 19a, it can be seen that the bandwidth is limited to cover the operating frequency of 1.7 to 2.7 GHz with a single setting. Therefore, the tunable-output impedance matching network is employed to achieve an optimum small-signal parameter across the operating frequency bandwidth. At 1.7 GHz, the S 11 achieved is −23 dB while the S 22 is −11 dB. At 2.45 GHz, the S 11 is −25 dB, while the S 22 achieved is −23 dB. Last but not least, at 2.7 GHz, the S 11 is −15 dB while the S 22 is −28 dB. The small-signal gain (S 21 ) performances do not significantly vary across the frequencies in which it achieved a gain of 30, 31, and 28 dB at 1.7, 2.45, and 2.7 GHz, respectively. Different settings of DAWPD and the tunable-output impedance matching network are utilized to achieve optimum performances across the frequency.
Furthermore, the DAWPD-PA with the tunable-output impedance matching network delivers a maximum output power of 30.2 dBm when simulated at 2.45 GHz. Prior to tuning, the maximum output power degrades by about 1 dB when simulated at 1.7 and 2.7 GHz. After tuning the integrated tunable-output impedance matching network, the maximum output power is enhanced across the frequency bandwidth. The drop in maximum output power is reduced to about 0.5 dB across the frequency. The simulated output power at 1.7 and 2.7 GHz are enhanced to 29.9 and 29.7 dBm, respectively. This validates the effectiveness of the tunable-output impedance matching network in providing an optimum impedance across the bandwidth for high output power and efficiency. Figure 19b shows the simulated power gain and output power performances across the operating bandwidth. It can be observed that the gain and maximum output power are slightly enhanced across the frequency.
to achieve an optimum small-signal parameter across the operating frequency bandwidth. At 1.7 GHz, the S11 achieved is −23 dB while the S22 is −11 dB. At 2.45 GHz, the S11 is −25 dB, while the S22 achieved is −23 dB. Last but not least, at 2.7 GHz, the S11 is −15 dB while the S22 is −28 dB. The small-signal gain (S21) performances do not significantly vary across the frequencies in which it achieved a gain of 30, 31, and 28 dB at 1.7, 2.45, and 2.7 GHz, respectively. Different settings of DAWPD and the tunable-output impedance matching network are utilized to achieve optimum performances across the frequency. Furthermore, the DAWPD-PA with the tunable-output impedance matching network delivers a maximum output power of 30.2 dBm when simulated at 2.45 GHz. Prior to tuning, the maximum output power degrades by about 1 dB when simulated at 1.7 and 2.7 GHz. After tuning the integrated tunable-output impedance matching network, the maximum output power is enhanced across the frequency bandwidth. The drop in maximum output power is reduced to about 0.5 dB across the frequency. The simulated output power at 1.7 and 2.7 GHz are enhanced to 29.9 and 29.7 dBm, respectively. This validates the effectiveness of the tunable-output impedance matching network in providing an optimum impedance across the bandwidth for high output power and efficiency. Figure 19b shows the simulated power gain and output power performances across the operating bandwidth. It can be observed that the gain and maximum output power are slightly enhanced across the frequency.
The PAE performance of the DAWPD-PA was also simulated prior and after tuning the tunable-output impedance matching network as depicted in Figure 19 (c). It is noticeable that prior to tuning, the PAE significantly dropped, by about 8%, when the operating frequency is shifted to 1.7 and 2.7 GHz. Prior to tuning, the peak PAE achieved was 45% at 2.45 GHz, 37% at 1.7 GHz, and 38% at 2.7 GHz. However, the PAE was significantly enhanced across the frequency after tuning the tunable-output impedance matching network. At 2.45 GHz, the peak PAE achieved is 46% while 44% was achieved at both 1.7 and 2.7 GHz. The PAE was enhanced by 7% compared to the PAE prior to tuning, at 1.7 and 2.7 GHz.
In addition, the DAWPD-PA was also simulated across the PVT variations at 2.45 The PAE performance of the DAWPD-PA was also simulated prior and after tuning the tunable-output impedance matching network as depicted in Figure 19c. It is noticeable that prior to tuning, the PAE significantly dropped, by about 8%, when the operating frequency is shifted to 1.7 and 2.7 GHz. Prior to tuning, the peak PAE achieved was 45% at 2.45 GHz, 37% at 1.7 GHz, and 38% at 2.7 GHz. However, the PAE was significantly enhanced across the frequency after tuning the tunable-output impedance matching network. At 2.45 GHz, the peak PAE achieved is 46% while 44% was achieved at both 1.7 and 2.7 GHz. The PAE was enhanced by 7% compared to the PAE prior to tuning, at 1.7 and 2.7 GHz.
In addition, the DAWPD-PA was also simulated across the PVT variations at 2.45 GHz in order to validate its robustness and reliability as compared to our previous research in [16]. The DAWPD-PA was simulated at different corners such as the TT (typical-typical), SS (slow-slow), and FF (fast-fast) corners as well as at different temperatures of +27 • , −25 • , and +125 • . The PVT performances are shown prior to and after tuning the DAWPD-PA in order to validate its reconfigurable feature under PVT variations which degrade its performance. The PAE and power-gain performances at different corners are shown in Figure 20a,b, respectively. From Figure 20a, it can be seen that the peak PAE at FF is better by 4% than its TT value of 46%. For SS, the peak PAE degrades by 8% prior to tuning, which yields a peak PAE of 38%. After tuning both the DAWPD and tunable transformer, the peak PAE is enhanced to 42%, which is an increment by 4% from the lower value. Referring to Figure 20b, the power gain shows a similar trend, wherein it is better in FF and degrades in SS. Prior to tuning, the power gain degrades from 31.5 dB to 27.5 dB in SS and it is enhanced to 29.5 dB after tuning. Furthermore, the PAE and power-gain performances at different temperatures are illustrated in Figure 21a,b, respectively. From Figure 21a, it can be seen that the peak PAE is higher at −25°, by 6%, than its +27° value of 46%. Prior to tuning, the peak PAE degrades by 9% at +125°, which results in a peak PAE of 37%. After tuning, it is feasible to improve the peak PAE to 40%, which is an increment of 3% over its degraded value. Meanwhile, the power gain is also increased at −25° and deteriorated at +125°. Prior to tuning at +125°, the power gain degrades from 31.5 dB to 25.5 dB and it is enhanced to 28.5 dB after tuning, as shown in Figure 21b. The configurability of the DAWPD-PA with tunable-output impedance matching network is validated via the PVT simulation in which the tuning of the digital bits in the DAWPD and tuning of the output impedance matching network improve its performances. Hence, the proposed techniques enhance the functionality of the PA when it is affected by PVT variations as well as contributing to wide-bandwidth operation.  Figure 22 shows the micrograph of the fabricated DAWPD-PA. From our previous study in [16], which included a fixed-output impedance matching network, the design has been modified by adding the CST to the transformer output matching network in order Furthermore, the PAE and power-gain performances at different temperatures are illustrated in Figure 21a,b, respectively. From Figure 21a, it can be seen that the peak PAE is higher at −25 • , by 6%, than its +27 • value of 46%. Prior to tuning, the peak PAE degrades by 9% at +125 • , which results in a peak PAE of 37%. After tuning, it is feasible to improve the peak PAE to 40%, which is an increment of 3% over its degraded value. Meanwhile, the power gain is also increased at −25 • and deteriorated at +125 • . Prior to tuning at +125 • , the power gain degrades from 31.5 dB to 25.5 dB and it is enhanced to 28.5 dB after tuning, as shown in Figure 21b. The configurability of the DAWPD-PA with tunable-output impedance matching network is validated via the PVT simulation in which the tuning of the digital bits in the DAWPD and tuning of the output impedance matching network improve its performances. Hence, the proposed techniques enhance the functionality of the PA when it is affected by PVT variations as well as contributing to wide-bandwidth operation. Furthermore, the PAE and power-gain performances at different temperatures are illustrated in Figure 21a,b, respectively. From Figure 21a, it can be seen that the peak PAE is higher at −25°, by 6%, than its +27° value of 46%. Prior to tuning, the peak PAE degrades by 9% at +125°, which results in a peak PAE of 37%. After tuning, it is feasible to improve the peak PAE to 40%, which is an increment of 3% over its degraded value. Meanwhile, the power gain is also increased at −25° and deteriorated at +125°. Prior to tuning at +125°, the power gain degrades from 31.5 dB to 25.5 dB and it is enhanced to 28.5 dB after tuning, as shown in Figure 21b. The configurability of the DAWPD-PA with tunable-output impedance matching network is validated via the PVT simulation in which the tuning of the digital bits in the DAWPD and tuning of the output impedance matching network improve its performances. Hence, the proposed techniques enhance the functionality of the PA when it is affected by PVT variations as well as contributing to wide-bandwidth operation.  Figure 22 shows the micrograph of the fabricated DAWPD-PA. From our previous study in [16], which included a fixed-output impedance matching network, the design has been modified by adding the CST to the transformer output matching network in order  Figure 22 shows the micrograph of the fabricated DAWPD-PA. From our previous study in [16], which included a fixed-output impedance matching network, the design has been modified by adding the CST to the transformer output matching network in order to realize the tunability mechanism. The added tuner is varied via the bond pad employed for V TUNE1 and V TUNE2 . Fabricated in 130 nm CMOS technology with eight metal layers, the DAWPD-PA consumes an area of 2.37 mm 2 on-chip, including the bond pads for measurement. The DAWPD-PA was first measured for small-signal performance with a continuous-wave (CW) signal, and Figure 23a shows the S parameters when the digital states are varied for the operating frequency of 1.7, 2.45, and 2.7 GHz. The measured S 11 were −17.8, −16.4, and −12.1 dB at 1.7, 2.45, and 2.7 GHz. Meanwhile, the measured S 22 were −13.4, −16.2, and −19.7 dB at 1.7, 2.45, and 2.7 GHz, respectively. In addition, the S 21 attained were 28.2 dB at 1.7 GHz, 29.1 dB at 2.45 GHz, and 26.7 dB at 2.7 GHz. Furthermore, the DAWPD-PA was also measured for large-signal performances with the CW signal. Figure 23b shows the power-gain performance, and it can be seen that the attained power gains across frequencies were 28.9, 29.7, and 26.9  to realize the tunability mechanism. The added tuner is varied via the bond pad employed for VTUNE1 and VTUNE2. Fabricated in 130 nm CMOS technology with eight metal layers, the DAWPD-PA consumes an area of 2.37 mm 2 on-chip, including the bond pads for measurement. The DAWPD-PA was first measured for small-signal performance with a continuous-wave (CW) signal, and Figure 23a shows the S parameters when the digital states are varied for the operating frequency of 1.7, 2.45, and 2.7 GHz. The measured S11 were −17.  Figure 23b shows the power-gain performance, and it can be seen that the attained power gains across frequencies were 28.9, 29.7, and 26.  The AM-PM performance of the DAWPD-PA was also measured, and its phase deviation versus output power at different frequencies with its respective tuning states are illustrated in Figure 24a. The measured phase deviations of 4° were observed up to an output power of 24.9 dBm at 1.7 GHz, 25.4 dBm at 2.45 GHz, and 24.3 at 2.7 GHz. A phase deviation of 5° or more indicates the 1-dB compression point where the PA enters the nonlinear region. In addition, the PAE performance across the frequencies is depicted in Figure 24b. The peak PAE attained at 1.7 GHz was 38.8%, while at 2.45 and 2.7 GHz, the peak PAE was 41.3% and 38.9%, respectively. In addition, the PAE obtained at 3-dB backed-off to realize the tunability mechanism. The added tuner is varied via the bond pad employed for VTUNE1 and VTUNE2. Fabricated in 130 nm CMOS technology with eight metal layers, the DAWPD-PA consumes an area of 2.37 mm 2 on-chip, including the bond pads for measurement. The DAWPD-PA was first measured for small-signal performance with a continuous-wave (CW) signal, and Figure 23a shows the S parameters when the digital states are varied for the operating frequency of 1.  Figure 23b shows the power-gain performance, and it can be seen that the attained power gains across frequencies were 28.9, 29.7, and 26.  The AM-PM performance of the DAWPD-PA was also measured, and its phase deviation versus output power at different frequencies with its respective tuning states are illustrated in Figure 24a. The measured phase deviations of 4° were observed up to an output power of 24.9 dBm at 1.7 GHz, 25.4 dBm at 2.45 GHz, and 24.3 at 2.7 GHz. A phase deviation of 5° or more indicates the 1-dB compression point where the PA enters the nonlinear region. In addition, the PAE performance across the frequencies is depicted in Fig-Figure 23. Measured (a) S parameters and (b) power-gain performances.

Measurement Results
The AM-PM performance of the DAWPD-PA was also measured, and its phase deviation versus output power at different frequencies with its respective tuning states are illustrated in Figure 24a. The measured phase deviations of 4 • were observed up to an output power of 24.9 dBm at 1.7 GHz, 25.4 dBm at 2.45 GHz, and 24.3 at 2.7 GHz. A phase deviation of 5 • or more indicates the 1-dB compression point where the PA enters the non-linear region. In addition, the PAE performance across the frequencies is depicted in Figure 24b. The peak PAE attained at 1.7 GHz was 38.8%, while at 2.45 and 2.7 GHz, the peak PAE was 41.3% and 38.9%, respectively. In addition, the PAE obtained at 3-dB backedoff output power for the frequencies of 1.7, 2.45, and 2.7 GHz are 34.5%, 38.8%, and 36.3%, respectively. The 3-dB P bo is the linear operating region where the DAWPD-PA satisfies the adjacent-channel-leakage-ratio (ACLR) specification when tested with a 20 MHz/16 QAM LTE-modulated signal.  Figure 25a shows the ACLR attained for the different frequencies, and it can be observed that the ACLR specification of −30 dBc was fulfilled up to an output power of 24.3 dBm at 1.7 GHz, 25.1 dBm at 2.45 GHz, and 24 dBm at 2.7 GHz. In addition, the error vector magnitude (EVM) performance of the DAWPD-PA was also measured, and its result is depicted in Figure 25b. The preferred EVM specification is less than −27.96 dB (4%), indicating the optimum in-band linearity requirement when tested with a 16 QAM LTE signal. Referring to Figure 25b, it can be observed that at 2.45 GHz, the EVM achieved is less than −27.96 dB (4%) up to an output power of 25.7 dBm. At 1.7 and 2.7 GHz, the EVM is within specification up to output powers of 25.5 and 24.3 dBm, respectively. The measured ACLR and EVM of the DAWPD-PA with tuned conditions are also illustrated via the power spectral density (PSD) and EVM constellation diagram. The PSD measured at different frequencies is depicted in Figure 26a-c, where the spectral mask of  Figure 25a shows the ACLR attained for the different frequencies, and it can be observed that the ACLR specification of −30 dBc was fulfilled up to an output power of 24.3 dBm at 1.7 GHz, 25.1 dBm at 2.45 GHz, and 24 dBm at 2.7 GHz. In addition, the error vector magnitude (EVM) performance of the DAWPD-PA was also measured, and its result is depicted in Figure 25b. The preferred EVM specification is less than −27.96 dB (4%), indicating the optimum in-band linearity requirement when tested with a 16 QAM LTE signal. Referring to Figure 25b, it can be observed that at 2.45 GHz, the EVM achieved is less than −27.96 dB (4%) up to an output power of 25.7 dBm. At 1.7 and 2.7 GHz, the EVM is within specification up to output powers of 25.5 and 24.3 dBm, respectively.
The measured ACLR and EVM of the DAWPD-PA with tuned conditions are also illustrated via the power spectral density (PSD) and EVM constellation diagram. The PSD measured at different frequencies is depicted in Figure 26a-c, where the spectral mask of the modulated signal is shown. The sidebands are kept within the specification of −30 dBc up to their linear output power across the frequencies (24 dBm at 1.7 and 2.7 GHz, 25 dBm at 2.45 GHz). On the other hand, it can be seen from the measured EVM constellation diagram that the symbols fall within the constellation with minimum deviation when measured at maximum linear output power. Figure 27a-c illustrates the EVM constellation diagram at the aforementioned frequencies.
dBm at 1.7 GHz, 25.1 dBm at 2.45 GHz, and 24 dBm at 2.7 GHz. In addition, the error vector magnitude (EVM) performance of the DAWPD-PA was also measured, and its result is depicted in Figure 25b. The preferred EVM specification is less than −27.96 dB (4%), indicating the optimum in-band linearity requirement when tested with a 16 QAM LTE signal. Referring to Figure 25b, it can be observed that at 2.45 GHz, the EVM achieved is less than −27.96 dB (4%) up to an output power of 25.7 dBm. At 1.7 and 2.7 GHz, the EVM is within specification up to output powers of 25.5 and 24.3 dBm, respectively. The measured ACLR and EVM of the DAWPD-PA with tuned conditions are also illustrated via the power spectral density (PSD) and EVM constellation diagram. The PSD measured at different frequencies is depicted in Figure 26a-c, where the spectral mask of the modulated signal is shown. The sidebands are kept within the specification of −30 dBc up to their linear output power across the frequencies (24 dBm at 1.7 and 2.7 GHz, 25 dBm On top of that, 10 chip samples or device under tests (DUTs) were tested to validate the resilience and reliability of the DAWPD-PA when subjected to PVT variations. The performance consistency of the designed DAWPD-PA is justified by measuring different dice from the wafer at different temperatures and corners. The measurement was conducted at 2.45 GHz for all the 10 DUTs. The tunable-output impedance matching network and the digital linearizer were adjusted to attain the optimum performances when the PA is affected by the PVT variations. The DAWPD-PA's reliability and manufacturing yield increase because most of the fabricated designs are usable and functioning as intended. Figure 28 shows the linear PAE, linear output power gain, and ACLR performances at 2.45 GHz across the PVT variations for 10 samples. Table 1 delineates the performance summary of the DAWPD-PA and comparison with other recent CMOS PAs. On top of that, 10 chip samples or device under tests (DUTs) were tested to validate the resilience and reliability of the DAWPD-PA when subjected to PVT variations. The performance consistency of the designed DAWPD-PA is justified by measuring different dice from the wafer at different temperatures and corners. The measurement was conducted at 2.45 GHz for all the 10 DUTs. The tunable-output impedance matching network and the digital linearizer were adjusted to attain the optimum performances when the PA is affected by the PVT variations. The DAWPD-PA's reliability and manufacturing yield increase because most of the fabricated designs are usable and functioning as intended. Figure 28 shows the linear PAE, linear output power gain, and ACLR performances at 2.45 GHz across the PVT variations for 10 samples. Table 1 delineates the performance On top of that, 10 chip samples or device under tests (DUTs) were tested to validate the resilience and reliability of the DAWPD-PA when subjected to PVT variations. The performance consistency of the designed DAWPD-PA is justified by measuring different dice from the wafer at different temperatures and corners. The measurement was conducted at 2.45 GHz for all the 10 DUTs. The tunable-output impedance matching network and the digital linearizer were adjusted to attain the optimum performances when the PA is affected by the PVT variations. The DAWPD-PA's reliability and manufacturing yield increase because most of the fabricated designs are usable and functioning as intended. Figure 28 shows the linear PAE, linear output power gain, and ACLR performances at 2.45 GHz across the PVT variations for 10 samples. Table 1 delineates the performance summary of the DAWPD-PA and comparison with other recent CMOS PAs.

Conclusions
The 130 nm wideband CMOS DAWPD-PA with tunable-output impedance matching network delivered an operating bandwidth from 1.7 to 2.7 GHz. The DAWPD with a digital implementation and active load offers a tunable wideband linearization across the aforementioned frequency. It also utilizes a tunable impedance matching network realized via a transformer and tuner circuits to reconfigure its performances when impacted by PVT variations. The maximum output power attained by the wideband DAWPD-PA is 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. A linear output power of 24 to 25.1 dBm with linear PAE of 34.5 to 38.8% was achieved when tested with a 20 MHz LTE-modulated signal. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations in which it improves the design's robustness, reliability and production yield. Its performances can be maintained via the design's tuning property, which is proven when 10 DUTs were tested across different corners and temperatures. The tuning of the digital-bit states of the DAWPD and the tuning of the tunable-output impedance matching network realize the reconfigurable wideband CMOS PA with high robustness.

Conclusions
The 130 nm wideband CMOS DAWPD-PA with tunable-output impedance matching network delivered an operating bandwidth from 1.7 to 2.7 GHz. The DAWPD with a digital implementation and active load offers a tunable wideband linearization across the aforementioned frequency. It also utilizes a tunable impedance matching network realized via a transformer and tuner circuits to reconfigure its performances when impacted by PVT variations. The maximum output power attained by the wideband DAWPD-PA is 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. A linear output power of 24 to 25.1 dBm with linear PAE of 34.5 to 38.8% was achieved when tested with a 20 MHz LTE-modulated signal. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations in which it improves the design's robustness, reliability and production yield. Its performances can be maintained via the design's tuning property, which is proven when 10 DUTs were tested across different corners and temperatures. The tuning of the digital-bit states of the DAWPD and the tuning of the tunable-output impedance matching network realize the reconfigurable wideband CMOS PA with high robustness.