Fabrication of Substrate-Integrated Waveguide Using Micromachining of Photoetchable Glass Substrate for 5G Millimeter-Wave Applications

A millimeter-wave substrate-integrated waveguide (SIW) was firstly demonstrated using the micromachining of photoetchable glass (PEG) for 5G applications. A PEG substrate was used as a dielectric material of the SIW, and its photoetchable properties were used to fabricate through glass via (TGV) holes. Instead of the conventional metallic through glass via (TGV) array structures that are typically used for the SIW, two continuous empty TGV holes with metallized sidewalls connecting the top metal layer to the bottom ground plane were used as waveguide walls. The proposed TGV walls were fabricated by using optical exposure, heat development and anisotropic HF (hydrofluoric acid) etching of the PEG substrate, followed by a metal sputtering technique. The SIW was fed by microstrip lines connected to the waveguide through tapered microstrip-to-waveguide transitions. The top metal layer, including these feedlines and transitions, was fabricated by selective metal sputtering through a silicon shadow mask, which was prefabricated by a silicon deep-reactive ion-etching (DRIE) technique. The developed PEG-based process provides a relatively simple, wafer-level manufacturing method to fabricate the SIW in a low-cost glass dielectric substrate, without the formation of individual of TGV holes, complex time-consuming TGV filling processes and repeated photolithographic steps. The fabricated SIW had a dimension of 6 × 10 × 0.42 mm3 and showed an average insertion loss of 2.53 ± 0.55 dB in the Ka-band frequency range from 26.5 GHz to 40 GHz, with a return loss better than 13.86 dB. The proposed process could be used not only for SIW-based devices, but also for various millimeter-wave applications where a glass substrate with TGV structures is required.


Introduction
The advent of 5G communications has been accelerating the development of radio frequency (RF) devices and components working at millimeter-wave frequencies. For many millimeter-wave applications, such as wireless communications, automotive radars, highresolution imaging systems and gigabit backbone networks, demand for small-footprint, high-density, low-loss and low-cost system integration is continuously increasing [1,2]. Packaging substrates or interposers with through substrate via structures are widely used to demonstrate 2.5D/3D packaging schemes with the fabricated devices [3][4][5][6]. In the choice of the substrate or interposer material, various factors, such as an electrical loss, precision machineability, processing yield and mechanical stability, should be considered. Conventional dielectric substrates with a low dissipation factor (tan δ) used for millimeterwave applications include traditional printed circuit boards (PCBs) and low-temperature co-fired ceramics (LTCCs) [7], as well as organic substrates, such as liquid crystal polymers (LCPs) [8] and polytetrafluoroethylenes (PTFEs) [9]. LTCC is a robust packaging substrate

Dielectric Properties of PEG Substrate
PEGs, which are normally known by their trademark names, such as FORTURAN (Schott, Germany) or APEX (Life Bioscience Inc., Albuquerque, NM, USA), are lithium aluminum silicates with some well-defined impurities of metal oxides that significantly contribute to photosensitive properties. These impurities include photosensitive metals, with silver (Ag) being used more than others, and optical sensitizers, among which cerium (Ce) is the most important. Typical procedures to fabricate microstructures in PEG are described in the literature [37,38]. The PEG substrate is first exposed to mid-to-near UV light whose wavelength ranges from 260 to 360 nm through a photomask, which is normally composed of quartz. Ce 3+ ions absorb photons and release one electron to enter the stable Ce 4+ state, and this electron is absorbed by Ag + ions reduced to Ag atoms. The exposed glass is then heated to higher temperatures, typically between 580~680 • C. During this "heat development" process, Ag atoms are clustered into bigger nuclei around which the glass crystallizes to form lithium metasilicate (Li 2 SiO 3 ), producing the latent image of the photomask [39]. The exposed region can be etched away, typically in a solution of 10% hydrofluoric acid (HF), because the etching ratio between the crystallized parts and bulk part is known to be more than 20:1 [27].
To design the SIW using PEG, the electrical properties of the PEG substrate need to be evaluated. In our study, the dielectric constant and loss tangent of the PEG substrate (MEG2; MicroFab, Seoul, Republic of Korea) at 28 GHz were experimentally measured using a split cylinder resonator method [40], where the cylindrical resonator is split in the middle and a plate sample is placed between the two. The permittivity is obtained from the change in frequency and the dielectric loss is obtained from the change in Q values. The split cylinder uses the TE 011 mode of resonance, where the electric flux circulates in the sample plane, eliminating the negative effects of ends and allowing accurate measurements. PEG plate samples were fabricated by dicing the substrate into a rectangular plate of 30 mm × 50 mm, followed by polishing them down to the thickness of 154 µm. Two different samples were prepared, one of which is an original unprocessed PEG, while the other is thermally treated at a temperature of 585 • C for 2 h to emulate the heat development conditions. The prepared samples were loaded in the split cylinder resonator (CR-728; EMLabs, Kobe, Japan) and measured using a vector network analyzer (N5291A; Keysight Technologies, Santa Rosa, CA, USA). The measured results are summarized in Table 1. The dielectric constant slightly decreased from 6.1 to 5.8 after heat development, but the loss tangent values were almost the same for both samples. In the design of the SIW, therefore, a dielectric constant of 5.8 and a loss tangent of 0.014 were used. The measured values are similar to the reported value of PEG at 60 GHz, which was a dielectric constant of 6.4 and a loss tangent of 0.022 [15].

Design and Simulation of SIW
In our work, SIW was selected to demonstrate the potential of PEG in the millimeterwave regimes. The entire three-dimensional schematic view of the proposed SIW is illustrated in Figure 1. The SIW is composed of a PEG dielectric substrate, TGVs, top metal patterns and bottom ground metal layer. Instead of forming the cylindrical metal-filled via arrays normally used for SIWs, two continuous rectangular empty TGV holes with their vertical sidewalls coated with a thin metal layer were utilized. These metal-coated TGV holes behave like the conductor walls of a conventional 3D rectangular waveguide. Therefore, leakage loss through the gap between the via arrays of the conventional SIW is minimized. The TGV holes can be fabricated in a waver level using the photoetchable properties of PEG, by following the procedures briefly described in Section 2.1. Instead of filling the TGV holes using photolithography and electroplating processes, only the sidewalls of the TGV holes are coated with thin metal layers during the consecutive two sputtering processes: one selective sputtering for the top metal patterns (including microstrip feedlines and tapered transitions) using a silicon shadow mask fabricated by silicon deep-reactive ion-etching (DRIE), and another, final sputtering without any shadow mask for the bottom ground metals. The proposed process does not require additional photolithographic processes to pattern the top metal layers, which is difficult to perform on the wafer with TGV holes. Furthermore, the via-filling process using electroplating-which is also difficult and takes a long time to obtain completely filled, void-free metallic vias for a substrate with a thickness of hundreds of micrometers-is also not necessary. The precision of the top metal patterns, which is important to fabricate millimeter-wave devices that usually have small sizes, could be determined by the accuracy of the silicon DRIE process, which is normally a few micrometers. In addition, the fabricated silicon shadow mask can be repeatedly used for the process of other substrates. These characteristics of the proposed process could make wafer-level fabrication process of the SIW relatively simpler than the previous works using TGV structures.  When the width of the waveguide is larger than its thickness, the cutoff frequency of the dominant TE 10 mode is given by the following well-known equations [41]: where f c,10 is the cutoff frequency of TE 10 mode, w is the width of the waveguide, ε r is the dielectric constant of the substrate and c is the speed of light in free space. In our study, an SIW with a cutoff frequency of 20.7 GHz was designed and optimized using commercial full-wave electromagnetic simulation software (Ansys HFSS, R16). The PEG substrate was supplied in the form of a 100 mm × 100 mm square plate with a thickness of 420 µm; thus, the thickness of the SIW (h) was also fixed to the same value here. A 50 Ω microstrip line was used for the feeding lines, and linearly tapered microstrip line transitions were connected between the microstrip line and the SIW to transform the quasi-TEM mode of the microstrip line into the TE 10 mode in the waveguide [42]. Smooth transition using this tapered transformer ensures field matching between the microstrip line and the waveguide over a broad bandwidth. After determining the waveguide width, the tapered section was designed using HFSS simulation, interrelating the line width of the microstrip line with the width of the SIW. The top view of the designed SIW metal pattern on the PEG substrate is shown in Figure 2. Detailed dimensions are w v = 0.205 mm, L v = 3.6 mm, w ms = 0.64 mm, L ms = 1.6 mm, w t = 1.2 mm, L t = 1.5 mm, L = 3.95 mm and w = 3.0 mm, respectively.  The simulated S-parameters of the designed SIW are shown in Figure 3. The average insertion loss of the SIW at the Ka-band (26.5 GHz to 40 GHz), including all microstrip feedlines and transitions, was estimated to be 1.41 ± 0.13 dB (1.79 dB at 40 GHz). In the photomask designed to fabricate the silicon shadow mask, the designed SIW and microstrip line patterns were included.

Fabrication Process
The overall fabrication process of the proposed SIW is illustrated in Figure 4. A 420 μm thick, 100 mm × 100 mm square-shaped PEG substrate was used as a dielectric substrate of the SIW. To create the TGV holes for the SIW, the glass substrate was firstly ex-

Fabrication Process
The overall fabrication process of the proposed SIW is illustrated in Figure 4. A 420 µm thick, 100 mm × 100 mm square-shaped PEG substrate was used as a dielectric substrate of the SIW. To create the TGV holes for the SIW, the glass substrate was firstly exposed by a 310 nm near-UV light source (ML-100F; Mikasa Co., Ltd., Tokyo, Japan) with a dose of 7.92 J/cm 2 using a soda-lime glass photomask ( Figure 4a). As mentioned in Section 2.1, a quartz mask that can transmit the required wavelength of 310 nm well is normally utilized. In our experiment, however, exposure conditions were optimized for a soda-lime glass mask because the quartz mask is expensive and also very sensitive to the optical dose. Then, the exposed substrate was heat developed and polished ( Figure 4b). The heat development conditions were carefully managed to minimize the dimensional changes of the patterns. The substrate was first heated up in the furnace to 350 • C with a rate of 3 • C/min and maintained for 30 min. The furnace temperature was further increased up to 585 • C with a rate of 2 • C/min and maintained for 2 h, and then the substrate was naturally cooled down to the room temperature. During this heat treatment step, the exposed area became foggy due to the crystallization of glass around Ag nanoclusters. Before the etching of the exposed region, both sides of the glass substrate were polished by chemical mechanical polishing (CMP). This CMP step is very important in order to keep the surface roughness of the PEG substrate as smooth as possible during the following etching step, which, in turn, affects the conductor loss of the deposited metal layer onto the substrate. The heat-developed substrate was dipped into a 10% HF solution for 450 s to etch away the exposed TGV regions (Figure 4c). The etch rate of the glass was measured to be about 60 µm/min.  After HF etching, both sides of the PEG substrate are metallized ( Figure 4d). First, top metal patterns, including waveguide, transitions and microstrip feedlines, were formed by the selective sputtering of a Ti/Cu (10 nm/500 nm) layer through the prefabricated silicon shadow mask, which is precisely aligned with the substrate. A 4-inch, 350 μm thick single crystal silicon wafer was etched through into the shape of the SIW pattern by the DRIE of silicon using an oxide etch mask, and it was utilized as a shadow mask for metal patterning (the shadow mask fabrication process is not shown in Figure 4). During this process, the sidewalls of the TGV holes were deposited with copper to some extent. Then, the bottom surface was coated with a metal layer, which is a ground plane of the SIW, by further Ti/Cu sputtering without any shadow mask. During these two consecutive sputtering processes, the sidewalls of the TGV holes were twice-covered with the deposited metal. Good electrical connections between the top and bottom metal layers were made thanks to the excellent step coverage of the sputtering process. Finally, the substrate After HF etching, both sides of the PEG substrate are metallized (Figure 4d). First, top metal patterns, including waveguide, transitions and microstrip feedlines, were formed by the selective sputtering of a Ti/Cu (10 nm/500 nm) layer through the prefabricated silicon shadow mask, which is precisely aligned with the substrate. A 4-inch, 350 µm thick single crystal silicon wafer was etched through into the shape of the SIW pattern by the DRIE of silicon using an oxide etch mask, and it was utilized as a shadow mask for metal patterning (the shadow mask fabrication process is not shown in Figure 4). During this process, the sidewalls of the TGV holes were deposited with copper to some extent. Then, the bottom surface was coated with a metal layer, which is a ground plane of the SIW, by further Ti/Cu sputtering without any shadow mask. During these two consecutive sputtering processes, the sidewalls of the TGV holes were twice-covered with the deposited metal. Good electrical connections between the top and bottom metal layers were made thanks to the excellent step coverage of the sputtering process. Finally, the substrate was diced out into a 6 mm × 10 mm sample for measurement (Figure 4e).
The PEG substrate exposed to the UV light and heat developed in the furnace is shown in Figure 5a. As described, the exposed region became opaque due to the crystallization effect. After polishing both sides of the substrate and etching it in a 10% HF solution, TGV holes were successfully fabricated, as shown in Figure 5b. The fabricated silicon shadow mask for the following selective metal deposition is shown in Figure 5c. The top and bottom views of the fabricated SIW sample after dicing are shown in Figure 5d.
top metal patterns, including waveguide, transitions and microstrip feedlines, were formed by the selective sputtering of a Ti/Cu (10 nm/500 nm) layer through the prefabricated silicon shadow mask, which is precisely aligned with the substrate. A 4-inch, 350 μm thick single crystal silicon wafer was etched through into the shape of the SIW pattern by the DRIE of silicon using an oxide etch mask, and it was utilized as a shadow mask for metal patterning (the shadow mask fabrication process is not shown in Figure 4). During this process, the sidewalls of the TGV holes were deposited with copper to some extent. Then, the bottom surface was coated with a metal layer, which is a ground plane of the SIW, by further Ti/Cu sputtering without any shadow mask. During these two consecutive sputtering processes, the sidewalls of the TGV holes were twice-covered with the deposited metal. Good electrical connections between the top and bottom metal layers were made thanks to the excellent step coverage of the sputtering process. Finally, the substrate was diced out into a 6 mm × 10 mm sample for measurement (Figure 4e).
The PEG substrate exposed to the UV light and heat developed in the furnace is shown in Figure 5a. As described, the exposed region became opaque due to the crystallization effect. After polishing both sides of the substrate and etching it in a 10% HF solution, TGV holes were successfully fabricated, as shown in Figure 5b. The fabricated silicon shadow mask for the following selective metal deposition is shown in Figure 5c. The top and bottom views of the fabricated SIW sample after dicing are shown in Figure 5d.

Experimental Results and Discussion
Before measuring the RF performances of the fabricated SIW, the dimensions of each part of the sample were measured and compared with the designed values, as shown in Table 2. The fabricated dimensions tended to be smaller than the designed values, which might be caused by various factors, such as the resolution of the PEG process, an alignment error between the shadow mask and PEG substrate, warpage of the silicon or PEG substrate, inaccuracy or nonuniformity of the DRIE-etched patterns in the silicon shadow mask, etc. It can be seen that the parameters , and , which are directly related to the resolution of the PEG patterning process, do not deviate much from the design. However, the other parameters, specifically depending on the size of the shadow mask patterns and physical state of the substrates, showed relatively larger disparities from the designed values, with a maximum deviation of up to 40 μm. The effect of these dimensional variations on the RF performances, thus, cannot be completely ignored, especially for the case of millimeter-wave devices where high-dimensional accuracies are required. Therefore, EM simulation of the SIW was performed again using these measured dimensions, and the results were compared with the measurement results.

Experimental Results and Discussion
Before measuring the RF performances of the fabricated SIW, the dimensions of each part of the sample were measured and compared with the designed values, as shown in Table 2. The fabricated dimensions tended to be smaller than the designed values, which might be caused by various factors, such as the resolution of the PEG process, an alignment error between the shadow mask and PEG substrate, warpage of the silicon or PEG substrate, inaccuracy or nonuniformity of the DRIE-etched patterns in the silicon shadow mask, etc. It can be seen that the parameters w v , L v and w, which are directly related to the resolution of the PEG patterning process, do not deviate much from the design. However, the other parameters, specifically depending on the size of the shadow mask patterns and physical state of the substrates, showed relatively larger disparities from the designed values, with a maximum deviation of up to 40 µm. The effect of these dimensional variations on the RF performances, thus, cannot be completely ignored, especially for the case of millimeterwave devices where high-dimensional accuracies are required. Therefore, EM simulation of the SIW was performed again using these measured dimensions, and the results were compared with the measurement results. The RF performances of the fabricated SIW were measured using a commercially available universal test fixture (3680V; Anritsu Corp., Atsugi, Japan) and a vector network analyzer (N5227B; Keysight Technologies, Santa Rosa, CA, USA). The experimental setup is shown in Figure 6. A standard SOLT (Short-Open-Load-Thru) calibration process was performed with a commercial calibration kit (36804B-10M; Anritsu Corp., Atsugi, Japan) for calibration.  The measured S-parameters of the fabricated SIW were compared with the simulation results in Figure 7. It can be seen that the simulated average insertion loss increased to 2.05 ± 0.24 dB (2.65 dB at 40 GHz) when the dimensional changes from the original design were reflected in the simulation. The measured S-parameters, as expected and shown in the figure, agree well with these new simulation results, including these fabrication errors. The measured average insertion loss of the fabricated SIW, however, saw a somewhat higher value of 2.53 ± 0.55 dB (2.94 dB at 40 GHz), mainly due to the increase in measured loss above 32 GHz. For the purpose of comparison, the measured S-parameters of a 10 mm long, 50 Ω microstrip line fabricated on the same PEG substrate is shown in Figure 8. In the Ka-band, the insertion loss of the microstrip line was measured to be 2.26 ± 0.37 dB (2.49 dB at 40 GHz). The measured S-parameters of the fabricated SIW were compared with the simulation results in Figure 7. It can be seen that the simulated average insertion loss increased to 2.05 ± 0.24 dB (2.65 dB at 40 GHz) when the dimensional changes from the original design were reflected in the simulation. The measured S-parameters, as expected and shown in the figure, agree well with these new simulation results, including these fabrication errors. The measured average insertion loss of the fabricated SIW, however, saw a somewhat higher value of 2.53 ± 0.55 dB (2.94 dB at 40 GHz), mainly due to the increase in measured loss above 32 GHz. For the purpose of comparison, the measured S-parameters of a 10 mm long, 50 Ω microstrip line fabricated on the same PEG substrate is shown in Figure 8. In the Ka-band, the insertion loss of the microstrip line was measured to be 2.26 ± 0.37 dB (2.49 dB at 40 GHz).
shown in the figure, agree well with these new simulation results, including these fabrication errors. The measured average insertion loss of the fabricated SIW, however, saw a somewhat higher value of 2.53 ± 0.55 dB (2.94 dB at 40 GHz), mainly due to the increase in measured loss above 32 GHz. For the purpose of comparison, the measured S-parameters of a 10 mm long, 50 Ω microstrip line fabricated on the same PEG substrate is shown in Figure 8. In the Ka-band, the insertion loss of the microstrip line was measured to be 2.26 ± 0.37 dB (2.49 dB at 40 GHz).  The measured insertion loss of the fabricated PEG SIW is higher than that of the reported SIWs fabricated on the borosilicate glass [16,21,22]. One main reason for this is the higher dissipation factor (0.016) of PEG, which is an order of magnitude higher than the borosilicate glass (0.0037 at 1 MHz [16,21], 0.006 at 24-40 GHz [22]). Another factor that contributes to an increase in the insertion loss is the roughness of the conductor metals, which, in turn, is strongly dependent on the surface roughness of the PEG substrate or sidewalls of TGV holes in the PEG. In Figure 9, we compared the AFM (atomic force microscope) images of unexposed surfaces for two PEG substrates: one etched to form TGV holes right after the heat development, and the other etched after being polished by CMP. The surface roughness of the PEG directly etched in a 10 wt% HF solution without performing a CMP process was measured to be about 15 times higher than the polished PEG substrate. This increase in surface roughness in the unexposed region is actually observed at the moment when heat development is performed. In addition, we can observe that the sidewalls of the TGV holes etched in HF are very rough compared with the polished top surface, as shown in the SEM (scanning electron microscope) image of Figure 10. In our process, the roughened sidewall of the TGV holes is directly reflected in the thin layers of The measured insertion loss of the fabricated PEG SIW is higher than that of the reported SIWs fabricated on the borosilicate glass [16,21,22]. One main reason for this is the higher dissipation factor (0.016) of PEG, which is an order of magnitude higher than the borosilicate glass (0.0037 at 1 MHz [16,21], 0.006 at 24-40 GHz [22]). Another factor that contributes to an increase in the insertion loss is the roughness of the conductor metals, which, in turn, is strongly dependent on the surface roughness of the PEG substrate or sidewalls of TGV holes in the PEG. In Figure 9, we compared the AFM (atomic force microscope) images of unexposed surfaces for two PEG substrates: one etched to form TGV holes right after the heat development, and the other etched after being polished by CMP. The surface roughness of the PEG directly etched in a 10 wt% HF solution without performing a CMP process was measured to be about 15 times higher than the polished PEG substrate. This increase in surface roughness in the unexposed region is actually observed at the moment when heat development is performed. In addition, we can observe that the sidewalls of the TGV holes etched in HF are very rough compared with the polished top surface, as shown in the SEM (scanning electron microscope) image of Figure 10. In our process, the roughened sidewall of the TGV holes is directly reflected in the thin layers of the sputtered metal, which are used as via conductors instead of filled-up metals.  To confirm the effect of surface roughness on the RF performances, the S-parameters of the two SIWs fabricated on the PEG substrate with or without the CMP process are compared in Figure 11. As shown in the figure, insertion loss at 40 GHz was increased from 2.94 dB to 4.32 dB when the surface of the PEG substrate was not polished by CMP. Therefore, the CMP process prior to the etching of the exposed region needed to be performed, as described in Section 3, to improve insertion losses.  To confirm the effect of surface roughness on the RF performances, the S-parameters of the two SIWs fabricated on the PEG substrate with or without the CMP process are compared in Figure 11. As shown in the figure, insertion loss at 40 GHz was increased from 2.94 dB to 4.32 dB when the surface of the PEG substrate was not polished by CMP. Therefore, the CMP process prior to the etching of the exposed region needed to be performed, as described in Section 3, to improve insertion losses. To confirm the effect of surface roughness on the RF performances, the S-parameters of the two SIWs fabricated on the PEG substrate with or without the CMP process are compared in Figure 11. As shown in the figure, insertion loss at 40 GHz was increased from 2.94 dB to 4.32 dB when the surface of the PEG substrate was not polished by CMP. Therefore, the CMP process prior to the etching of the exposed region needed to be performed, as described in Section 3, to improve insertion losses.
As mentioned before, very few works about microwave applications of PEG are reported, especially in the regime of millimeter-wave frequencies. Since we could not find the SIW realized in the PEG substrates, the performances of our fabricated SIW on the PEG substrate were compared with some other glass-based SIWs, including our previous results, which were mostly manufactured on the borosilicate glass substrates, as presented in Table 3. Due to the higher dielectric loss factor described above, the insertion loss was measured to be somewhat higher than that of the SIWs on the borosilicate glass. In our work, a 10 mm long microstrip line on the PEG substrate showed an insertion loss of 2.49 dB at 40 GHz. In the previous reference, coplanar waveguides (CPWs) and grounded coplanar waveguides (GCPWs) fabricated on the PEG substrate exhibited an insertion loss of 3.3 dB/cm at 60 GHz [14].
Micromachines 2023, 14, x 12 of 15 Figure 11. The measured S-parameter of the fabricated SIWs with and without performing CMP process after heat development.
As mentioned before, very few works about microwave applications of PEG are reported, especially in the regime of millimeter-wave frequencies. Since we could not find the SIW realized in the PEG substrates, the performances of our fabricated SIW on the PEG substrate were compared with some other glass-based SIWs, including our previous results, which were mostly manufactured on the borosilicate glass substrates, as presented in Table 3. Due to the higher dielectric loss factor described above, the insertion loss was measured to be somewhat higher than that of the SIWs on the borosilicate glass. In our work, a 10 mm long microstrip line on the PEG substrate showed an insertion loss of 2.49 dB at 40 GHz. In the previous reference, coplanar waveguides (CPWs) and grounded coplanar waveguides (GCPWs) fabricated on the PEG substrate exhibited an insertion loss of 3.3 dB/cm at 60 GHz [14].  Figure 11. The measured S-parameter of the fabricated SIWs with and without performing CMP process after heat development.

Conclusions
In this study, we proposed a manufacturing method to fabricate SIWs based on the micromachining of photoetchable glass (PEG). Empty TGV holes were fabricated by the UV exposure, heat development and HF etching of PEG, and the sidewalls of the TGV holes were metallized with selective sputtering processes using a silicon shadow mask to connect the top metal and bottom ground plane. By using this process, the wafer-level manufacturing of SIWs in a low-cost glass substrate can be carried out in a relatively simple way without further photolithographic steps or time-consuming via metallization processes. An SIW operating at the Ka-band was designed and fabricated by the developed process. The measured average insertion loss of the SIW was 2.53 ± 0.55 dB with a return loss better than 13.86 dB, from 26.5 to 40 GHz. A microstrip line fabricated on the PEG substrate showed an average insertion loss of 2.26 ± 0.37 dB in the same frequency range. Due to the higher dielectric loss factor of PEG, the fabricated SIW on the PEG substrate tends to show a somewhat higher insertion loss than the SIW on the borosilicate glass. The PEG substrate, however, still has the potential to be applied to millimeter-wave passives or packages for 5G applications because of its simple, wafer-level machineability to fabricate fine-pitched micro TGVs in the glass dielectric material. The process developed in this work could be applied to demonstrate millimeter-wave devices such as SIW-based resonators, filters, 3D inductors and helical antennas, or interposers for integrated packaging where conductive TGVs are required.

Data Availability Statement:
The data presented in this study are available on request from the corresponding author. The data are not publicly available due to privacy restrictions.