Design and Application of Memristive Balanced Ternary Univariate Logic Circuit

This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.


Introduction
In the era of big data, the amount of data is growing explosively, and as a result, digital logic systems are having difficulty in processing such huge amounts of data while striving for ever-increasing efficiency [1].To meet the demand of data processing speed and power efficiency, ternary logic has received recent attention due to its advantages of higher single-line information carrying capacity and additional logical functions [2][3][4][5][6][7].Compared to the binary digital signal, each bit of the ternary digital signal contains more information, resulting in a higher transmission rate at the same frequency.It also helps in reducing circuit interconnections, and digital chips can be made smaller and less expensive [8][9][10].Ternary logic can be divided into two categories: balanced ternary {−1, 0, 1} and unbalanced ternary {0, 1, 2} or {0, −1, −2} [11].Among them, balanced ternary logic has unique advantages, including the ability of having a unified representation for positive and negative numbers without the sign bit, and multiplication operation without generating a carry.Moreover, the symmetry of one-bit addition and multiplication operations can be used for symmetric arithmetic operation circuit design [12,13].
There are two typical paradigms for designing memristor-based ternary logic circuits; one uses three resistance states of the ternary memristor and the other one uses the voltage value as the logic variable, where the former method makes full use of the resistance change characteristics of the memristor, the operation result can be stored in memristors, the logic state will not be lost after power withdrawal.Several studies [21,22] reported on the unbalanced ternary basic logic gate circuit using the three resistance states of the ternary memristor which correspond to positive ternary logic '0', '1', and '2'.A voltagecontrolled tri-valued memristor model was first proposed in Ref. [22], with designs of ternary AND, OR and NOT gate circuits based on it.In this case, three stable resistance states, R H , R M and R L , correspond to logic '0', '1', and '2', respectively.In Ref. [23], a bipolar three-state ZnO memristor was reported, and then all the 27 possible univariate positive ternary logics were realized with a single memristor cell.Furthermore, Ref. [24] proposed a method of realizing a balanced ternary adder using the resistance state transformation of only one single memristor, in which the circuit area and system power consumption were greatly reduced.
Significant advancement has also been achieved in implementing logic circuits using the second method (i.e., employing the voltage value as a logic variable) [25,26].For example, Wang et al. [27] reported the construction of positive ternary logic circuits, including, the ternary AND gate, OR gate, inverters, encoder and decoder circuits.Similarly, in Ref. [28], ternary basic logic gates and combinational logic circuits using memristor-CNTFET hybrid circuit were proposed, whose delay and circuit complexity were lower compared to those of the circuits only using CNTFETs.Ref. [29] proposed a systematic method of constructing a two-digit ternary logic function based on the concept of memristive threshold logic (MTL) and applied this method for constructing basic ternary arithmetic operations.Compared to that of the previously reported relevant circuit design schemes, the circuit area of the ternary adder and ternary multiplier was greatly reduced.In Refs.[5,30], the balanced ternary logic circuits based on a memristor and MOSFET were proposed.The design idea was to construct balanced ternary essential logic gates, such as TAND, TOR, TI, TSUM, NCONS, NANY, etc., and then propose design scheme of a balanced ternary full adder.
As a further development in the present study, combinatorial logic circuits are implemented directly by combining univariate logic circuits and multiplexers.The multiplexer uses the circuit proposed in Ref. [31], and its function is to select only one of the data of multiple channels and transmit it to the output terminal according to the state of the selection signal.The proposed design scheme of a memristive balanced ternary digital logic circuit with the voltage value as the logic variable could be beneficial for further improving information storage, processing, and transmission efficiency.
The structure of this paper is as follows: Section 2 presents a design scheme of a balanced ternary single-variable logic function circuit based on a hybrid design of memristor and MOS transistor; in Section 3, based on the proposed univariate logic circuits and the multiplexer designed in our previous study [31], balanced ternary application-type combinational logic circuits are designed, including a half adder, multiplier, and numerical comparator; Section 4 presents the comparison and analysis of the proposed circuit with existing designs; Section 5 contains the conclusion of this paper.

Balanced Ternary Univariate Logic Circuit
In digital logic circuits, univariate logic functions are used to perform corresponding logic transformations on signals, thus playing an important role in circuit design.For ternary logic, there are three possible values for a single-input variable, with 3 3 = 27 possible output results in total, as shown in Table 1.
As evident from Table 1, balanced ternary univariate logic can be divided into three categories, such as three-state to one-state logic, three-state to two-state logic, and threestate to three-state logic.The first category (three-state to one-state logic: F 1 , F 14 , and F 27 ) is also called constant logic; that is, irrespective of the input value, the output is a fixed logic state, and therefore their applications are limited in circuit design.

Input Output
This paper will mainly involve the circuit design of the other two categories, i.e., the balanced ternary three-state to two-state logic, and the three-state to three-state univariate logic, as well as a detailed analysis and simulation verification of the corresponding circuits.All univariate logic circuits are represented by the circuit symbol shown in Figure 1.

Input Output
As evident from Table 1, balanced ternary univariate logic can be divided into three categories, such as three-state to one-state logic, three-state to two-state logic, and threestate to three-state logic.The first category (three-state to one-state logic: F1, F14, and F27) is also called constant logic; that is, irrespective of the input value, the output is a fixed logic state, and therefore their applications are limited in circuit design.This paper will mainly involve the circuit design of the other two categories, i.e., the balanced ternary three-state to two-state logic, and the three-state to three-state univariate logic, as well as a detailed analysis and simulation verification of the corresponding circuits.All univariate logic circuits are represented by the circuit symbol shown in Figure 1.
Circuit symbol of univariate logistic function Fn.

Three-State to Two-State Logic
From the truth table of the balanced ternary univariate logic function shown in Table 1, there are 18 kinds of univariate logic functions for three-state to two-state logic.Among them, the logics of F19 and F25 correspond to the NTI gate and the PTI gate, respectively, which have been introduced in detail in Ref. [31] and will not be repeated in this section.

Circuit Design of Logic Function F4, F5, F9, F10, F13, F18, F23 and F26
Table 2 shows the designed circuit diagram and the threshold voltage range of the MOS transistor.While the circuits of logic functions F4 and F9 only need one memristor and one NMOS transistor, those of the logic functions F5, F9, F10, F13, F18, F23 and F26 are all composed of two memristors and one NMOS transistor.Among them, two groups of logic (F10 and F13) and (F23 and F26) adopt the same circuit structure, but the difference is that the threshold voltage ranges of MOS transistors in the corresponding circuits are different.See Table 2 for details.

Three-State to Two-State Logic
From the truth table of the balanced ternary univariate logic function shown in Table 1, there are 18 kinds of univariate logic functions for three-state to two-state logic.Among them, the logics of F 19 and F 25 correspond to the NTI gate and the PTI gate, respectively, which have been introduced in detail in Ref. [31] and will not be repeated in this section.
2.1.1.Circuit Design of Logic Function F 4 , F 5 , F 9 , F 10 , F 13 , F 18 , F 23 and F 26 Table 2 shows the designed circuit diagram and the threshold voltage range of the MOS transistor.While the circuits of logic functions F 4 and F 9 only need one memristor and one NMOS transistor, those of the logic functions F 5 , F 9 , F 10 , F 13 , F 18 , F 23 and F 26 are all composed of two memristors and one NMOS transistor.Among them, two groups of logic (F 10 and F 13 ) and (F 23 and F 26 ) adopt the same circuit structure, but the difference is that the threshold voltage ranges of MOS transistors in the corresponding circuits are different.See Table 2 for details.
The working principles of these logic functions can be understood via simply analyzing the circuits of logic functions F 4 and F 5 .For F 4 , when input A is −V DD (logic '−1') or 0V (logic '0'), transistor T 1 is turned off, and the output terminal will be directly connected to the input terminal through memristor M 1 , so the output remains consistent with the input.When input A is V DD (logic '1'), transistor T 1 is turned on, and the output terminal will be directly connected to -V DD through T 1 , that is, logic '-1' is the output.For F 5 , when input A is −V DD (logic '−1') or 0V (logic '0'), transistor T 1 is turned off, the output terminal will pass through memristor M 1 , which is directly connected to the input terminal, and the output is consistent with the input.When input A is V DD (logic '1'), transistor T 1 is turned on, and there is a current path flowing from the input terminal to −V DD in the circuit.Both memristors M 1 and M 2 are switched to the R OFF state, and the output terminal is about 0 V after voltage division, that is, the output logic is '0'.Similar methods can be used to verify the correctness of other circuits, which will not be repeated here.

Logic Function F4 F5 F9
Circuit Structure The working principles of these logic functions can be understood via simply analyzing the circuits of logic functions F4 and F5.For F4, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, and the output terminal will be directly connected to the input terminal through memristor M1, so the output remains consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and the output terminal will be directly connected to -VDD through T1, that is, logic '-1' is the output.For F5, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, the output terminal will pass through memristor M1, which is directly connected to the input terminal, and the output is consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and there is a current path flowing from the input terminal to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, and the output terminal is about 0 V after voltage division, that is, the output logic is '0'.Similar methods can be used to verify the correctness of other circuits, which will not be repeated here.

The Circuit Design of the Remaining Three-State to Two-State Logic Function
The remaining three-state to two-state logic function circuits, including F2, F3, F7, F11, F15, F17, F21, and F24 logic, can be obtained via cascading the circuits as mentioned above.For example, for the F2 logic circuit, it is only necessary to cascade an F4 logic circuit after the F26 logic circuit to complete the logic conversion corresponding to F2.As shown in Table 3, it is a design scheme of a single-variable three-state to two-state logic circuit designed via the cascade method.Among them, 'Fm + Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.

F4 F5 F9
Circuit Structure The working principles of these logic functions can be understood via simply analyzing the circuits of logic functions F4 and F5.For F4, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, and the output terminal will be directly connected to the input terminal through memristor M1, so the output remains consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and the output terminal will be directly connected to -VDD through T1, that is, logic '-1' is the output.For F5, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, the output terminal will pass through memristor M1, which is directly connected to the input terminal, and the output is consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and there is a current path flowing from the input terminal to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, and the output terminal is about 0 V after voltage division, that is, the output logic is '0'.Similar methods can be used to verify the correctness of other circuits, which will not be repeated here.

The Circuit Design of the Remaining Three-State to Two-State Logic Function
The remaining three-state to two-state logic function circuits, including F2, F3, F7, F11, F15, F17, F21, and F24 logic, can be obtained via cascading the circuits as mentioned above.For example, for the F2 logic circuit, it is only necessary to cascade an F4 logic circuit after the F26 logic circuit to complete the logic conversion corresponding to F2.As shown in Table 3, it is a design scheme of a single-variable three-state to two-state logic circuit designed via the cascade method.Among them, 'Fm + Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.

Logic Function F4 F5 F9
Circuit Structure The working principles of these logic functions can be understood via simply analyzing the circuits of logic functions F4 and F5.For F4, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, and the output terminal will be directly connected to the input terminal through memristor M1, so the output remains consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and the output terminal will be directly connected to -VDD through T1, that is, logic '-1' is the output.For F5, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, the output terminal will pass through memristor M1, which is directly connected to the input terminal, and the output is consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and there is a current path flowing from the input terminal to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, and the output terminal is about 0 V after voltage division, that is, the output logic is '0'.Similar methods can be used to verify the correctness of other circuits, which will not be repeated here.

The Circuit Design of the Remaining Three-State to Two-State Logic Function
The remaining three-state to two-state logic function circuits, including F2, F3, F7, F11, F15, F17, F21, and F24 logic, can be obtained via cascading the circuits as mentioned above.For example, for the F2 logic circuit, it is only necessary to cascade an F4 logic circuit after the F26 logic circuit to complete the logic conversion corresponding to F2.As shown in Table 3, it is a design scheme of a single-variable three-state to two-state logic circuit designed via the cascade method.Among them, 'Fm + Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.

Logic Function F4 F5 F9
Circuit Structure The working principles of these logic functions can be understood via simply analyzing the circuits of logic functions F4 and F5.For F4, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, and the output terminal will be directly connected to the input terminal through memristor M1, so the output remains consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and the output terminal will be directly connected to -VDD through T1, that is, logic '-1' is the output.For F5, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, the output terminal will pass through memristor M1, which is directly connected to the input terminal, and the output is consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and there is a current path flowing from the input terminal to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, and the output terminal is about 0 V after voltage division, that is, the output logic is '0'.Similar methods can be used to verify the correctness of other circuits, which will not be repeated here.

The Circuit Design of the Remaining Three-State to Two-State Logic Function
The remaining three-state to two-state logic function circuits, including F2, F3, F7, F11, F15, F17, F21, and F24 logic, can be obtained via cascading the circuits as mentioned above.For example, for the F2 logic circuit, it is only necessary to cascade an F4 logic circuit after the F26 logic circuit to complete the logic conversion corresponding to F2.As shown in Table 3, it is a design scheme of a single-variable three-state to two-state logic circuit designed via the cascade method.Among them, 'Fm + Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.

Logic Function F4 F5 F9
Circuit Structure The working principles of these logic functions can be understood via simply analyzing the circuits of logic functions F4 and F5.For F4, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, and the output terminal will be directly connected to the input terminal through memristor M1, so the output remains consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and the output terminal will be directly connected to -VDD through T1, that is, logic '-1' is the output.For F5, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, the output terminal will pass through memristor M1, which is directly connected to the input terminal, and the output is consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and there is a current path flowing from the input terminal to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, and the output terminal is about 0 V after voltage division, that is, the output logic is '0'.Similar methods can be used to verify the correctness of other circuits, which will not be repeated here.

The Circuit Design of the Remaining Three-State to Two-State Logic Function
The remaining three-state to two-state logic function circuits, including F2, F3, F7, F11, F15, F17, F21, and F24 logic, can be obtained via cascading the circuits as mentioned above.For example, for the F2 logic circuit, it is only necessary to cascade an F4 logic circuit after the F26 logic circuit to complete the logic conversion corresponding to F2.As shown in Table 3, it is a design scheme of a single-variable three-state to two-state logic circuit designed via the cascade method.Among them, 'Fm + Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.

Logic Function F4 F5 F9
Circuit Structure The working principles of these logic functions can be understood via simply analyzing the circuits of logic functions F4 and F5.For F4, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, and the output terminal will be directly connected to the input terminal through memristor M1, so the output remains consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and the output terminal will be directly connected to -VDD through T1, that is, logic '-1' is the output.For F5, when input A is −VDD (logic '−1') or 0V (logic '0'), transistor T1 is turned off, the output terminal will pass through memristor M1, which is directly connected to the input terminal, and the output is consistent with the input.When input A is VDD (logic '1'), transistor T1 is turned on, and there is a current path flowing from the input terminal to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, and the output terminal is about 0 V after voltage division, that is, the output logic is '0'.Similar methods can be used to verify the correctness of other circuits, which will not be repeated here.

The Circuit Design of the Remaining Three-State to Two-State Logic Function
The remaining three-state to two-state logic function circuits, including F2, F3, F7, F11, F15, F17, F21, and F24 logic, can be obtained via cascading the circuits as mentioned above.For example, for the F2 logic circuit, it is only necessary to cascade an F4 logic circuit after the F26 logic circuit to complete the logic conversion corresponding to F2.As shown in Table 3, it is a design scheme of a single-variable three-state to two-state logic circuit designed via the cascade method.Among them, 'Fm + Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.

MOS Transistor Threshold Voltage
The Circuit Design of the Remaining Three-State to Two-State Logic Function The remaining three-state to two-state logic function circuits, including F 2 , F 3 , F 7 , F 11 , F 15 , F 17 , F 21 , and F 24 logic, can be obtained via cascading the circuits as mentioned above.For example, for the F 2 logic circuit, it is only necessary to cascade an F 4 logic circuit after the F 26 logic circuit to complete the logic conversion corresponding to F 2 .As shown in Table 3, it is a design scheme of a single-variable three-state to two-state logic circuit designed via the cascade method.Among them, 'F m + F n ' indicates that the F n logic circuit is cascaded after the F m logic circuit.To validate the above approach, the proposed circuit is simulated and verified using LTSpice.Figures 2-4 show the simulation waveforms of three kinds of three-state to twostate logic, including the transition from the three-state logic circuits to logic (−1,1), (−1,0) and (0,1).ion

Simulation Verification of Three-State to Two-State Logic Circuit
To validate the above approach, the proposed circuit is simulated and verified using LTSpice.Figures 2-4 show the simulation waveforms of three kinds of three-state to twostate logic, including the transition from the three-state logic circuits to logic (−1,1), (−1,0) and (0,1).
Simulation results of transition from three-state logic circuits to logic (−1,1).
Simulation results of transition from three-state logic circuits to logic (−1,0).
Simulation results of transition from three-state logic circuits to logic (0,1).

Three-State to Three-State Logic
There are 6 types of single-variable logic functions in this category, including F6, F8, F12, F16, F20 and F22.Among them, the output of F6 is equal to the input, which is called 'follower logic'.Only five types of three-state to three-state logic are effective and used in

Simulation Verification of Three-State to Two-State Logic Circuit
To validate the above approach, the proposed circuit is simulated and verified using LTSpice.Figures 2-4 show the simulation waveforms of three kinds of three-state to twostate logic, including the transition from the three-state logic circuits to logic (−1,1), (−1,0) and (0,1).
Simulation results of transition from three-state logic circuits to logic (−1,1).
Simulation results of transition from three-state logic circuits to logic (−1,0).

Three-State to Three-State Logic
There are 6 types of single-variable logic functions in this category, including F6, F8, F12, F16, F20 and F22.Among them, the output of F6 is equal to the input, which is called 'follower logic'.Only five types of three-state to three-state logic are effective and used in

Simulation Verification of Three-State to Two-State Logic Circuit
To validate the above approach, the proposed circuit is simulated and verified using LTSpice.Figures 2-4 show the simulation waveforms of three kinds of three-state to twostate logic, including the transition from the three-state logic circuits to logic (−1,1), (−1,0) and (0,1).
Simulation results of transition from three-state logic circuits to logic (−1,1).
Simulation results of transition from three-state logic circuits to logic (−1,0).

Three-State to Three-State Logic
There are 6 types of single-variable logic functions in this category, including F6, F8, F12, F16, F20 and F22.Among them, the output of F6 is equal to the input, which is called 'follower logic'.Only five types of three-state to three-state logic are effective and used in

Three-State to Three-State Logic
There are 6 types of single-variable logic functions in this category, including F 6 , F 8 , F 12 , F 16 , F 20 and F 22 .Among them, the output of F 6 is equal to the input, which is called 'follower logic'.Only five types of three-state to three-state logic are effective and used in circuit design.However, the F 22 logic (STI gate) circuit has been discussed in detail previously [31], and the remaining four logic circuits will be introduced here.The circuit structure diagram of the up-spin logic function, F 16 , the down-spin logic function, F 20 , and the threshold voltage range of the MOS transistor used is shown in Table 4.The F 16 circuit uses two memristors and two NMOS transistors, while the F 20 circuit uses three memristors and three NMOS transistors.In the case of F 20 , when input A is −V DD (logic '−1'), MOS transistors T 1 , T 2 , and T 3 are all turned off, and the output terminal is pulled up to V DD through memristor M 1 , that is, the output logic is '1'.When input A is 0 V (logic '0'), both T 1 and T 2 are turned off, T 3 is turned on, and the output terminal is directly connected to −V DD through T 2 , that is, the output logic is '−1'.When input A is V DD (logic '1'), both T 1 and T 2 are turned on, T 3 is turned off, and there is a current path from V DD to −V DD in the circuit.Both memristors M 1 and M 2 are switched to the R OFF state, and the output terminal outputs a voltage nearly 0V, that is, the output logic is '0'.The correctness of spin-up logic function F 16 can be verified via a similar method, which will not be repeated here.three memristors and three NMOS transistors.In the case of F20, when input A is − (logic '−1'), MOS transistors T1, T2, and T3 are all turned off, and the output termina pulled up to VDD through memristor M1, that is, the output logic is '1'.When input A V (logic '0'), both T1 and T2 are turned off, T3 is turned on, and the output termina directly connected to −VDD through T2, that is, the output logic is '−1'.When input A is (logic '1'), both T1 and T2 are turned on, T3 is turned off, and there is a current path fr VDD to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, the output terminal outputs a voltage nearly 0V, that is, the output logic is '0'.correctness of spin-up logic function F16 can be verified via a similar method, which w not be repeated here.

Logic Function
Up-Spin Logic Function, F16 Down-Spin Logic Function, F20 Circuit Structure

The Circuit Design of the Remaining Three-State to Three-State Logic Function
The remaining three-state to three-state logic function circuits, including F8 and logic, can also be obtained via cascading the circuits mentioned above.For example, the F8 logic circuit, it is only necessary to cascade an F22 logic circuit after the F20 lo circuit to complete logic conversion corresponding to F8.Similarly, the F12 logic circuit be obtained via cascading F16 logic and F22 logic.Table 5 shows the design scheme of univariate three-state to three-state logic circuit using the cascade method.The term 'F Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.Table 5. Design scheme of univariate three-state to three-state logic circuit designed via casc method.

Logic Function
three memristors and three NMOS transistors.In the case of F20, when input A is −VDD (logic '−1'), MOS transistors T1, T2, and T3 are all turned off, and the output terminal is pulled up to VDD through memristor M1, that is, the output logic is '1'.When input A is 0 V (logic '0'), both T1 and T2 are turned off, T3 is turned on, and the output terminal is directly connected to −VDD through T2, that is, the output logic is '−1'.When input A is VDD (logic '1'), both T1 and T2 are turned on, T3 is turned off, and there is a current path from VDD to −VDD in the circuit.Both memristors M1 and M2 are switched to the ROFF state, and the output terminal outputs a voltage nearly 0V, that is, the output logic is '0'.The correctness of spin-up logic function F16 can be verified via a similar method, which will not be repeated here.

Logic Function
Up-Spin Logic Function, F16 Down-Spin Logic Function, F20 Circuit Structure

The Circuit Design of the Remaining Three-State to Three-State Logic Function
The remaining three-state to three-state logic function circuits, including F8 and F12 logic, can also be obtained via cascading the circuits mentioned above.For example, for the F8 logic circuit, it is only necessary to cascade an F22 logic circuit after the F20 logic circuit to complete logic conversion corresponding to F8.Similarly, the F12 logic circuit can be obtained via cascading F16 logic and F22 logic.Table 5 shows the design scheme of the univariate three-state to three-state logic circuit using the cascade method.The term 'Fm + Fn' indicates that the Fn logic circuit is cascaded after the Fm logic circuit.Table 5. Design scheme of univariate three-state to three-state logic circuit designed via cascade method.

The Circuit Design of the Remaining Three-State to Three-State Logic Function
The remaining three-state to three-state logic function circuits, including F 8 and F 12 logic, can also be obtained via cascading the circuits mentioned above.For example, for the F 8 logic circuit, it is only necessary to cascade an F 22 logic circuit after the F 20 logic circuit to complete logic conversion corresponding to F 8 .Similarly, the F 12 logic circuit can be obtained via cascading F 16 logic and F 22 logic.Table 5 shows the design scheme of the univariate three-state to three-state logic circuit using the cascade method.The term 'F m + F n ' indicates that the F n logic circuit is cascaded after the F m logic circuit.The above circuit was simulated in LTSpice, which provides a verification of the design for a given input signal.The simulation waveform diagram of the three-state to three-state logic circuit is shown in Figure 5.

Verification of Three-State to Three-State Logic Circuit Using LTSpice Simulation
The above circuit was simulated in LTSpice, which provides a verification of the design for a given input signal.The simulation waveform diagram of the three-state to three-state logic circuit is shown in Figure 5.

Design of Balanced Three-Valued Combinational Logic Circuit Based on Univariate Logic and Multiplexer
A multiplexer can select one of several input signals to the output.This paper uses the balanced ternary multiplexer circuit proposed in Ref. [31], which can realize the output of one signal from the three inputs.The corresponding input-output relationship is

Design of Balanced Three-Valued Combinational Logic Circuit Based on Univariate Logic and Multiplexer
A multiplexer can select one of several input signals to the output.This paper uses the balanced ternary multiplexer circuit proposed in Ref. [31], which can realize the output of one signal from the three inputs.The corresponding input-output relationship is expressed as follows: Here, S is a selection signal, and I −1 , I 0 , and I 1 are three input signals.The multiplexer is composed of a balanced ternary one-line-one-line decoder, three balanced ternary minimum gates and one balanced ternary maximum gate.The circuit structure diagram is shown in Figure 6.

Design of Balanced Three-Valued Combinational Logic Circuit Based on Univariate Logic and Multiplexer
A multiplexer can select one of several input signals to the output.This paper uses the balanced ternary multiplexer circuit proposed in Ref. [31], which can realize the output of one signal from the three inputs.The corresponding input-output relationship is expressed as follows: Here, S is a selection signal, and I−1, I0, and I1 are three input signals.The multiplexer is composed of a balanced ternary one-line-one-line decoder, three balanced ternary minimum gates and one balanced ternary maximum gate.The circuit structure diagram is shown in Figure 6.When the selection signal is S =−1, the output terminals S−1, S0 and S1 of the one-linethree-line decoder output logic 1, −1 and −1, respectively.According to the working principle of the minimum value gate and the maximum value gate, the output signal of the circuit is equal to input signal I−1, that is, Y = I−1, and the circuit realizes the function of output signal I-1.When the selection signal S = 0, the output terminals S−1, S0 and S1 of the decoder output the logic −1, 1, −1, respectively.In this case, Y = I0, that is, the circuit realizes the function of outputting signal I0.Finally, when the selection signal S = 1 occurs, the output o decoder terminals S−1, S0, and S1 output the logic −1, −1, and 1, respectively, resulting in Y = I1.When the selection signal is S =−1, the output terminals S −1 , S 0 and S 1 of the oneline-three-line decoder output logic 1, −1 and −1, respectively.According to the working principle of the minimum value gate and the maximum value gate, the output signal of the circuit is equal to input signal I −1 , that is, Y = I −1 , and the circuit realizes the function of output signal I -1 .When the selection signal S = 0, the output terminals S −1 , S 0 and S 1 of the decoder output the logic −1, 1, −1, respectively.In this case, Y = I 0 , that is, the circuit realizes the function of outputting signal I 0 .Finally, when the selection signal S = 1 occurs, the output o decoder terminals S −1 , S 0 , and S 1 output the logic −1, −1, and 1, respectively, resulting in Y I 1 .
In this paper, a balanced ternary half adder, a balanced ternary multiplier and a balanced ternary numerical comparator are also designed using the multiplexer and the univariate logic circuit described in Section 2. The truth tables and circuit structures of these applications are summarized in Tables 6 and 7, respectively.The design process and working principle of each circuit are explained in the following three subsections, along with the corresponding simulation results.

Balanced Ternary Half Adder
It can be seen from the truth table that when input signals A = −1 and B selects f the values of {−1, 0, 1}, the 'SUM' outputs the sum of the half adder outputs, corresponding to {1, −1, 0}.According to the working principle of the multiplexer, if A is used as the selection signal, we can obtain the following results.When A = −1, the multiplexer selects the I-1 input terminal for the output, that is, SUM = I-1.And as shown in Table 1 a univariate logic F20 just can fulfill the conversion demanded in the red square in Table 6, so F20 is selected to connect the input B and I-1 in the circuit.Similarly, when input signal A = 0, the sum output of the half adder is SUM = I0 = B, so we directly connect B to I0.When input signal A = 1, SUM = I1, the logic F16 is consistent with the conversion, so F16 is selected to connect the input B and I1 in this case.The 'CARRY' output circuit part is designed in the same way.Figure 7 shows the corresponding logic conversion diagram of the balanced ternary half adder.

Balanced Ternary Half Adder
It can be seen from the truth table that when input signals A = −1 and B selects f the values of {−1, 0, 1}, the 'SUM' outputs the sum of the half adder outputs, corresponding to {1, −1, 0}.According to the working principle of the multiplexer, if A is used as the selection signal, we can obtain the following results.When A = −1, the multiplexer selects the I-1 input terminal for the output, that is, SUM = I-1.And as shown in Table 1 a univariate logic F20 just can fulfill the conversion demanded in the red square in Table 6, so F20 is selected to connect the input B and I-1 in the circuit.Similarly, when input signal A = 0, the sum output of the half adder is SUM = I0 = B, so we directly connect B to I0.When input signal A = 1, SUM = I1, the logic F16 is consistent with the conversion, so F16 is selected to connect the input B and I1 in this case.The 'CARRY' output circuit part is designed in the same way.Figure 7 shows the corresponding logic conversion diagram of the balanced ternary half adder.

Balanced Ternary Half Adder
It can be seen from the truth table that when input signals A = −1 and B selects f the values of {−1, 0, 1}, the 'SUM' outputs the sum of the half adder outputs, corresponding to {1, −1, 0}.According to the working principle of the multiplexer, if A is used as the selection signal, we can obtain the following results.When A = −1, the multiplexer selects the I-1 input terminal for the output, that is, SUM = I-1.And as shown in Table 1 a univariate logic F20 just can fulfill the conversion demanded in the red square in Table 6, so F20 is selected to connect the input B and I-1 in the circuit.Similarly, when input signal A = 0, the sum output of the half adder is SUM = I0 = B, so we directly connect B to I0.When input signal A = 1, SUM = I1, the logic F16 is consistent with the conversion, so F16 is selected to connect the input B and I1 in this case.The 'CARRY' output circuit part is designed in the same way.Figure 7 shows the corresponding logic conversion diagram of the balanced ternary half adder.

Balanced Ternary Half Adder
It can be seen from the truth table that when input signals A = −1 and B selects f the values of {−1, 0, 1}, the 'SUM' outputs the sum of the half adder outputs, corresponding to {1, −1, 0}.According to the working principle of the multiplexer, if A is used as the selection signal, we can obtain the following results.When A = −1, the multiplexer selects the I -1 input terminal for the output, that is, SUM = I -1 .And as shown in Table 1 a univariate logic F 20 just can fulfill the conversion demanded in the red square in Table 6, so F 20 is selected to connect the input B and I -1 in the circuit.Similarly, when input signal A = 0, the sum output of the half adder is SUM = I 0 = B, so we directly connect B to I 0 .When input signal A = 1, SUM = I 1 , the logic F 16 is consistent with the conversion, so F 16 is selected to connect the input B and I 1 in this case.The 'CARRY' output circuit part is designed in the same way.Figure 7 shows the corresponding logic conversion diagram of the balanced ternary half adder.
Micromachines 2023, 14, 1895 9 of 13 According to the univariate logic function relationship in Table 1, for the 'sum' output part, the three logic conversion relationships correspond to the down-spin logic function, F20, the follow-up logic function, F6, and the up-spin logic function, F16.For the 'carry' output part, the three logical conversion relationships correspond to the logical functions F5, F14, and F15.Therefore, it is only necessary to introduce the corresponding univariate logic circuit into circuit design.The LTSpice simulation waveform diagram is given in Figure 8.According to the univariate logic function relationship in Table 1, for the 'sum' output part, the three logic conversion relationships correspond to the down-spin logic function, F 20 , the follow-up logic function, F 6 , and the up-spin logic function, F 16 .For the 'carry' output part, the three logical conversion relationships correspond to the logical functions F 5 , F 14 , and F 15 .Therefore, it is only necessary to introduce the corresponding univariate logic circuit into circuit design.The LTSpice simulation waveform diagram is given in Figure 8.
According to the univariate logic function relationship in Table 1, for the 'sum' output part, the three logic conversion relationships correspond to the down-spin logic function, F20, the follow-up logic function, F6, and the up-spin logic function, F16.For the 'carry' output part, the three logical conversion relationships correspond to the logical functions F5, F14, and F15.Therefore, it is only necessary to introduce the corresponding univariate logic circuit into circuit design.The LTSpice simulation waveform diagram is given in Figure 8.

Balanced Ternary Multiplier
Balanced ternary does not generate carry during multiplication, so it has certain advantages over the unbalanced ternary logic.The multiplier circuits design is as follows: When A = −1, the multiplexer selects the I-1 input terminal for the output, According to Tables 1 and 6, F22 can be selected to connect the input B and I-1 in the circuit.When A = 0, the I0 terminal of the multiplexer is gated, and now the output terminal outputs a logic '0', so we can directly connect I0 to the ground.When A = 1, the logic value of the output terminal is consistent with the input signal B, so we connect input signal B to the I1 terminal of the multiplexer in this case.Figure 9 shows the LTSpice simulation waveform diagram of the circuit.

Balanced Ternary Multiplier
Balanced ternary does not generate carry during multiplication, so it has certain advantages over the unbalanced ternary logic.The multiplier circuits design is as follows: When A = −1, the multiplexer selects the I -1 input terminal for the output, According to Tables 1 and 6, F 22 can be selected to connect the input B and I -1 in the circuit.When A = 0, the I 0 terminal of the multiplexer is gated, and now the output terminal outputs a logic '0', so we can directly connect I 0 to the ground.When A = 1, the logic value of the output terminal is consistent with the input signal B, so we connect input signal B to the I 1 terminal of the multiplexer in this case.Figure 9 shows the LTSpice simulation waveform diagram of the circuit.

Balanced Ternary Numerical Comparator
As we known, the output of multiplexer equals to I-1 when the input signal A is selected as −1, that is, MLE = I-1.And according to the truth Tables 1 and 6, logic F10 performs the some function when input A = −1.so F10 is selected to connect the input B and I-1 in the circuit.Similarly, logics F22 and F26 are chosen to perform the corresponding functions when input A = 0 and A = 1. Figure 10 shows the simulation results for a balanced ternary numerical comparator.

Comparison and Analysis
The number of components using the proposed method are given in Table 8 and are compared with that reported earlier [31].It is evident that there are significant advantages of the proposed method in terms of the balanced ternary half adder, multiplier, and numerical comparator circuit as the number of circuit components is reduced by 37.8%, 39.5%, and 48.2%, respectively.

Balanced Ternary Numerical Comparator
As we known, the output of multiplexer equals to I -1 when the input signal A is selected as −1, that is, MLE = I -1 .And according to the truth Tables 1 and 6, logic F 10 performs the some function when input A = −1.so F 10 is selected to connect the input B and I -1 in the circuit.Similarly, logics F 22 and F 26 are chosen to perform the corresponding functions when input A = 0 and A = 1. Figure 10 shows the simulation results for a balanced ternary numerical comparator.

Balanced Ternary Numerical Comparator
As we known, the output of multiplexer equals to I-1 when the input signal A is selected as −1, that is, MLE = I-1.And according to the truth Tables 1 and 6, logic F10 performs the some function when input A = −1.so F10 is selected to connect the input B and I-1 in the circuit.Similarly, logics F22 and F26 are chosen to perform the corresponding functions when input A = 0 and A = 1. Figure 10 shows the simulation results for a balanced ternary numerical comparator.

Comparison and Analysis
The number of components using the proposed method are given in Table 8 and are compared with that reported earlier [31].It is evident that there are significant advantages of the proposed method in terms of the balanced ternary half adder, multiplier, and circuit was compared with other design methods.Our results show that the number of components can be significantly reduced using the proposed design method, which could further reduce the complexity of the circuit.

Figure 1 .
Figure 1. Circuit symbol of univariate logistic function F n.

F
16 and Down-Spin Logic Function F 20

1 Figure 5 .
Figure 5. Simulation waveform diagram of three-state to three-state univariate logic circuit.

Figure 5 .
Figure 5. Simulation waveform diagram of three-state to three-state univariate logic circuit.

Figure 5 .
Figure 5. Simulation waveform diagram of three-state to three-state univariate logic circuit.

Figure 7 .
Figure 7.The corresponding logic conversion diagram of the balanced ternary half adder.(a) 'sum' output part; (b) 'carry' output part.

Figure 7 .
Figure 7.The corresponding logic conversion diagram of the balanced ternary half adder.(a) 'sum' output part; (b) 'carry' output part.

Table 1 .
Balanced ternary univariate logic function truth table.

Table 1 .
Balanced ternary univariate logic function truth table.

Table 2 .
Structure diagram of three-state to two-state logic circuit and threshold voltage of MOS transistor.

Table 2 .
Structure diagram of three-state to two-state logic circuit and threshold voltage of MOS transistor.

Table 2 .
Structure diagram of three-state to two-state logic circuit and threshold voltage of MOS transistor.

Table 2 .
Structure diagram of three-state to two-state logic circuit and threshold voltage of MOS transistor.

Table 2 .
Structure diagram of three-state to two-state logic circuit and threshold voltage of MOS transistor.

Table 2 .
Structure diagram of three-state to two-state logic circuit and threshold voltage of MOS transistor.

Table 2 .
Structure diagram of three-state to two-state logic circuit and threshold voltage of MOS transistor.

Table 3 .
The scheme of univariate three-state to two-state logic circuit designed via the cascade method.

Table 4 .
Circuit structure diagram of up-spin logic function, down-spin logic function and threshold voltage of MOS transistor.

Table 4 .
Circuit structure diagram of up-spin logic function, down-spin logic function and thresh voltage of MOS transistor.

Table 4 .
Circuit structure diagram of up-spin logic function, down-spin logic function and threshold voltage of MOS transistor.

Table 5 .
Design scheme of univariate three-state to three-state logic circuit designed via cascade method.

Table 6 .
Truth table of balanced ternary half adder, balanced ternary multiplier, and balanced ternary numerical comparator.

Table 7 .
Circuit structure of each application.

Table 7 .
Circuit structure of each application.

Table 7 .
Circuit structure of each application.

Table 7 .
Circuit structure of each application.