Analysis of SiC/Si Heterojunction Band Energy and Interface State Characteristics for SiC/Si VDMOS

SiC/Si and GaN/Si heterojunction technology has been widely used in power semiconductor devices, and SiC/Si VDMOS and GaN/Si VDMOS were proposed in our previous paper. Based on existing research, breakdown point transfer technology (BPT) was used to optimize SiC/Si VDMOS. Simulation results showed that the BV of the SiC/Si heterojunction VDMOS was considerably increased from 259 V to 1144 V, and Ron,sp decreased from 18.2 mΩ·cm2 to 6.03 mΩ·cm2 compared with Si VDMOS. In order to analyze the characteristics of the SiC/Si heterojunction structure deeply, the influence of the interface state characteristics of the SiC/Si heterojunction on the electrical parameters of VDMOS was analyzed, including electric field characteristics, blocking characteristics, output characteristics, and transfer characteristics. In addition, the influence of the interface state of the SiC/Si heterojunction on energy band characteristics was analyzed. The results showed that with an increase in the interfacial charge (acceptor) concentration, the p-type trap layer was introduced into the interface of the SiC/Si heterojunction, energy increased slightly, and the barrier height difference at the heterojunction increased, resulting in an increase in BV. At the same time, since the barrier height became higher, electrons did not flow easily, so Ron,sp increased. On the contrary, when a charge (donor) was introduced at the interface of the SiC/Si heterojunction, the number of electrons in the channel increased, resulting in an increase in the electron current, which is conducive to the flow of electrons, resulting in a decrease in Ron,sp. The energy band and other characteristics of devices with temperature were simulated at different temperatures. Finally, the effects of SiC/Si heterojunction interface states on interface capacitances and switching performances of VDMOS devices were also discussed.

However, efforts to improve Si power devices are always limited by the low critical electric field of Si, which gives an opportunity for the development of SiC devices.SiC materials have a large bandgap and a critical electric field about 10 times that of Si, which can break the limit of Si materials .Nevertheless, SiC power devices suffer from gate oxide reliability and some difficulties in manufacturing processes, such as the diffusion of impurity and the realization of high-quality ohm contact [16,17].Moreover, manufacturing SiC devices is much more costly compared with Si devices.The successful fabrication of SiC/Si substrates offers a practical approach to solving these problems [18][19][20][21][22].
A SiC/Si heterojunction VDMOS combines the mature process of Si materials with the wide bandgap of SiC materials.Thus, a high critical breakdown electric field can optimize BV compared with a traditional Si-based power device [16,17].The contradiction between BV and R on,sp is optimized, and the high thermal conductivity of SiC materials is beneficial to the heat dissipation of a VDMOS device, which effectively improves the performance of the device.Since the active region of the device is formed from silicon semiconductor material, a mature silicon process can be employed in the device fabrication process to achieve better ohmic contact [16][17][18][19][20][21][22][23][24][25].SiC/Si VDMOS and GaN/Si VDMOS were proposed in our previous paper, and the influence of device electrical and structural parameters was studied [16,18].However, this paper mainly discusses the influence of the interface state on the electric field, band energy distribution, temperature, and switching characteristics.

Materials and Methods
In this paper, a VDMOS with SiC/Si heterojunction was used to optimize BV by breakdown point transfer (BPT), which transfers the breakdown point from a high electric field to a low electric field.Figure 1 shows a cell of the proposed SiC/Si heterojunction VDMOS; the formation of the Si/SiC substrate can be realized by the method in [22]."D Si " is defined as the Si thickness, "L D " is the length of N − drift region, and "N D " is the concentration of N − drift region in the structures.
Micromachines 2023, 14, x FOR PEER REVIEW 2 of 13 sion of impurity and the realization of high-quality ohm contact [16,17].Moreover, manufacturing SiC devices is much more costly compared with Si devices.The successful fabrication of SiC/Si substrates offers a practical approach to solving these problems [18][19][20][21][22].A SiC/Si heterojunction VDMOS combines the mature process of Si materials with the wide bandgap of SiC materials.Thus, a high critical breakdown electric field can optimize BV compared with a traditional Si-based power device [16,17].The contradiction between BV and Ron,sp is optimized, and the high thermal conductivity of SiC materials is beneficial to the heat dissipation of a VDMOS device, which effectively improves the performance of the device.Since the active region of the device is formed from silicon semiconductor material, a mature silicon process can be employed in the device fabrication process to achieve better ohmic contact [16][17][18][19][20][21][22][23][24][25].SiC/Si VDMOS and GaN/Si VDMOS were proposed in our previous paper, and the influence of device electrical and structural parameters was studied [16,18].However, this paper mainly discusses the influence of the interface state on the electric field, band energy distribution, temperature, and switching characteristics.

Materials and Methods
In this paper, a VDMOS with SiC/Si heterojunction was used to optimize BV by breakdown point transfer (BPT), which transfers the breakdown point from a high electric field to a low electric field.Figure 1 shows a cell of the proposed SiC/Si heterojunction VDMOS; the formation of the Si/SiC substrate can be realized by the method in [22]."DSi" is defined as the Si thickness, "LD" is the length of N − drift region, and "ND" is the concentration of N − drift region in the structures.In this paper, a two-dimensional numerical simulation of SiC/Si VDMOS is performed using ISE-TCAD.The main physics models were applied in Synopsys Sentau-rusTM tools simulation, including Mobility (DopingDep High Field Sat Enormal), Effec-tiveIntrinsic Density (OldSlotboom), and Recombination (SRH (DopingDep) and Auger Avalanche (Eparal)).The criterion of breakdown was BreakCriteria {Current (Contact = "drain" Absval = 1 × 10 −7 )}.The main solving model was Coupled {Poisson Electron Hole}.For the coordinates, it was necessary to optimize the parameters in the numerical simulations.Some of the device parameters in the simulation are presented in Table 1.The ambient temperature was 300 K, the breakdown voltage (BV) was obtained at VGS = 0 V, and the specific on-resistance (Ron,sp) was obtained at VGS = 10 V; the simulation results of the four devices are shown in Table 2.In this paper, a two-dimensional numerical simulation of SiC/Si VDMOS is performed using ISE-TCAD.The main physics models were applied in Synopsys SentaurusTM tools simulation, including Mobility (DopingDep High Field Sat Enormal), EffectiveIntrinsic Density (OldSlotboom), and Recombination (SRH (DopingDep) and Auger Avalanche (Eparal)).The criterion of breakdown was BreakCriteria {Current (Contact = "drain" Absval = 1 × 10 −7 )}.The main solving model was Coupled {Poisson Electron Hole}.For the coordinates, it was necessary to optimize the parameters in the numerical simulations.Some of the device parameters in the simulation are presented in Table 1.The ambient temperature was 300 K, the breakdown voltage (BV) was obtained at V GS = 0 V, and the specific on-resistance (R on,sp ) was obtained at V GS = 10 V; the simulation results of the four devices are shown in Table 2.

The Influence of Interface State on Electrical Parameters
The vertical electric field for SiC/Si VDMOS, Si VDMOS, and SiC VDMOS are shown in Figure 2a.For SiC VDMOS, BV reached 1747V.For Si VDMOS, when X = 2.5 µm (shown in Figure 1), the maximum field strength was 3.03 × 10 5 V/cm (reaching the critical breakdown electric field of Si materials), and BV was 259 V of Si VDMOS.For SiC/Si VDMOS, when the drain voltage reached 259 V, the electric field strength at the interface between the P-base and the N-type drift regions did not reach the critical breakdown field strength of SiC, so the device did not break down.As the drain voltage was further increased, the electric field strength of the device increased until the electric field at the heterojunction reached 3.45 × 10 5 V/cm (reaching the critical breakdown field of the Si materials), and the SiC/Si VDMOS broke down.Therefore, the BV of SiC/Si VDMOS was increased from 259 V to 1144 V compared with the conventional Si VDMOS [16,17].According to previous experimental results [23,24], SiC/Si interfacial charges were introduced during the direct bonding process.The effect of different interface state charge concentrations on the vertical electric field of SiC/Si VDMOS is shown in Figure 2b.The type of interface state charge introduced was donor (electron) or acceptor (hole) in this paper.An increase in the interface state charge (acceptorlike) concentrations resulted in an increase in the vertical electric field of the SiC/Si VDMOS compared with SiC/Si VDMOS without an interface state charge.This is because of the p-type trap layer introduced by the interface charge (acceptor) at the SiC/Si heterojunction, which enhanced the internal electric field at the SiC/Si interface and changed the distribution of the electric field.As the interface state charge (donor) concentration increased, the vertical electric field at the SiC/Si heterojunction decreased.
The optimized blocking characteristics and output characteristics for the SiC/Si VD-MOS are provided in Figure 3a,b.As can be seen, BV was 1144 V, and R on,sp was 6.03 mΩ•cm 2 for the SiC/Si VDMOS without an interface state charge.The BV of the SiC/Si VDMOS increased from 1182 V to 1507 V with increasing interface state charges (acceptorlike) concentrations.This is because the vertical electric field of SiC/Si VDMOS increased by SiC/Si heterojunction, which the p-type trap layer introduced by the interface charge (acceptor) at the SiC/Si heterojunction, resulting in R on,sp increasing to 28 mΩ•cm 2 .However, the internal electron barrier was induced in the inversion layer at the SiC/Si interface, and the number of electrons in the channel increased, resulting in an increase in the electron current.This resulted in R on,sp dropping from 6.03 mΩ•cm 2 to 5.80 mΩ•cm 2 , and BV decreased to 748 V at this time.The transfer characteristics for the SiC/Si VDMOS are shown in Figure 3c.It is reported that the charge at the SiC/Si interface had an influence on the I-V characteristics of the SiC/Si VDMOS.That is, when the interface charge donor (electron) concentration increased, the threshold voltage (V TH ) of SiC/Si VDMOS increased from 4.82 V to 5.08 V.When the interface charge was considered an acceptor (hole), the V TH of the SiC/Si VD-MOS decreased from 4.75 V to 4.51 V as the interface charge concentration increased from 1 × 10 5 /cm 2 to 5 × 10 5 /cm 2 .The optimized blocking characteristics and output characteristics for the SiC/Si VDMOS are provided in Figure 3a,b.As can be seen, BV was 1144 V, and Ron,sp was 6.03 mΩ•cm 2 for the SiC/Si VDMOS without an interface state charge.The BV of the SiC/Si VDMOS increased from 1182 V to 1507 V with increasing interface state charges (acceptorlike) concentrations.This is because the vertical electric field of SiC/Si VDMOS increased by SiC/Si heterojunction, which the p-type trap layer introduced by the interface charge (acceptor) at the SiC/Si heterojunction, resulting in Ron,sp increasing to 28 mΩ•cm 2 .However, the internal electron barrier was induced in the inversion layer at the SiC/Si interface, and the number of electrons in the channel increased, resulting in an increase in the electron current.This resulted in Ron,sp dropping from 6.03 mΩ•cm 2 to 5.80 mΩ•cm 2 , and BV decreased to 748 V at this time.The transfer characteristics for the SiC/Si VDMOS are shown in Figure 3c.It is reported that the charge at the SiC/Si interface had an influence on the I-V characteristics of the SiC/Si VDMOS.That is, when the interface charge donor (electron) concentration increased, the threshold voltage (VTH) of SiC/Si VDMOS increased from 4.82 V to 5.08 V.When the interface charge was considered an acceptor (hole), the VTH of the SiC/Si VDMOS decreased from 4.75 V to 4.51 V as the interface charge concentration increased from 1 × 10 5 /cm 2 to 5 × 10 5 /cm 2 .

The Influence of Interface State on Band Energy Distributions
Figure 4 shows the energy bands of SiC/Si VDMOS, Si VDMOS, and SiC VDMOS during thermal equilibrium.It can be seen that for Si VDMOS, the bandgap was 1.12 eV, and the curve X = 2.5 µm was the focus of the Si VDMOS breakdown voltage (shown in

The Influence of Interface State on Band Energy Distributions
Figure 4 shows the energy bands of SiC/Si VDMOS, Si VDMOS, and SiC VDMOS during thermal equilibrium.It can be seen that for Si VDMOS, the bandgap was 1.12 eV, and the curve X = 2.5 µm was the focus of the Si VDMOS breakdown voltage (shown in Figure 1), which means that the breakdown point was located at the junction of the P-based and N-type drift regions, the site of the maximum radius of curvature of conventional Si VDMOS.Since the band gap of SiC VDMOS was 3.26 eV, curve X = 4.9 µm was the focal point of the SiC VDMOS breakdown voltage, and the BV of the device reached 1747 V.The curve X = 4.9 µm was the focus of the breakdown voltage for SiC/Si VDMOS with SiC/Si heterojunction (shown in Figure 1).Due to the high critical breakdown field strength of SiC materials, BV increased from 259 V to 1144 V compared with Si VDMOS.

The Influence of Interface State on Band Energy Distributions
Figure 4 shows the energy bands of SiC/Si VDMOS, Si VDMOS, and SiC VDMOS during thermal equilibrium.It can be seen that for Si VDMOS, the bandgap was 1.12 eV, and the curve X = 2.5 µm was the focus of the Si VDMOS breakdown voltage (shown in Figure 1), which means that the breakdown point was located at the junction of the Pbased and N-type drift regions, the site of the maximum radius of curvature of conventional Si VDMOS.Since the band gap of SiC VDMOS was 3.26 eV, curve X = 4.9 µm was the focal point of the SiC VDMOS breakdown voltage, and the BV of the device reached 1747 V.The curve X = 4.9 µm was the focus of the breakdown voltage for SiC/Si VDMOS with SiC/Si heterojunction (shown in Figure 1).Due to the high critical breakdown field strength of SiC materials, BV increased from 259 V to 1144 V compared with Si VDMOS.The energy band diagram of SiC/Si VDMOS with different interface state charges (acceptorlike) is shown in Figure 6a.In this figure, as the interface concentration increases, the energy at the SiC/Si heterojunction rises slightly due to the p-type trap layer introduced by the interface charge (acceptor) at the SiC/Si heterojunction interface.This results in an increase in the barrier height difference at the heterojunction, resulting in an increase in the BV of SiC/Si VDMOS (shown in Figure 3a).Further, since the height of the barrier The energy band diagram of SiC/Si VDMOS with different interface state charges (acceptorlike) is shown in Figure 6a.In this figure, as the interface concentration increases, the energy at the SiC/Si heterojunction rises slightly due to the p-type trap layer introduced by the interface charge (acceptor) at the SiC/Si heterojunction interface.This results in an increase in the barrier height difference at the heterojunction, resulting in an increase in the BV of SiC/Si VDMOS (shown in Figure 3a).Further, since the height of the barrier becomes high, electrons do not easily flow, and thus, R on,sp increases (shown in Figure 3b).Figure 6b shows the influence of different interface state charges (donors) on the energy band diagram of SiC/Si VDMOS.Electrons were induced in the inversion layer at the SiC/Si heterojunction interface.As the interface concentration increased, the number of electrons in the channel increased, resulting in an increase in the electron current.The decrease in the barrier height resulted in a decrease in the BV of SiC/Si VDMOS, which facilitated electron flow and caused a decrease in R on,sp (shown in Figure 3a,b).

The Influence of Interface State on Temperature Effects
Figure 7a shows the vertical electric field distributions for SiC/Si VDMOS at the temperature range of 300 K to 360 K.It can be seen that the highest electric field of the SiC/Si VDMOS reached 9.8 MV/cm, and BV was 1144 V at 300 K [25][26][27][28][29].When the temperature was increased to 360 K, the maximum electric field of the SiC/Si VDMOS dropped to 8.8 MV/cm, and BV dropped to 1000 V.The dependences of BV, Ron,sp, and figure-of-merit (FOM = BV 2 /Ron,sp) changes from 300 K to 360 K for the SiC/Si VDMOS are shown in Figure 7b.It was found that the BV of SiC/Si VDMOS decreased from 1144 V to 1000 V as the temperature increased.In addition, the Ron,sp of SiC/Si VDMOS increased, yielding a FOM (217 MW/cm 2 ) of SiC/Si VDMOS that dropped to 48 MW/cm 2 .

The Influence of Interface State on Temperature Effects
Figure 7a shows the vertical electric field distributions for SiC/Si VDMOS at the temperature range of 300 K to 360 K.It can be seen that the highest electric field of the SiC/Si VDMOS reached 9.8 MV/cm, and BV was 1144 V at 300 K [25][26][27][28][29].When the temperature was increased to 360 K, the maximum electric field of the SiC/Si VDMOS dropped to 8.8 MV/cm, and BV dropped to 1000 V.The dependences of BV, R on,sp , and figure-of-merit (FOM = BV 2 /R on,sp ) changes from 300 K to 360 K for the SiC/Si VDMOS are shown in Figure 7b.It was found that the BV of SiC/Si VDMOS decreased from 1144 V to 1000 V as the temperature increased.In addition, the R on,sp of SiC/Si VDMOS increased, yielding a FOM (217 MW/cm 2 ) of SiC/Si VDMOS that dropped to 48 MW/cm 2 .
Figure 8a shows the band diagram of the P-Si/N−SiC heterojunction at a temperature range of 300 K to 360 K.The barrier height difference decreased when the temperature rose and BV decreased.At the same time, the resistivity and impurity ionization rate of the drift region increased as the temperature increased [37].Transfer characteristics changes from 300 K to 360 K for the SiC/Si VDMOS are shown in Figure 8b.At 300 K, V TH was 4.37 V for SiC/Si VDMOS.As the temperature increased, the barrier height difference decreased, resulting in a decrease in the V TH of SiC/Si VDMOS.When the temperature reached 360 K, the V TH of the SiC/Si VDMOS was reduced to 3.68 V.
VDMOS reached 9.8 MV/cm, and BV was 1144 V at 300 K [25][26][27][28][29].When the temperature was increased to 360 K, the maximum electric field of the SiC/Si VDMOS dropped to 8.8 MV/cm, and BV dropped to 1000 V.The dependences of BV, Ron,sp, and figure-of-merit (FOM = BV 2 /Ron,sp) changes from 300 K to 360 K for the SiC/Si VDMOS are shown in Figure 7b.It was found that the BV of SiC/Si VDMOS decreased from 1144 V to 1000 V as the temperature increased.In addition, the Ron,sp of SiC/Si VDMOS increased, yielding a FOM (217 MW/cm 2 ) of SiC/Si VDMOS that dropped to 48 MW/cm 2 .Figure 8a shows the band diagram of the P-Si/N−SiC heterojunction at a temperature range of 300 K to 360 K.The barrier height difference decreased when the temperature rose and BV decreased.At the same time, the resistivity and impurity ionization rate of the drift region increased as the temperature increased [37].Transfer characteristics changes from 300 K to 360 K for the SiC/Si VDMOS are shown in Figure 8b.At 300 K, VTH

The Influence of Interface State on Interface Capacitances and Switching Performances
Figure 9 shows the reverse transfer capacitances (Crss) of SiC/Si VDMOS, Si VDMOS, and SiC VDMOS.Crss is especially important when VDMOS devices are used for power supplies due to the switching loss of the device being seriously affected.The expression for Crss is: As shown in Figure 9, the Crss of SiC/Si VDMOS was smaller than that of conventional Si VDMOS and SiC VDMOS.A new capacitor was introduced at the interface where the SiC/Si heterojunction was introduced, thereby reducing the depletion capacitance of the SiC/Si VDMOS.

The Influence of Interface State on Interface Capacitances and Switching Performances
Figure 9 shows the reverse transfer capacitances (C rss ) of SiC/Si VDMOS, Si VDMOS, and SiC VDMOS.C rss is especially important when VDMOS devices are used for power supplies due to the switching loss of the device being seriously affected.The expression for C rss is: As shown in Figure 9, the C rss of SiC/Si VDMOS was smaller than that of conventional Si VDMOS and SiC VDMOS.A new capacitor was introduced at the interface where the SiC/Si heterojunction was introduced, thereby reducing the depletion capacitance of the SiC/Si VDMOS.
Figure 10a shows the influence of different interface state charges (acceptorlike) on the reverse transfer capacitances (C rss ) for SiC/Si VDMOS.When the acceptor (hole) interface charge was considered, an opposite type of negative charge was induced at the channel of e SiC/Si VDMOS.This increased the depletion charge of the device, causing the C rss of SiC/Si VDMOSFET to increase as the interface concentration increased.The C rss of SiC/Si VDMOS with different interface state charges (donor) is shown in Figure 10b.A positive charge induced at the channel of the SiC/Si VDMOS reduced the depletion charge of SiC/Si VDMOS due to the interface charge donor (electron) being introduced at the SiC/Si interface.Therefore, as the concentration increased, the C rss of SiC/Si VDMOS decreased.and SiC VDMOS.Crss is especially important when VDMOS devices are used for power supplies due to the switching loss of the device being seriously affected.The expression for Crss is: As shown in Figure 9, the Crss of SiC/Si VDMOS was smaller than that of conventional Si VDMOS and SiC VDMOS.A new capacitor was introduced at the interface where the SiC/Si heterojunction was introduced, thereby reducing the depletion capacitance of the SiC/Si VDMOS. Figure 10a shows the influence of different interface state charges (acceptorlike) on the reverse transfer capacitances (Crss) for SiC/Si VDMOS.When the acceptor (hole) interface charge was considered, an opposite type of negative charge was induced at the channel of e SiC/Si VDMOS.This increased the depletion charge of the device, causing the Crss Figure 11a shows the dynamic performance of the three devices under resistive load.It can be seen that the turn-OFF speed of SiC VDMOS was lower than that of SiC/Si VDMOS and Si VDMOS.The dynamic characteristics of the proposed device were more suitable for low and medium frequencies in the power field, while the turn-ON speed for the two devices was almost the same.Figure 11b shows the influence of different interface state charges on the switching characteristics for SiC/Si VDMOS.A positive charge was induced at the channel of the SiC/Si VDMOS due to the interface charge donor (electron) being introduced.This reduced the depletion charge of the device, resulting in a faster turn-OFF speed of SiC/Si VDMOS.When the acceptor (hole) interface charge was considered, the depletion charge of the device increased.This resulted in a slower turn-OFF of SiC/Si VDMOS, while the turn-ON speed for the three cases was almost the same.The dynamic characteristics of the SiC/Si VDMOS were more suitable for low and medium frequencies in the power field.Figure 11a shows the dynamic performance of the three devices under resistive load.It can be seen that the turn-OFF speed of SiC VDMOS was lower than that of SiC/Si VDMOS and Si VDMOS.The dynamic characteristics of the proposed device were more suitable for low and medium frequencies in the power field, while the turn-ON speed for the two devices was almost the same.Figure 11b shows the influence of different interface state charges on the switching characteristics for SiC/Si VDMOS.A positive charge was induced at the channel of the SiC/Si VDMOS due to the interface charge donor (electron) being introduced.This reduced the depletion charge of the device, resulting in a faster turn-OFF speed of SiC/Si VDMOS.When the acceptor (hole) interface charge was considered, the depletion charge of the device increased.This resulted in a slower turn-OFF of SiC/Si VDMOS, while the turn-ON speed for the three cases was almost the same.The dynamic characteristics of the SiC/Si VDMOS were more suitable for low and medium frequencies in the power field.
The key processes for the feasibility of manufacturing SiC/Si VDMOS are shown in Figure 12, and some key processes are similar to Si VDMOS.The formation of the SiC/Si drift region can be achieved by the method in Ref. [22].The simplified wafer bonding process is as follows: (a) ion implantation forms a P-well in the N-SiC drift region; (b) ion implantation to form source region; (c) epitaxial growth of N-Si Layer; (d) wafer bonding is carried out and ion implantation is made to form the portion of the P-well in the N-Si layer; (e) ion implantation to form the portion of the source in the N-Si layer; and (f) the gate oxide layer grows, the field oxide layer grows, and then the source electrode and the drain electrode are contacted.
Figure 11a shows the dynamic performance of the three devices under resistive load.It can be seen that the turn-OFF speed of SiC VDMOS was lower than that of SiC/Si VDMOS and Si VDMOS.The dynamic characteristics of the proposed device were more suitable for low and medium frequencies in the power field, while the turn-ON speed for the two devices was almost the same.Figure 11b shows the influence of different interface state charges on the switching characteristics for SiC/Si VDMOS.A positive charge was induced at the channel of the SiC/Si VDMOS due to the interface charge donor (electron) being introduced.This reduced the depletion charge of the device, resulting in a faster turn-OFF speed of SiC/Si VDMOS.When the acceptor (hole) interface charge was considered, the depletion charge of the device increased.This resulted in a slower turn-OFF of SiC/Si VDMOS, while the turn-ON speed for the three cases was almost the same.The dynamic characteristics of the SiC/Si VDMOS were more suitable for low and medium frequencies in the power field.The key processes for the feasibility of manufacturing SiC/Si VDMOS are shown in Figure 12, and some key processes are similar to Si VDMOS.The formation of the SiC/Si drift region can be achieved by the method in Ref. [22].The simplified wafer bonding process is as follows:

Conclusions
SiC/Si VDMOS and GaN/Si VDMOS were proposed in our previous paper; however, only the electrical and structural parameters of the device were studied.In the present

Figure 3 .
Figure 3. (a) Blocking characteristics, (b) output characteristics, and (c) transfer characteristics for SiC/Si VDMOS with the different concentrations of interface state charge.

Figure 3 .
Figure 3. (a) Blocking characteristics, (b) output characteristics, and (c) transfer characteristics for SiC/Si VDMOS with the different concentrations of interface state charge.

Figure 4 .
Figure 4.The energy band diagram at thermal equilibrium for SiC/Si VDMOS, Si VDMOS, and SiC VDMOS.

Figure 5
Figure5shows the band diagram of N − -Si/N-SiC in the middle of mesa (AA'), the P-Si/N-SiC heterojunction (BB'), the P-Si/P-SiC heterojunction (CC'), and the N + -Si/P-SiC heterojunction (DD').To analyze the band state of the SiC/Si VDMOS heterojunction, four tangents in the y direction (AA', BB', CC', and DD') were chosen.We can see that the SiC/Si VDMOS heterojunction is affected not only by the two materials Si and SiC with different bandgaps but also by the doping concentration and different doping types at different regions of the device, which change the heterojunction bandgap of SiC/Si VDMOS.

Figure 4 .
Figure 4.The energy band diagram at thermal equilibrium for SiC/Si VDMOS, Si VDMOS, and SiC VDMOS.

Figure 5 Figure 5 .
Figure5shows the band diagram of N − -Si/N-SiC in the middle of mesa (AA'), the P-Si/N-SiC heterojunction (BB'), the P-Si/P-SiC heterojunction (CC'), and the N + -Si/P-SiC heterojunction (DD').To analyze the band state of the SiC/Si VDMOS heterojunction, four tangents in the y direction (AA', BB', CC', and DD') were chosen.We can see that the SiC/Si VDMOS heterojunction is affected not only by the two materials Si and SiC with different bandgaps but also by the doping concentration and different doping types at different regions of the device, which change the heterojunction bandgap of SiC/Si VDMOS.

Figure 6 .
Figure 6.(a) The influence of different interface state charges (acceptorlike) on the energy band diagram of SiC/Si VDMOS, and (b) the influence of different interface state charges (donor) on the energy band diagram of SiC/Si VDMOS: LD = 5 µm, DSi = 0.5 µm.

Figure 7 . 2 Figure 6 .
Figure 7. (a) Vertical electric field distributions for SiC/Si VDMOS at a temperature range of 300 to 2

Figure 7 .
Figure 7. (a) Vertical electric field distributions for SiC/Si VDMOS at a temperature range of 300 to 360 K, and (b) dependences of BV, Ron,sp, and figure-of-merit (FOM = BV 2 /Ron,sp) changes from 300 to 360 K for SiC/Si VDMOS.

Figure 7 .Figure 8 .
Figure 7. (a) Vertical electric field distributions for SiC/Si VDMOS at a temperature range of 300 to 360 K, and (b) dependences of BV, R on,sp , and figure-of-merit (FOM = BV 2 /R on,sp ) changes from 300 to 360 K for SiC/Si VDMOS.

5 5Figure 8 .
Figure 8.(a) Band diagram of the P-Si/N − -SiC heterojunction at a temperature range of 300 to 360 K, and (b) transfer characteristic changes from 300 K to 360 K for SiC/Si VDMOS.

Figure 10 .
Figure 10.(a) The influence of different interface state charges (acceptorlike) on the reverse transfer capacitances (C rss ) for SiC/Si VDMOS, and (b) the influence of different interface state charges (donor) on the reverse transfer capacitances (C rss ) for SiC/Si VDMOS.

Figure 11 . 13 Figure 11 .
Figure 11.(a) Switching characteristics under resistive load for the SiC/Si VDMOS, Si VDMOS, and SiC VDMOS, and (b) the influence of different interface state charges on the switching characteristics for SiC/Si VDMOS.

Figure 12 .
Figure 12. (a-f) is a simplified key process for manufacturing SiC/Si VDMOS.

Figure 12 .
Figure12.(a-f) is a simplified key process for manufacturing SiC/Si VDMOS.

Table 1 .
Device parameters in the simulation.