Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide–nitride–oxide layer and a metal–oxide–semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and −18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (TILD) decreases from 100 to 10 nm, the change in the VTH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin TILD of 50 nm or less need to be designed considering electrical coupling.


Introduction
In recent decades, the scaling of transistors has continuously been improved, and the fabrication technology node of a metal-oxide-semiconductor field-effect transistor (MOSFET) has reached the nanoscale.However, the technical challenges of nanoscale transistors make it difficult to increase transistor integration [1].Moreover, the 2-dimensional planar structure of the MOSFET has secondary effects such as a short-channel effect [2].To overcome these limitations, various solutions have been suggested in terms of devices and circuit design [3][4][5][6][7][8][9][10].Among them, monolithic 3-dimensional integration (M3DI), which allows the vertical stacking of transistors, logic gates, and memory devices, is a promising technology for future chip design [11][12][13][14][15]. Consequently, M3D structures have been researched in terms of transistors, logic gates, and system-level applications.For M3D structures, the transistor density within the same area is higher than that of conventional 2D structures.Moreover, the critical delay of M3DI is low due to vertical interconnection, which is shorter than horizontal interconnection [16].In most of the configuration of the M3D structure, the logic gates are located in the lowest layer and the memory circuits and systems are designed in the upper layer [17][18][19].To facilitate the stacking of each system, an investigation of the memory device, circuit, and system with a stackable structure is required.
One of the candidates for a next-generation memory device is a feedback field-effect transistor (FBFET).The FBFET exhibits an approximately zero slope and hysteresis characteristics [20][21][22].Various circuits consisting of FBFETs operating as logic [23][24][25], memory circuits [26][27][28], and neuromorphic circuits [29,30] have been presented.In particular, the basic fabrication of the FBFET is based on the complementary metal-oxide-semiconductor (CMOS) technology; therefore, memory circuits configured with the FBFET have received attention as a next-generation memory system considering fabrication costs.Recently, a nonvolatile memory FBFET (NVM-FBFET) with a nanowire structure was suggested [31].This NVM-FBFET demonstrates fast erasing and programming times (~1 µs) compared with conventional flash memory.Moreover, the suggested NVM-FBFET can operate as volatile memory (VM) using hysteresis characteristics.When using NVM-FBFET as volatile memory, the hysteresis characteristics themselves do not require a capacitor.This characteristic offers advantages for increasing the memory capacity through transistor scaling, whereas the conventional dynamic random access memory is challenged to increase density due to capacitor scaling [32].When the VM-FBFET is designed with a M3D structure, data transmission is faster due to the reduced physical distance between NVM and VM.Additionally, the data bus width can be increased by stacking the memory circuits, as has already been realized by high-bandwidth memory [33].However, the structure of the suggested NVM-FBFET makes it difficult to stack vertically.The nanowire structure can be designed as a 3D structure at the transistor level, but designing a 3D structure with circuits or at the system level is challenging.In order to stack the NVM-FBFET vertically for M3D design, an investigation of the stackable structure of the NVM-FBFET is required.
When designing the M3D structure, the electrical coupling between the top and bottom transistors or the monolithic interlayer via (MIV) occurs [34].The electrical characteristics of the top-layer transistor were changed due to electrical coupling by the bottom-layer transistors or MIVs.The electrical coupling effects of the various circuits configured with MOSFETs [35], junction-less FETs [36,37], and FBFETs [38,39] have already been investigated.In the case of the NVM-FBFET, the investigation of the electrical coupling has not been conducted yet.For the M3D-NVM-FBFET, the current level considering the electrical coupling is an important factor that decides the '0' and '1' of a bit.Hence, the electrical coupling must be investigated before designing the M3D-NVM-FBFET.
In this paper, the electrical characteristics and the electrical coupling of the M3D-NVM-FBFET are investigated using technology computer-aided design (TCAD).First, the simulation structure of the M3D-NVM-FBFET will be explained in Section 2.Then, the electrical characteristics and the electrical coupling of the M3D-NVM-FBFET will be discussed in Section 3. Finally, the conclusions of this study will be described in Section 4.

Simulation Structure and Parameters
Figure 1a,b show the 3D schematic and its cross-section of the A-A' of the M3D-NVM-FBFET, respectively.The NVM-FBFET located in the top tier in the M3D-NVM-FBFET was benchmarked from the published paper [31].The bottom tier of the M3D-NVM-FBFET is one fully depleted silicon-on-insulator (FD-SOI) metal-oxide-semiconductor field-effect transistor (MOSFET).The M3D-NVM-FBFET consists of the N-type FBFET (NFBFET) including the tunneling oxide-nitride-blocking oxide (ONO) stack.The NFBFET structure is basically configured with p-n-p-n structure.For the M3D structure, an FD-SOI FET structure is used for the NFBFET.This optimal structure of the NFBFET has been researched already [38], and the structure was used for this M3D-NVM-FBFET.The M3D-NVM-FBFET can be fabricated based on the elaboration step of previous work [39], and deposition of the ONO layer must be added before deposition of the gate material in the fabrication flow [40].The materials of the ONO stack are SiO 2 , Si 3 N 4 , and Al 2 O 3 , and the thickness of each ONO layer is 4, 5, and 6 nm, respectively.The total length of the channel region is 100 nm, and the length of each gated and ungated channel region is 50 nm.The doping concentration of each drain, source, and the ungated channel region is 1 × 10 20 cm −3 , and that of the gated channel region is 1 × 10 15 cm −3 .These structure parameters are described in Table 1.The simulation was conducted using commercial TCAD simulator Atlas [41].The physical models including SRH, CVT, FERMI, BGN, CONMOB, FLDMOB, CONSRH, and AUGER for the FBFET simulation and PF.NITRIDE for the NVM simulation were used.
× 10 20 cm −3 , and that of the gated channel region is 1 × 10 15 cm −3 .These structure parameters are described in Table 1.The simulation was conducted using commercial TCAD simulator Atlas [41].The physical models including SRH, CVT, FERMI, BGN, CONMOB, FLD-MOB, CONSRH, and AUGER for the FBFET simulation and PF.NITRIDE for the NVM simulation were used.

Simulation Results
In this section, the simulation results of the M3D-NVM-FBFET will be discussed.First, the mechanism of the M3D-NVM-FBFET will be explained in Section 3.1.Then, the memory characteristics of the M3D-NVM-FBFET for programming, erasing, and retention will be discussed in Section 3.2.Finally, the electrical coupling for the M3D-NVM-FBFET will be discussed in Section 3.3.

Mechanism of the M3D-NVM-FBFET
Figure 2a-c show the energy band of the off state, the forward sweep, and the on state of the M3D-NVM-FBFET, respectively.The black and red lines denote the valence band and the conduction band, respectively.Figure 3 shows the drain-source current (I DS )-gate-source voltage (V GS ) characteristics of the M3D-NVM-FBFET with no charge in the nitride layer.For the off state of the M3D-NVM-FBFET, the drain-source voltage (V DS ) and V GS are applied for 1 and −2 V, respectively.In this state, the carriers from the drain and source regions cannot inject into the channel region due to the potential barriers, as shown in Figure 2a.When the gate voltage starts the forward sweep at −2 V, the potential barrier in the gated channel region is lower, as shown in Figure 2b.Then, the electron from the source region can inject into the ungated channel region by thermionic emission.In the ungated channel region, the injected electrons accumulate and increase the carrier density.Subsequently, the potential barrier at the drain side is lower, so the hole from the drain region can diffuse into the ungated channel region.This positive feedback occurs through interaction between the electron and hole injection, as shown in Figure 2c.The positive feedback increases the current of the M3D-NVM-FBFET steeply, as shown in Figure 3.For the M3D-NVM-FBFET, the threshold voltage (V TH ) is −0.43 V and the subthreshold swing is approximately zero.x Conduction Band Valence band Conduction Band Valence band

Memory Characteristics of the M3D-NVM-FBFET
Figure 4a,b show the energy band of the ONO layer and the trapped electron concentration in the nitride layer for the programming and erasing operations, respectively.The black, red, and blue lines denote the valence band, the conduction band, and the trapped electron concentration, respectively.To simulate the programming operation, trap parameters used in the simulation are described in Table 2.Those parameters are basically based on fitted data on the fabricated NVM devices [42][43][44][45].In order to avoid degradation of the memory performance such as the hot carrier effect [46,47], the very high voltage was applied to the gate electrode utilizing Fowler-Nordheim (FN) tunneling and the drain voltage for read operation is relatively low (~1 V).For the memory opera-

Memory Characteristics of the M3D-NVM-FBFET
Figure 4a,b show the energy band of the ONO layer and the trapped electron concentration in the nitride layer for the programming and erasing operations, respectively.The black, red, and blue lines denote the valence band, the conduction band, and the trapped electron concentration, respectively.To simulate the programming operation, trap parameters used in the simulation are described in Table 2.Those parameters are basically based on fitted data on the fabricated NVM devices [42][43][44][45].In order to avoid degradation of the memory performance such as the hot carrier effect [46,47], the very high voltage was applied to the gate electrode utilizing Fowler-Nordheim (FN) tunneling and the drain voltage for read operation is relatively low (~1 V).For the memory operation, the programming and erasing voltages are 18 and −18 V, respectively.The programming and erasing times are 1 µs.When the programming voltage is applied at the gate, the high electric field directs the potential of the tunneling oxide narrow in the field direction.Then, the electron from the silicon body can be transported into the nitride layer by FN tunneling and trapping in the nitride layer.Moreover, the trapped electron in tunneling oxide can be transported by Poole-Frenkel emission, as shown in Figure 4a.For the erasing operation, the negative voltage is applied at the gate, and then the direction of the electric field is reversed compared to the programming operation.The trapped electrons from the nitride layer are emitted and transported into the silicon channel region by FN tunneling, as shown in Figure 4b.  Figure 5a-c show the energy band of the off state, IDS-VGS characteristics of the M3D-NVM-FBFET after the programming and erasing operations, and IDS-VGS characteristics of the M3D-NVM-FBFET after five cycles, respectively.The red and black lines denote the results after the programming and erasing operations, respectively.For the programming operation, the trapped electrons accumulate holes in the gated channel region.Then, the fermi-energy level of the gated channel region is lower and the potential barrier is higher.Therefore, in order to turn to the on state, higher VGS is required.For the erasing operation, the trapped electrons are eliminated, and then the raised barrier is lower, as shown in Figure 5a.After the programming operation, the VTH of the M3D-NVM-FBFET shifts to 1.78 V.Then, after the erasing operation, the VTH shifts from 1.78 to −0.2 V.For the M3D-NVM-FBFET, the memory window is 1.98 V, as shown in Figure 5b.After the first cycle, the VTH after the programming operation shifts from 1.78 to 1.9 V, and stays almost the same after 2~5 cycles, but one was not changed after the erasing operation, as shown in Figure 5c.  Figure 5a-c show the energy band of the off state, I DS -V GS characteristics of the M3D-NVM-FBFET after the programming and erasing operations, and I DS -V GS characteristics of the M3D-NVM-FBFET after five cycles, respectively.The red and black lines denote the results after the programming and erasing operations, respectively.For the programming operation, the trapped electrons accumulate holes in the gated channel region.Then, the fermi-energy level of the gated channel region is lower and the potential barrier is higher.Therefore, in order to turn to the on state, higher V GS is required.For the erasing operation, the trapped electrons are eliminated, and then the raised barrier is lower, as shown in Figure 5a.After the programming operation, the V TH of the M3D-NVM-FBFET shifts to 1.78 V.Then, after the erasing operation, the V TH shifts from 1.78 to −0.2 V.For the M3D-NVM-FBFET, the memory window is 1.98 V, as shown in Figure 5b.After the first cycle, the V TH after the programming operation shifts from 1.78 to 1.9 V, and stays almost the same after 2~5 cycles, but one was not changed after the erasing operation, as shown in Figure 5c.
x Figure 6 shows the retention characteristics of the M3D-NVM-FBFET.The red and black lines denote the change in the VTH for the M3D-NVM-FBFET after the programming and erasing operations, respectively.The retention simulation was conducted for 10 years (3 × 10 8 s).The memory window of the M3D-NVM-FBFET decreased from 1.98 to 0.83 V, as shown in Figure 6, so that it operates as an NVM.Finally, the comparison of the memory performance for various NVM-FBFETs is summarized in Table 3.The M3D-NVM-FBFET demonstrate the same performance for the programming and erasing oper- Figure 6 shows the retention characteristics of the M3D-NVM-FBFET.The red and black lines denote the change in the VTH for the M3D-NVM-FBFET after the programming and erasing operations, respectively.The retention simulation was conducted for 10 years (3 × 10 8 s).The memory window of the M3D-NVM-FBFET decreased from 1.98 to 0.83 V, as shown in Figure 6, so that it operates as an NVM.Finally, the comparison of the memory performance for various NVM-FBFETs is summarized in Table 3.The M3D-NVM-FBFET demonstrate the same performance for the programming and erasing operation, but improvements in read time and retention characteristics are needed when compared to other NVM-FBFETs.However, only the M3D-NVM-FBFET structure is designed considering M3DI.Table 3.Comparison of the memory performance for various NVM-FBFETs.

The Electrical Coupling Effect for the M3D-NVM-FBFET
Figure 7 shows the IDS-VGS characteristics of the M3D-NVM-FBFET with no charge in the nitride layer at a thickness of the interlayer dielectric (TILD) of 10 and 100 nm at a bottom-gate voltage (VBG) of 0 and 1 V.The black and red lines denote those of a TILD of 10 and 100 nm, respectively, and the solid and dashed lines denote those of a VBG of 0 and 1 V, respectively.The electrical coupling for the M3D-NVM-FBFET is caused by the bottomtier gate.When the VBG changes from 0 to 1 V, the VTH of the M3D-NVM-FBFET also changes, similar to the coupling effect of asymmetric double-gate FD-SOI [50] as follows: where ΔVTH represents the difference in the VTH when the VBG is changed by the ΔVBG, and TONO, εILD, and εONO represent the thickness of the ONO stack and the permittivity of the ILD and the ONO stack, respectively.Here, 1/εONO = 1/εblocking + 1/εnitride + 1/εtunneling, where εblocking, εnitride, and εtunneling are the permittivity of blocking oxide, nitride, and tunneling oxide, respectively.When the TILD decreases, the right-hand term of Equation (1) increases, then the ΔVTH increases, as shown in Figure 7.When the TILD is 100 and 10 nm, the ΔVTH is 0.16 and 0.84 V, respectively.

The Electrical Coupling Effect for the M3D-NVM-FBFET
Figure 7 shows the I DS -V GS characteristics of the M3D-NVM-FBFET with no charge in the nitride layer at a thickness of the interlayer dielectric (T ILD ) of 10 and 100 nm at a bottom-gate voltage (V BG ) of 0 and 1 V.The black and red lines denote those of a T ILD of 10 and 100 nm, respectively, and the solid and dashed lines denote those of a V BG of 0 and 1 V, respectively.The electrical coupling for the M3D-NVM-FBFET is caused by the bottom-tier gate.When the V BG changes from 0 to 1 V, the V TH of the M3D-NVM-FBFET also changes, similar to the coupling effect of asymmetric double-gate FD-SOI [50] as follows: where ∆V TH represents the difference in the V TH when the V BG is changed by the ∆V BG , and T ONO , ε ILD , and ε ONO represent the thickness of the ONO stack and the permittivity of the ILD and the ONO stack, respectively.Here, 1/ε ONO = 1/ε blocking + 1/ε nitride + 1/ε tunneling , where ε blocking , ε nitride , and ε tunneling are the permittivity of blocking oxide, nitride, and tunneling oxide, respectively.When the T ILD decreases, the right-hand term of Equation ( 1) increases, then the ∆V TH increases, as shown in Figure 7.When the T ILD is 100 and 10 nm, the ∆V TH is 0.16 and 0.84 V, respectively.Figure 8 shows the change in the VTH (ΔVTH) for the M3D-NVM-FBFET with various TILD after programming and erasing operations, respectively.The solid and dashed lines denote the ΔVTH after the programming and erasing operations, respectively.The black, red, green, and blue lines denote the ΔVTH at VBG = 1, 0.8, 0.6, and 0.4 V, respectively.When the VBG is applied to the gate of the bottom transistor, the electric field is formed between the top and bottom transistors.Additionally, the magnitude of the field depends on the TILD and the VBG.As the TILD decreases and the VBG increases, the field is stronger, and the change in the VTH increases.When the TILD decreases from 100 to 10 nm, the ΔVTH after the programming and erasing operations increases from 0.16 to 0.87 V and from 0.15 to 0.84 V, respectively.When the VBG increases at TILD = 10 nm, the ΔVTH after the programming and erasing operations increases from 0.14 to 0.87 V and from 0.18 to 0.84 V.As the TILD decreases, the ΔVTH increases abruptly at a TILD of 50 nm.The electrical coupling must be considered below TILD = 50 nm before designing the M3D-NVM-FBFET.T ILD [nm] . Change in the VTH for the M3D-NVM-FBFET with various TILD after the programming (solid line) and erasing (dashed line) operations as a VBG of for 1.0 (black), 0.8 (red), 0.6 (green), and 0.4 V (blue) is applied.Figure 8 shows the change in the V TH (∆V TH ) for the M3D-NVM-FBFET with various T ILD after programming and erasing operations, respectively.The solid and dashed lines denote the ∆V TH after the programming and erasing operations, respectively.The black, red, green, and blue lines denote the ∆V TH at V BG = 1, 0.8, 0.6, and 0.4 V, respectively.When the V BG is applied to the gate of the bottom transistor, the electric field is formed between the top and bottom transistors.Additionally, the magnitude of the field depends on the T ILD and the V BG .As the T ILD decreases and the V BG increases, the field is stronger, and the change in the V TH increases.When the T ILD decreases from 100 to 10 nm, the ∆V TH after the programming and erasing operations increases from 0.16 to 0.87 V and from 0.15 to 0.84 V, respectively.When the V BG increases at T ILD = 10 nm, the ∆V TH after the programming and erasing operations increases from 0.14 to 0.87 V and from 0.18 to 0.84 V.As the T ILD decreases, the ∆V TH increases abruptly at a T ILD of 50 nm.The electrical coupling must be considered below T ILD = 50 nm before designing the M3D-NVM-FBFET.  Figure 8 shows the change in the VTH (ΔVTH) for the M3D-NVM-FBFET with various TILD after programming and erasing operations, respectively.The solid and dashed lines denote the ΔVTH after the programming and erasing operations, respectively.The black, red, green, and blue lines denote the ΔVTH at VBG = 1, 0.8, 0.6, and 0.4 V, respectively.When the VBG is applied to the gate of the bottom transistor, the electric field is formed between the top and bottom transistors.Additionally, the magnitude of the field depends on the TILD and the VBG.As the TILD decreases and the VBG increases, the field is stronger, and the change in the VTH increases.When the TILD decreases from 100 to 10 nm, the ΔVTH after the programming and erasing operations increases from 0.16 to 0.87 V and from 0.15 to 0.84 V, respectively.When the VBG increases at TILD = 10 nm, the ΔVTH after the programming and erasing operations increases from 0.14 to 0.87 V and from 0.18 to 0.84 V.As the TILD decreases, the ΔVTH increases abruptly at a TILD of 50 nm.The electrical coupling must be considered below TILD = 50 nm before designing the M3D-NVM-FBFET.

Conclusions
In this study, the electrical characteristics and electrical coupling effect of the M3D-NVM-FBFET were investigated using TCAD.The M3D-NVM-FBFET is configured with a NVM-FBFET with and a MOSFET in the top and bottom tiers, respectively.For the M3D structure, the FD-SOI structure was used for the NFBFET and the MOSFET.For the memory operation, the programming and erasing voltages were applied at 18 and −18 V, respectively, and the programming and erasing time was 1 µs.The memory window of the M3D-NVM-FBFET was 1.98 V.As the retention simulation was conducted over 10 years, the memory window decreased from 1.98 to 0.83 V, but it can be operated as an NVM.For the M3D-NVM-FBFET, the electrical coupling is caused by the electric field from the bottom-tier transistor, and the magnitude of the field depends on the T ILD and the V BG .When the T ILD decreases, the ∆V TH after the programming and erasing operations changes from 0.16 to 0.87 V and from 0.15 to 0.84 V, respectively.When the V BG increases at T ILD = 10 nm, the ∆V TH after the programming and erasing operations increases from 0.14 to 0.87 V and from 0.18 to 0.84 V.For the memory operation, the electrical coupling must be considered below T ILD = 50 nm before designing the M3D-NVM-FBFET.

Figure 2 .
Figure 2. The energy band of the M3D-NVM-FBFET for (a) the off state (V DS = 1 V and V GS = −2 V), (b) the forward sweep at different V GS (V DS = 1 V), and (c) the on state (V DS = 1 V and V GS = 0 V).

Figure 3 .
Figure 3.I DS -V GS characteristics of the M3D-NVM-FBFET with no charge in the nitride layer (V DS = 1 V).

Micromachines 2023 ,Figure 4 .
Figure 4. Energy band of the ONO layer and the trapped electron concentration in the nitride layer for (a) programming (VGS = 18 V) and (b) erasing operations (VGS = −18 V).

Figure 4 .
Figure 4. Energy band of the ONO layer and the trapped electron concentration in the nitride layer for (a) programming (V GS = 18 V) and (b) erasing operations (V GS = −18 V).

Figure 5 .
Figure 5. (a) Energy band in the off state (V DS = 1 V and V GS = −2 V), (b) I DS -V GS characteristics of the M3D-NVM-FBFET (V DS = 1 V) after the programming operation (red line) and the erasing operation (black line), and (c) I DS -V GS characteristics of the M3D-NVM-FBFET after five cycles.

Figure 7 .
Figure 7. IDS−VGS characteristics of the M3D-NVM-FBFET with no charge in the nitride layer at TILD = 10 and 100 nm at VBG = 0 and 1 V.

Figure 7 .
Figure 7.I DS -V GS characteristics of the M3D-NVM-FBFET with no charge in the nitride layer at T ILD = 10 and 100 nm at V BG = 0 and 1 V.

Figure 7 .
Figure 7. IDS−VGS characteristics of the M3D-NVM-FBFET with no charge in the nitride layer at TILD = 10 and 100 nm at VBG = 0 and 1 V.

Figure 8 .
Figure 8. Change in the VTH for the M3D-NVM-FBFET with various TILD after the programming (solid line) and erasing (dashed line) operations as a VBG of for 1.0 (black), 0.8 (red), 0.6 (green), and 0.4 V (blue) is applied.

Figure 8 .
Figure 8. Change in the V TH for the M3D-NVM-FBFET with various T ILD after the programming (solid line) and erasing (dashed line) operations as a V BG of for 1.0 (black), 0.8 (red), 0.6 (green), and 0.4 V (blue) is applied.

Table 2 .
Trap parameters for the nitride layer for the M3D-NVM-FBFET.

Table 2 .
Trap parameters for the nitride layer for the M3D-NVM-FBFET.

Table 3 .
Comparison of the memory performance for various NVM-FBFETs.