A Novel L-Gate InGaAs/GaAsSb TFET with Improved Performance and Suppressed Ambipolar Effect

A heterojunction tunneling field effect transistor with an L-shaped gate (HJ-LTFET), which is very applicable to operate at low voltage, is proposed and studied by TCAD tools in this paper. InGaAs/GaAsSb heterojunction is applied in HJ-LTFET to enhance the ON-state current (ION). Owing to the quasi-broken gap energy band alignment of InGaAs/GaAsSb heterojunction, height and thickness of tunneling barrier are greatly reduced. However, the OFF-state leakage current (IOFF) also increases significantly due to the reduced barrier height and thickness and results in an obvious source-to-drain tunneling (SDT). In order to solve this problem, an HfO2 barrier layer is inserted between source and drain. Result shows that the insertion layer can greatly suppress the horizontal tunneling leakage appears at the source and drain interface. Other optimization studies such as work function modulation, doping concentration optimization, scaling capability, and analog/RF performance analysis are carried out, too. Finally, the HJ-LTFET with a large ION of 213 μA/μm, a steep average SS of 8.9 mV/dec, and a suppressed IOFF of 10−12 μA/μm can be obtained. Not only that, but the fT and GBP reached the maximum values of 68.3 GHz and 7.3 GHz under the condition of Vd = 0.5 V, respectively.


Introduction
The performance and density of integrated circuits have been significantly enhanced by scaling down of the MOSFET in the past several decades [1]. However, the conventional MOSFETs has a minimum subthreshold swing limited at 60 mV/dec. On the premise of maintaining device performance, scaling of the supply voltage will unavoidably be accompanied with the increasing I OFF , which will finally result in increased static power consumption. Therefore, researchers have to find other ways to solve the contradiction between static power consumption and performance [2][3][4]. Due to their steeper switching behavior than MOSFET, the tunneling field effect transistors (TFET), based on the band-toband tunneling (BTBT) operation mechanism, have been considered as a potential substitute for ultra-low power applications [5][6][7][8][9].
However, low ON-state current, large leakage current, and poor analog performance are three deficiencies that conventional TFETs need to confront [10][11][12][13]. These need to further optimize the conventional TFET for low-power and high-frequency application. In recent years, many research groups have done valuable work to improve the performance of TFET. Many novel TFETs with various structures have been proposed, such as L-TFET [14][15][16], U-TFET, and TGTFET [17][18][19]. Due to larger tunnel junction area and stronger gate-controlled capability, higher ON-state current and lower subthreshold swing than conventional planar TFET can be obtained. In spite of these advantages, the low ONstate current is still one of the greatest challenges of the TFET design. TFET still cannot meet the demand in commercial applications. To further improve the ON-state current, multimaterial heterojunction engineering is applied to improve the band-to-band tunneling rate [20]. Compared with conventional homojunction TFET, research shows that HJTFETs have superior performances, such as Si/SiGe heterojunction [21][22][23][24], SiGeSn/GeSn heterojunction [25], and III-V heterojunction [26][27][28][29][30][31][32]. By selecting appropriate materials to form heterojunction, on the one hand, the height and thickness of the tunneling barrier can be effectively reduced. On the other hand, smaller carrier mass and higher carrier mobility can be achieved than with Si-based TFET. In this way, the tunneling rate can be further improved, and the larger ON-state current can be obtained. However, for HJTFETs, large OFF current, poor analog performance, and bipolar effect still need to be improved.
In this work, a novel InGaAs/GaAsSb HJ-LTFET with a remarkably good switching performance and suppressed ambipolar effect is proposed. Benefiting from the quasibroken gap energy band alignment of InGaAs/GaAsSb heterojunction and high tunneling efficiency of the L-shaped gate structure, HJ-LTFET obtained maximum I ON of 213 µA/µm. Moreover, the insertion of barrier layer between the source and drain obviously suppressed the OFF-state source-to-drain tunneling on horizontal direction. On the other hand, the application of multiple-gate work functions by electrode work function modulation technics [33] obviously suppressed the OFF-state source-to-drain tunneling in the diagonal direction, which can help to achieve the I OFF of 10 −12 µA/µm. Figure 1a shows the structure of the proposed InGaAs/GaAsSb HJ-LTFET. The tunneling junction consists of a p+ GaAs 0.9 Sb 0.1 source with doping concentration of 2 × 10 19 cm −3 and a n + In 0.9 Ga 0.1 As channel layer with doping concentration of 1 × 10 18 cm −3 . To maximize the effective area of line tunneling junction, the source region and channel layer are overlapped as much as possible by structural design. The defined gate length (L g ) and gate height (H g ) are equal to 50 nm, and the thickness of channel (T C ) is 10 nm. In order to suppress the source-to-drain tunneling (SDT) leakage current effectively, a 5 nm thickness HfO2 barrier layer is inserted to suppress the OFF-state tunneling between the source and the drain on the horizontal direction. On the other hand, the metal work function is modified to further reduce the OFF-state tunneling in other directions, such as vertical and diagonal directions. As shown in Figure 1, the metal work function of the dark purple region on the left is 4.75 eV, and that of the light purple region on the right is 4.85 eV. Furthermore, an HfO2 layer with 2 nm thickness is selected as the gate dielectric, which remarkably improves the gate control ability while maintaining enough gate dielectric thickness [34].

Structure and Mechanism of the HJ-LTFET
Micromachines 2022, 13, 1474 2 of 11 cannot meet the demand in commercial applications. To further improve the ON-state current, multi-material heterojunction engineering is applied to improve the band-toband tunneling rate [20]. Compared with conventional homojunction TFET, research shows that HJTFETs have superior performances, such as Si/SiGe heterojunction [21][22][23][24], SiGeSn/GeSn heterojunction [25], and III-V heterojunction [26][27][28][29][30][31][32]. By selecting appropriate materials to form heterojunction, on the one hand, the height and thickness of the tunneling barrier can be effectively reduced. On the other hand, smaller carrier mass and higher carrier mobility can be achieved than with Si-based TFET. In this way, the tunneling rate can be further improved, and the larger ON-state current can be obtained. However, for HJTFETs, large OFF current, poor analog performance, and bipolar effect still need to be improved. In this work, a novel InGaAs/GaAsSb HJ-LTFET with a remarkably good switching performance and suppressed ambipolar effect is proposed. Benefiting from the quasi-broken gap energy band alignment of InGaAs/GaAsSb heterojunction and high tunneling efficiency of the L-shaped gate structure, HJ-LTFET obtained maximum ION of 213 μA/μm. Moreover, the insertion of barrier layer between the source and drain obviously suppressed the OFF-state source-to-drain tunneling on horizontal direction. On the other hand, the application of multiple-gate work functions by electrode work function modulation technics [33] obviously suppressed the OFF-state source-to-drain tunneling in the diagonal direction, which can help to achieve the IOFF of 10 −12 μA/μm. Figure 1a shows the structure of the proposed InGaAs/GaAsSb HJ-LTFET. The tunneling junction consists of a p+ GaAs0.9Sb0.1 source with doping concentration of 2 × 10 19 cm −3 and a n + In0.9Ga0.1As channel layer with doping concentration of 1 × 10 18 cm −3 . To maximize the effective area of line tunneling junction, the source region and channel layer are overlapped as much as possible by structural design. The defined gate length (Lg) and gate height (Hg) are equal to 50 nm, and the thickness of channel (TC) is 10 nm. In order to suppress the source-to-drain tunneling (SDT) leakage current effectively, a 5 nm thickness HfO2 barrier layer is inserted to suppress the OFF-state tunneling between the source and the drain on the horizontal direction. On the other hand, the metal work function is modified to further reduce the OFF-state tunneling in other directions, such as vertical and diagonal directions. As shown in Figure 1, the metal work function of the dark purple region on the left is 4.75 eV, and that of the light purple region on the right is 4.85 eV. Furthermore, an HfO2 layer with 2 nm thickness is selected as the gate dielectric, which remarkably improves the gate control ability while maintaining enough gate dielectric thickness [34].    Figure 2a, electrons are tunneling from p+ GaAsSb source to n+ InGaAs channel. with the gate voltage increasing, the energy bands near the heterojunction will bend downward to meet the BTBT condition. After tunneling, the electrons will transfer from channel to drain and finally be collected by the drain electrode. In the OFF-state, as shown in Figure 2b, there no BTBT occurs, and no tunneling current is observed in HJ-LTFET. Figure 2 shows the ON-state and OFF-state energy band diagram of HJ-LTFET. The cutline positions are shown by the red dotted lines. In the ON-state, as shown in Figure  2a, electrons are tunneling from p+ GaAsSb source to n+ InGaAs channel. with the gate voltage increasing, the energy bands near the heterojunction will bend downward to meet the BTBT condition. After tunneling, the electrons will transfer from channel to drain and finally be collected by the drain electrode. In the OFF-state, as shown in Figure 2b, there no BTBT occurs, and no tunneling current is observed in HJ-LTFET. Correspondingly, the electron and hole current density distribution also show the current switching mechanism of HJ-LTFET, as shown in Figure 3. It is not difficult to see from Figure 3a,b that a small amount of free electrons flows from the channel layer to the drain electrode, forming the IOFF. The OFF-state holes have no contribution to the IOFF because the existence of the HfO2 barrier layer blocks the hole conductive path between the source and drain electrode. This indicates that in the OFF-state, there is no electron tunneling from the source region to the channel. Additionally, the presence of the space charge region results in significant resistance close to the p-n junction. However, in the ON-state, the electron current density and hole current density are extraordinarily high, as shown in Figure 3c,d. These electrons and holes mainly tunnel from heterojunction. Correspondingly, the electron and hole current density distribution also show the current switching mechanism of HJ-LTFET, as shown in Figure 3. It is not difficult to see from Figure 3a,b that a small amount of free electrons flows from the channel layer to the drain electrode, forming the I OFF . The OFF-state holes have no contribution to the I OFF because the existence of the HfO2 barrier layer blocks the hole conductive path between the source and drain electrode. This indicates that in the OFF-state, there is no electron tunneling from the source region to the channel. Additionally, the presence of the space charge region results in significant resistance close to the p-n junction. However, in the ON-state, the electron current density and hole current density are extraordinarily high, as shown in Figure 3c,d. These electrons and holes mainly tunnel from heterojunction. Figure 2 shows the ON-state and OFF-state energy band diagram of HJ-LTFET. The cutline positions are shown by the red dotted lines. In the ON-state, as shown in Figure  2a, electrons are tunneling from p+ GaAsSb source to n+ InGaAs channel. with the gate voltage increasing, the energy bands near the heterojunction will bend downward to meet the BTBT condition. After tunneling, the electrons will transfer from channel to drain and finally be collected by the drain electrode. In the OFF-state, as shown in Figure 2b, there no BTBT occurs, and no tunneling current is observed in HJ-LTFET. Correspondingly, the electron and hole current density distribution also show the current switching mechanism of HJ-LTFET, as shown in Figure 3. It is not difficult to see from Figure 3a,b that a small amount of free electrons flows from the channel layer to the drain electrode, forming the IOFF. The OFF-state holes have no contribution to the IOFF because the existence of the HfO2 barrier layer blocks the hole conductive path between the source and drain electrode. This indicates that in the OFF-state, there is no electron tunneling from the source region to the channel. Additionally, the presence of the space charge region results in significant resistance close to the p-n junction. However, in the ON-state, the electron current density and hole current density are extraordinarily high, as shown in Figure 3c,d. These electrons and holes mainly tunnel from heterojunction. The transfer characteristic curve simulated by Silvaco TCAD is shown in Figure 1b. For the InGaAs/GaAsSb material used in the simulation, we obtained the fitting parameters in [35]. In order to accurately calculate the tunneling process under reverse bias condition, the hurkx BTBT model was used in this work, and models of Fermi-Dirac distri- The transfer characteristic curve simulated by Silvaco TCAD is shown in Figure 1b. For the InGaAs/GaAsSb material used in the simulation, we obtained the fitting parameters in [35]. In order to accurately calculate the tunneling process under reverse bias condition, the hurkx BTBT model was used in this work, and models of Fermi-Dirac distribution, SRH recombination, non-local BTBT and field-dependent mobility were also used along with a band gap narrowing model. Considering both the high-doped source region and the low-doped channel, the BTBT parameters used to calculate the tunneling current are A BTBT= 1.3 × 10 20 (cm −3 s −1 ), and B BTBT= 5.7 × 10 6 (V cm −1 ), respectively [36].  Figure 4a. This is because the higher the N S value, the easier the formation of the BTBT channel, and the smaller the V GS value required to turn ON the BTBT process. When NS is more than 2.0 × 10 19 cm −3 , an OFF-state BTBT phenomenon can be found near the source/channel interface in Figure 4b, which can cause a large I OFF and a small I ON /I OFF . When N S is lower than 2.0 × 10 19 cm −3 , the BTBT leakage channel is switched OFF, and the I OFF is decreased with the increasing N S . This is because large N S can reduce the electron concentration flowing from the source region to the channel, thereby inhibiting the leakage current composed of electron current in the OFF-state. Meanwhile, Figure 4b shows rapid I ON increase due to the increasing of ON-state BTBT rate. The transfer characteristic curve simulated by Silvaco TCAD is shown in Figure 1b. For the InGaAs/GaAsSb material used in the simulation, we obtained the fitting parameters in [35]. In order to accurately calculate the tunneling process under reverse bias condition, the hurkx BTBT model was used in this work, and models of Fermi-Dirac distribution, SRH recombination, non-local BTBT and field-dependent mobility were also used along with a band gap narrowing model. Considering both the high-doped source region and the low-doped channel, the BTBT parameters used to calculate the tunneling current are ABTBT= 1.3 × 10 20 (cm −3 s −1 ), and BBTBT= 5.7 × 10 6 (V cm −1 ), respectively [36].  Figure  4a. This is because the higher the NS value, the easier the formation of the BTBT channel, and the smaller the VGS value required to turn ON the BTBT process. When NS is more than 2.0 × 10 19 cm −3 , an OFF-state BTBT phenomenon can be found near the source/channel interface in Figure 4b, which can cause a large IOFF and a small ION/IOFF. When NS is lower than 2.0 × 10 19 cm −3 , the BTBT leakage channel is switched OFF, and the IOFF is decreased with the increasing NS. This is because large NS can reduce the electron concentration flowing from the source region to the channel, thereby inhibiting the leakage current composed of electron current in the OFF-state. Meanwhile, Figure 4b shows rapid ION increase due to the increasing of ON-state BTBT rate.   Figures 5 and 6. The increase of N C and N D will reduce the channel resistance, resulting in a slight increase in the I ON , as shown in Figures 5b and 6b. However, when the drain doping increases to 1 × 10 18 cm −3 , Figure 6b shows that the I OFF will increase sharply, resulting in a decrease in the I ON /I OFF . This is because the tunneling barrier between source and drain region will decrease with the increase of N D . When the barrier is lower than a certain value, SDT leakage current will be generated.

Effect of Doping Concentration in Source, Channel, and Drain on Device Performance
doping concentration (ND). Changes in NC and ND have little effect on the transfer characteristic, ION, and ION/IOFF, as shown in Figures 5 and 6. The increase of NC and ND will reduce the channel resistance, resulting in a slight increase in the ION, as shown in Figures  5b and 6b. However, when the drain doping increases to 1 × 10 18 cm −3 , Figure 6b shows that the IOFF will increase sharply, resulting in a decrease in the ION/IOFF. This is because the tunneling barrier between source and drain region will decrease with the increase of ND. When the barrier is lower than a certain value, SDT leakage current will be generated.   Figure 7 shows the change of the transfer characteristic, ON-state current, and OFFstate current of HJ-LTFET with different source thickness (TS). It is not difficult to find that, with the increasing TS, the ION increases continuously, and the variation of IOFF can be ignored, which is maintained at around 6 × 10 −12 μA/μm. This is because the increase of TS promotes the generation of free electrons in the source region, thereby increasing the number of tunneling electrons from source to channel and ultimately increasing the current density in the ON-state. teristic, ION, and ION/IOFF, as shown in Figures 5 and 6. The increase of NC and ND will reduce the channel resistance, resulting in a slight increase in the ION, as shown in Figures  5b and 6b. However, when the drain doping increases to 1 × 10 18 cm −3 , Figure 6b shows that the IOFF will increase sharply, resulting in a decrease in the ION/IOFF. This is because the tunneling barrier between source and drain region will decrease with the increase of ND. When the barrier is lower than a certain value, SDT leakage current will be generated.   Figure 7 shows the change of the transfer characteristic, ON-state current, and OFFstate current of HJ-LTFET with different source thickness (TS). It is not difficult to find that, with the increasing TS, the ION increases continuously, and the variation of IOFF can be ignored, which is maintained at around 6 × 10 −12 μA/μm. This is because the increase of TS promotes the generation of free electrons in the source region, thereby increasing the number of tunneling electrons from source to channel and ultimately increasing the current density in the ON-state.  Figure 7 shows the change of the transfer characteristic, ON-state current, and OFFstate current of HJ-LTFET with different source thickness (T S ). It is not difficult to find that, with the increasing T S , the I ON increases continuously, and the variation of I OFF can be ignored, which is maintained at around 6 × 10 −12 µA/µm. This is because the increase of T S promotes the generation of free electrons in the source region, thereby increasing the number of tunneling electrons from source to channel and ultimately increasing the current density in the ON-state.  Figure 8 shows the change of the transfer characteristic, ON-state current, and switching current ratio of HJ-LTFET with different channel thickness (TC). Since the increase of TC increases the area of diagonal tunneling between source and drain, the ION increases with the increase of TC, as shown in Figure 8b. However, when the TC is greater than 10 nm, it will also form an extremely serious tunneling current in the OFF-state, resulting in a decline in device switching performance. In general, it is necessary to compromise between high ION and low IOFF.  Figure 8 shows the change of the transfer characteristic, ON-state current, and switching current ratio of HJ-LTFET with different channel thickness (T C ). Since the increase of T C increases the area of diagonal tunneling between source and drain, the I ON increases with the increase of T C , as shown in Figure 8b. However, when the T C is greater than 10 nm, it will also form an extremely serious tunneling current in the OFF-state, resulting in a decline in device switching performance. In general, it is necessary to compromise between high I ON and low I OFF .  Figure 8 shows the change of the transfer characteristic, ON-state current, and switching current ratio of HJ-LTFET with different channel thickness (TC). Since the increase of TC increases the area of diagonal tunneling between source and drain, the ION increases with the increase of TC, as shown in Figure 8b. However, when the TC is greater than 10 nm, it will also form an extremely serious tunneling current in the OFF-state, resulting in a decline in device switching performance. In general, it is necessary to compromise between high ION and low IOFF.  Figure 9 compares the effect of traditional low-doped spacer layer and modified HFO2 barrier layer with varying thickness between the source and drain on suppressing SDT leakage in OFF-state. It is not hard to find, in Figure 9a, that the SDT phenomenon (consisting of source-to-drain horizontal tunneling and source-to-drain diagonal tunneling) of the traditional structure in OFF-state is particularly serious. After the HfO2 barrier layer is used, the OFF-state electron tunneling on the horizontal direction of source and drain is completely suppressed, which shows that the performance of the modified structure has been greatly improved. For the diagonal tunneling between source and drain, the OFF-state leakage can be further reduced by increasing the thickness of the barrier layer, as shown in Figure 9b. This is because the increased barrier thickness weakens the drain voltage and increases the barrier height of SDT. At the same time, the ION marginally declines as the barrier layer's thickness increases.  Figure 9 compares the effect of traditional low-doped spacer layer and modified HFO2 barrier layer with varying thickness between the source and drain on suppressing SDT leakage in OFF-state. It is not hard to find, in Figure 9a, that the SDT phenomenon (consisting of source-to-drain horizontal tunneling and source-to-drain diagonal tunneling) of the traditional structure in OFF-state is particularly serious. After the HfO2 barrier layer is used, the OFF-state electron tunneling on the horizontal direction of source and drain is completely suppressed, which shows that the performance of the modified structure has been greatly improved. For the diagonal tunneling between source and drain, the OFF-state leakage can be further reduced by increasing the thickness of the barrier layer, as shown in Figure 9b. This is because the increased barrier thickness weakens the drain voltage and increases the barrier height of SDT. At the same time, the I ON marginally declines as the barrier layer's thickness increases.  Figure 10 shows the impact of multi-metal work function modulation on device performance. It can be seen from Figure 10a that the IOFF is reduced by 10 orders of magnitude through raising the work function of the gate2 (WF2) to 4.85 eV. When the WF2 is improved further, the IOFF changes slightly, and the ION will decrease gradually. Therefore, the WF2 can be appropriately improved by the work function modulation method to optimize the device structure.  Figure 10 shows the impact of multi-metal work function modulation on device performance. It can be seen from Figure 10a that the I OFF is reduced by 10 orders of magnitude through raising the work function of the gate2 (WF 2 ) to 4.85 eV. When the WF 2 is improved further, the I OFF changes slightly, and the I ON will decrease gradually. Therefore, the WF 2 can be appropriately improved by the work function modulation method to optimize the device structure. Figure 10 shows the impact of multi-metal work function modulation on device performance. It can be seen from Figure 10a that the IOFF is reduced by 10 orders of magnitude through raising the work function of the gate2 (WF2) to 4.85 eV. When the WF2 is improved further, the IOFF changes slightly, and the ION will decrease gradually. Therefore, the WF2 can be appropriately improved by the work function modulation method to optimize the device structure. In order to analyze the reasons for the above results, the distribution of energy band with or without work function modulation in OFF-state is shown in Figure 10b. The source-to-drain diagonal tunneling is the main cause of OFF-state leakage, and increasing WF2 appropriately can reduce the probability of such tunneling. This is because the energy band close to the drain is raised with the increase of WF2, and the elevation of the conduction band in the drain region increases the barrier of SDT. Therefore, by the application of multi-metal work function, the OFF-state tunneling phenomenon can be suppressed greatly. Figure 11 shows the curve of subthreshold swing (SS) varying with channel length. It is clear to find that the SS changes weakly as the channel length decreases in the vertical and horizontal directions (Vch and Hch). The SS is still lower than 60 mv/dec at Id = 0.1 μA, even if the channel length is reduced to 5 nm in both vertical and horizontal directions. This is because the L-shaped channel expands the length to a certain extent by making full In order to analyze the reasons for the above results, the distribution of energy band with or without work function modulation in OFF-state is shown in Figure 10b. The sourceto-drain diagonal tunneling is the main cause of OFF-state leakage, and increasing WF 2 appropriately can reduce the probability of such tunneling. This is because the energy band close to the drain is raised with the increase of WF 2 , and the elevation of the conduction band in the drain region increases the barrier of SDT. Therefore, by the application of multimetal work function, the OFF-state tunneling phenomenon can be suppressed greatly. Figure 11 shows the curve of subthreshold swing (SS) varying with channel length. It is clear to find that the SS changes weakly as the channel length decreases in the vertical and horizontal directions (V ch and H ch ). The SS is still lower than 60 mv/dec at Id = 0.1 µA, even if the channel length is reduced to 5 nm in both vertical and horizontal directions. This is because the L-shaped channel expands the length to a certain extent by making full use of the vertical space. Compared with conventional planar TFET, the short-channel effects is not prominent with the scaling of the device. Therefore, this structure has excellent scaling capability and device reliability. use of the vertical space. Compared with conventional planar TFET, the short-channel effects is not prominent with the scaling of the device. Therefore, this structure has excellent scaling capability and device reliability.  Figure 12a shows the transconductance curves of the HJTFET at Vds = 0.5 V. The transconductance (gm) can be obtained from the first derivative of the transfer characteristic curve [29], as shown in Equation (1) Figure 12a shows the transconductance curves of the HJTFET at Vds = 0.5 V. The transconductance (g m ) can be obtained from the first derivative of the transfer characteristic curve [29], as shown in Equation (1): Figure 12a shows the transconductance curves of the HJTFET at Vds = 0.5 V. The transconductance (gm) can be obtained from the first derivative of the transfer characteristic curve [29], as shown in Equation (1) As a result, the maximum transconductance of 947 μS/μm can be achieved at Vg = 0.5 V, as shown in Figure 12a. This is benefited from the high current gain contributed by InGaAs/GaAsSb heterojunction and L-shaped gate.

Analog/RF Performance of the HJTFET
It is generally believed that the parasitic capacitance of devices is crucial to the frequency characteristics of integrated circuits, especially the gate capacitance (Cgg). For proposed device structure, Cgg generally consists of gate-to-source capacitance (Cgs) and gateto-drain capacitance (Cgd). Therefore, the characteristics of Cgg, Cgs, and Cgd are of great significance for evaluating the frequency characteristics and analog application ability of devices. As shown in Figure 12b, the Cgd of the HJTFET under 0.5 V gate voltage is 0.15 fF/μm at Vd = 0.5 V, which is much smaller than that of the Cgs (2.0 fF/μm at Vd = 0.5 V). Thus, the Cgg of the HJTFET is mainly determined by Cgs, unlike the general heterojunction devices. This is closely related to the bias voltage applied on the gate and drain.
In addition to parasitic capacitance, cut-off frequency (fT) and gain bandwidth product (GBP) are also significant performance indicators to evaluate the frequency characteristics of devices. The fT depends on the ratio of transconductance to total capacitance [37], As a result, the maximum transconductance of 947 µS/µm can be achieved at Vg = 0.5 V, as shown in Figure 12a. This is benefited from the high current gain contributed by In-GaAs/GaAsSb heterojunction and L-shaped gate.
It is generally believed that the parasitic capacitance of devices is crucial to the frequency characteristics of integrated circuits, especially the gate capacitance (C gg ). For proposed device structure, C gg generally consists of gate-to-source capacitance (C gs ) and gate-to-drain capacitance (C gd ). Therefore, the characteristics of C gg , C gs , and C gd are of great significance for evaluating the frequency characteristics and analog application ability of devices. As shown in Figure 12b, the C gd of the HJTFET under 0.5 V gate voltage is 0.15 fF/µm at Vd = 0.5 V, which is much smaller than that of the C gs (2.0 fF/µm at Vd = 0.5 V). Thus, the C gg of the HJTFET is mainly determined by C gs , unlike the general heterojunction devices. This is closely related to the bias voltage applied on the gate and drain.
In addition to parasitic capacitance, cut-off frequency (f T ) and gain bandwidth product (GBP) are also significant performance indicators to evaluate the frequency characteristics of devices. The fT depends on the ratio of transconductance to total capacitance [37], as shown in Equation (2). If a specific DC gain of 10 is assumed, the GBP can be expressed by Equation (3) [37,38].
By comparison with similar HJ-TFET, the superior DC and high-frequency characteristics of the proposed structure are highlighted, as shown in Table 1.

Conclusions
In this paper, a novel InGaAs/GaAsSb HJ-LTFET device structure based on the line tunneling mechanism is proposed. To reduce the leakage current in the OFF-state, the insertion of a HfO2 barrier layer separates the source region from the drain region to prevent the source-to-drain horizontal tunneling leakage. In addition, by adjusting the electrode work function, the gate metal work function above the drain region is improved to suppress the source drain diagonal tunneling. Meanwhile, the InGaAs/GaAsSb heterojunction of quasi-fault gap energy band alignment as well as large overlap area with an L-shaped between source region and channel layer greatly improve the I ON of the device. Through TCAD simulation, the HJ-LTFET with a large I ON of 213 µA/µm, a steep average SS of 8.9mV/dec, and a maximum fT and GBP of 68.3 GHz and 7.3 GH, respectively, can be obtained. Therefore, the device structure is expected to be widely used in ultra-low power circuits in the future.