Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs

Electro-thermal annealing (ETA) in a MOSFET utilizes Joule heating. The high-temperature heat effectively cures gate dielectric damages induced by electrical stresses or ionizing radiation. However, even though ETA can be used to improve the reliability of logic and memory devices, applying ETA in state-of-the-art field-effect transistors (FETs) such as nanosheet FETs (NS FETs) has not yet been demonstrated. This paper addresses the heat distribution characteristic of an NS FET considering the application of ETA, using 3D simulations. A vacuum inner spacer is newly proposed to improve annealing effects during ETA. In addition, evaluations of the device scaling and annealing effect were performed with respect to gate length, nanosheet-to-nanosheet vertical space, and inner spacer thickness. Guidelines for ETA in NS FETs can be provided on the basis of the results.


Introduction
Semiconductor devices have been shrunk beyond Moore's law, to increase output performance and to reduce power consumption [1]. However, as chip sizes become smaller, it is becoming more difficult to both control short-channel effects (SCEs) and improve device reliability. SCEs lead to increased standby power consumption by increasing off-state current (I OFF ) [2]. SCEs have been suppressed by the evolution of device structures such as FinFETs [3] and gate-all-around (GAA) FETs [4]. It is also possible to improve immunity to SCEs with the aid of advanced material engineering and process technology [5].
In contrast to work on SCEs, there have been few breakthrough advances to address the degradation in reliability resulting from gate dielectric aging, except for lightly doped drain (LDD) and forming gas annealing (FGA), which were developed decades ago [6,7].
Recently, an electro-thermal annealing (ETA) configuration was introduced which utilizes Joule heat generated by the device itself to cure damaged gate dielectrics [8]. The ETA effectively cures the gate dielectric damage produced by hot-carrier injection (HCI), bias-temperature instability (BTI), and even total ionizing dose (TID). In addition, the ETA is applicable for removing contaminants such as photoresist (PR), moisture, or traps existing in channels [9,10]. However, additional power consumption is inevitably required to trigger the ETA.
Several approaches have been proposed to improve the annealing effect and to minimize the power consumption by modifying the device structure or materials [11,12]. However, these previous methods are not fully compatible with state-of-the-art logic transistors such as nanosheet FETs (NS FETs), since the backbone of the NS FET is completely different compared to conventional FinFETs and GAA FETs. This paper demonstrates heat distribution characteristics during ETA in an NS FET. In addition, a novel device structure is provided which enables an improved annealing effect under identical power consumption. The proposed device structure contains a vacuum inner spacer which includes a vacuum dielectric. Device scaling was investigated in terms

Device Structure and Simulation Methodology
In this study, 3D simulations of the NS FETs with a vacuum inner spacer were performed using COMSOL Multiphysics software. The reason for using COMSOL is because it is the most useful tool for analyzing heat during ETA in nanoscale devices [8,12]. Heat transfer in both the solids module and the electric currents module was used. The simulated environmental conditions were assumed to be air, and the heat transfer coefficient (h) for convective cooling was assumed to be 10 W/m 2 K. The mesh sizes were varied from 1 nm to 10 nm according to the structure. All simulations were performed under steady-state conditions. Figure 1 shows a schematic of an NS FET including the vacuum inner spacer. The NS FET has three suspended channels composed of silicon which are surrounded by a high-k and metal gate. effect under identical power consumption. The proposed device structure contains a vacuum inner spacer which includes a vacuum dielectric. Device scaling was investigated in terms of gate module, multiple NS channels, and vacuum inner spacers, and the results are discussed for better use of ETA.

Device Structure and Simulation Methodology
In this study, 3D simulations of the NS FETs with a vacuum inner spacer were performed using COMSOL Multiphysics software. The reason for using COMSOL is because it is the most useful tool for analyzing heat during ETA in nanoscale devices [8,12]. Heat transfer in both the solids module and the electric currents module was used. The simulated environmental conditions were assumed to be air, and the heat transfer coefficient (h) for convective cooling was assumed to be 10 W/m 2 K. The mesh sizes were varied from 1 nm to 10 nm according to the structure. All simulations were performed under steadystate conditions. Figure 1 shows a schematic of an NS FET including the vacuum inner spacer. The NS FET has three suspended channels composed of silicon which are surrounded by a highk and metal gate.   The gate length (L G ), channel width (W NS ), nanosheet thickness (T NS ), and nanosheetto-nanosheet vertical space (V SPC ) were 12 nm, 30 nm, 5 nm, and 15 nm, respectively [13]. The SiO 2 and HfO 2 interlayers of 1 nm and 3 nm, respectively, were deposited on suspended nanosheets as the gate dielectric. The equivalent oxide thickness (EOT) of the gate dielectric was assumed to be 1.53 nm. In terms of gate module, TiAlC was deposited on TiN as the gate metal [14]. Using vacuum spacer structures has several advantages for logic transistors [15][16][17][18][19]. In particular, in an NS FET, the vacuum inner spacer shows superior AC performance for the device with a low-k inner spacer. The vacuum inner spacer for this work was surrounded by a 1 nm Si 3 N 4 outer shell. Detailed information about the device structure and materials is summarized in Tables 1 and 2. Then, a current of 2.5 mA was applied through the gate-to-gate method to trigger ETA for Joule heat generation higher temperature than 600 • C [8].

Figure 2a
shows the heat distribution profile during ETA using gate-to-gate current in an NS FET. During the ETA, the gate temperature was increased beyond 300 • C by Joule heating. The temperature was highest on the surface of the gate electrode, but lowest near the Si substrate, since the Si substrate acted as a heat sink. It was observed that the temperature of the gate surface rose higher than 300 • C, while the temperature in the source and the drain regions remained relatively low because of heat dissipation through the source and drain, which had high thermal conductivity.
Micromachines 2022, 13, x FOR PEER REVIEW 4 of 9 temperature of the gate surface rose higher than 300 °C, while the temperature in the source and the drain regions remained relatively low because of heat dissipation through the source and drain, which had high thermal conductivity.  Figure 2b shows the extracted temperature of an NS FET with respect to the inner spacer materials. The temperature was extracted after reaching a steady state. During the ETA using gate-to-gate current, most of the Joule heat was concentrated in the middle of the gate electrode, as expected. While curing of the gate dielectric characteristics, on the basis of measured ID-VG or gate leakage (IG), is not included in this work, these electrical results have already been reported several times [8].
When the vacuum inner spacer was included, the temperature during the ETA became 6.46% higher than the case with a conventional inner spacer composed solely of Si3N4. Since the thermal conductivity of the inserted vacuum was 0.024 W/(mK), the low thermally conductive vacuum provided thermal isolation during the ETA. As a result, the annealing effect induced by the ETA could be further improved but with identical power consumption. To improve the annealing effect further, it is desirable to provide guidelines related to device scaling such as LG, TIN, and VSPC. In particular, LG is one of the aggressive design parameters in the minimization of semiconductor devices. Figure 3a shows the simulated gate surface temperatures considering LG scaling from 16 nm to 8 nm. As the LG decreased from 12 nm to 8 nm, the temperature dramatically increased over 700 °C under an identical power consumption of 2.5 mA. Temperature sensitivity was approximately 80 °C/nm of LG. As LG decreased, the temperature increased due to the increased gate-to-gate resistance, as shown in Figure 3b. As the cross-sectional area of the gate electrode was reduced by LG scaling, the gate-to-gate resistance increased. Hence, the increased voltage drop across the gate-to-gate interval raised the Joule heat temperature [25]. In addition, when current for the ETA was increased from 2.5 mA to 3 mA, the annealing temperature also increased. However, for a relatively long channel device (i.e., LG = 16 nm), it was difficult to generate a sufficiently high temperature to enable gate dielectric curing, even under a current of 3 mA.  Figure 2b shows the extracted temperature of an NS FET with respect to the inner spacer materials. The temperature was extracted after reaching a steady state. During the ETA using gate-to-gate current, most of the Joule heat was concentrated in the middle of the gate electrode, as expected. While curing of the gate dielectric characteristics, on the basis of measured I D -V G or gate leakage (I G ), is not included in this work, these electrical results have already been reported several times [8].
When the vacuum inner spacer was included, the temperature during the ETA became 6.46% higher than the case with a conventional inner spacer composed solely of Si 3 N 4 . Since the thermal conductivity of the inserted vacuum was 0.024 W/(mK), the low thermally conductive vacuum provided thermal isolation during the ETA. As a result, the annealing effect induced by the ETA could be further improved but with identical power consumption. To improve the annealing effect further, it is desirable to provide guidelines related to device scaling such as L G , T IN , and V SPC . In particular, L G is one of the aggressive design parameters in the minimization of semiconductor devices. Figure 3a shows the simulated gate surface temperatures considering L G scaling from 16 nm to 8 nm. As the L G decreased from 12 nm to 8 nm, the temperature dramatically increased over 700 • C under an identical power consumption of 2.5 mA. Temperature sensitivity was approximately 80 • C/nm of L G . As L G decreased, the temperature increased due to the increased gate-to-gate resistance, as shown in Figure 3b. As the cross-sectional area of the gate electrode was reduced by L G scaling, the gate-to-gate resistance increased. Hence, the increased voltage drop across the gate-to-gate interval raised the Joule heat temperature [25]. In addition, when current for the ETA was increased from 2.5 mA to 3 mA, the annealing temperature also increased. However, for a relatively long channel device (i.e., L G = 16 nm), it was difficult to generate a sufficiently high temperature to enable gate dielectric curing, even under a current of 3 mA.  Figure 4a shows the simulated surface temperature when VSPC was reduced from 20 nm to 10 nm. The temperature during the ETA increased as the VSPC decreased. The temperature sensitivity with respect to VSPC was approximately 101 °C/nm. Considering the extracted sensitivities, the impact of VSPC was greater than the case with LG scaling. When the VSPC decreased, metal gate height also decreased; hence, the gate-to-gate resistance became larger, as shown in Figure 4b. The increased gate-to-gate resistance gave rise to higher generated Joule heat temperature, as described above. Typically, the Joule heat temperature depends on the applied current density, as shown in Figure 4c. However, when VSPC was longer than 20 nm, insufficient Joule heat was generated to be used for the ETA because of the lowered gate-to-gate resistance. Hence, a VSPC narrower than 15 nm would be preferred for a better annealing effect of NS FETs. This tendency coincides with the development trend of current NS FETs toward a narrower VSPC for better packing density [26].  Figure 4a shows the simulated surface temperature when V SPC was reduced from 20 nm to 10 nm. The temperature during the ETA increased as the V SPC decreased. The temperature sensitivity with respect to V SPC was approximately 101 • C/nm. Considering the extracted sensitivities, the impact of V SPC was greater than the case with L G scaling. When the V SPC decreased, metal gate height also decreased; hence, the gate-to-gate resistance became larger, as shown in Figure 4b. The increased gate-to-gate resistance gave rise to higher generated Joule heat temperature, as described above. Typically, the Joule heat temperature depends on the applied current density, as shown in Figure 4c. However, when V SPC was longer than 20 nm, insufficient Joule heat was generated to be used for the ETA because of the lowered gate-to-gate resistance. Hence, a V SPC narrower than 15 nm would be preferred for a better annealing effect of NS FETs. This tendency coincides with the development trend of current NS FETs toward a narrower V SPC for better packing density [26].  Figure 5 shows the simulated surface temperature according to vacuum inner spacer thickness (TIN). Modification of the TIN was independent of the gate-to-gate resistance (not shown). However, the temperature sensitivity during the ETA decreased by approximately 6 °C/nm, as the TIN became thinner. This was the effect of increased heat dissipation. As the TIN decreased, thermal resistance in the source/drain (S/D) extension decreased because of reduced extension length. Hence, heat loss through the S/D extension increased [27].   Figure 5 shows the simulated surface temperature according to vacuum inner spacer thickness (T IN ). Modification of the T IN was independent of the gate-to-gate resistance (not shown). However, the temperature sensitivity during the ETA decreased by approximately 6 • C/nm, as the T IN became thinner. This was the effect of increased heat dissipation. As the T IN decreased, thermal resistance in the source/drain (S/D) extension decreased because of reduced extension length. Hence, heat loss through the S/D extension increased [27]. Figure 6 shows the proposed fabrication process flow for an NS FET with a vacuum inner spacer. Multiple Si/Si x Ge 1−x layers are deposited on the Si substrate using iterative epitaxial growth. After dry etching to form the S/D region, the Si x Ge 1−x is selectively indented etched, as shown in Figure 6b. Then, Si 3 N 4 for the shell of the vacuum dielectric is deposited using a poor step coverage process such as plasma-enhanced chemical vapor deposition (PECVD), as shown in Figure 6c,d. The void acts as a vacuum dielectric. Thereafter, nanosheets are released and suspended during the replacement of the poly-Si gate (RPG) process in Figure 6e. Finally, gate stacks including the gate dielectric and work function adjustment metals are deposited. Figure 5 shows the simulated surface temperature according to vacuum inner spacer thickness (TIN). Modification of the TIN was independent of the gate-to-gate resistance (not shown). However, the temperature sensitivity during the ETA decreased by approximately 6 °C/nm, as the TIN became thinner. This was the effect of increased heat dissipation. As the TIN decreased, thermal resistance in the source/drain (S/D) extension decreased because of reduced extension length. Hence, heat loss through the S/D extension increased [27]. Micromachines 2022, 13, x FOR PEER REVIEW 7 of 9 Figure 6 shows the proposed fabrication process flow for an NS FET with a vacuum inner spacer. Multiple Si/SixGe1−x layers are deposited on the Si substrate using iterative epitaxial growth. After dry etching to form the S/D region, the SixGe1−x is selectively indented etched, as shown in Figure 6b. Then, Si3N4 for the shell of the vacuum dielectric is deposited using a poor step coverage process such as plasma-enhanced chemical vapor deposition (PECVD), as shown in Figure 6c,d. The void acts as a vacuum dielectric. Thereafter, nanosheets are released and suspended during the replacement of the poly-Si gate (RPG) process in Figure 6e. Finally, gate stacks including the gate dielectric and work function adjustment metals are deposited.

Conclusions
The heat distribution characteristics during the ETA of an NS FET were demonstrated using 3D simulations. When the inner spacer in an NS FET was replaced by a vacuum inner spacer instead of the conventional Si3N4 inner spacer, the temperature generated during the ETA increased by 6.46% under identical power consumption. Device scaling with respect to LG, VSPC, and TIN was investigated in relation to the ETA temperature. The VSPC scaling showed a significant temperature increase with a sensitivity of 101 °C/nm. Moreover, LG scaling showed a temperature increase of 80 °C/nm. However, TIN scaling resulted in a decrease in ETA temperature, and the sensitivity was negligible. As

Conclusions
The heat distribution characteristics during the ETA of an NS FET were demonstrated using 3D simulations. When the inner spacer in an NS FET was replaced by a vacuum inner spacer instead of the conventional Si 3 N 4 inner spacer, the temperature generated during the ETA increased by 6.46% under identical power consumption. Device scaling with respect to L G, V SPC , and T IN was investigated in relation to the ETA temperature. The V SPC scaling showed a significant temperature increase with a sensitivity of 101 • C/nm. Moreover, L G scaling showed a temperature increase of 80 • C/nm. However, T IN scaling resulted in a decrease in ETA temperature, and the sensitivity was negligible. As a result, it can be concluded that the proposed NS FET with a vacuum inner spacer is a promising candidate to improve annealing during ETA.

Conflicts of Interest:
The authors declare no conflict of interest.