A 2.5 V, 2.56 ppm/°C Curvature-Compensated Bandgap Reference for High-Precision Monitoring Applications

This work presents a high-precision high-order curvature-compensated bandgap voltage reference (BGR) for battery monitoring applications. The collector currents of bipolar junction transistor (BJT) pairs with different ratios and temperature characteristics can cause greater nonlinearities in ΔVEB. The proposed circuit additionally introduces high-order curvature compensation in the generation of ΔVEB, such that it presents high-order temperature effects complementary to VEB. Fabricated using a 0.18 µm BCD process, the proposed BGR generates a 2.5 V reference voltage with a minimum temperature coefficient of 2.65 ppm/°C in the range of −40 to 125 °C. The minimum line sensitivity is 0.023%/V when supply voltage varies from 4.5 to 5.5 V. The BGR circuit area is 382 × 270 μm2, and the BMIC area is 2.8 × 2.8 mm2.


Introduction
The battery management system (BMS) guarantee the working performance and service life of the battery, and provides new energy management for various applications such as electric vehicles (EVs), energy storage system, and aerospace satellites. Battery monitoring (including voltage, current, temperature, State of Charge (SOC), State of Health (SOH)) is the most basic and core application of the BMS. In typical BMS, it is necessary to constantly evaluate various parameters pertaining to Li-ion battery packs. Monitoring precision is the fundamental guarantee for the reliability and performance of EVs. Figure 1 presents the structure of the proposed BMS.

Introduction
The battery management system (BMS) guarantee the working performance and service life of the battery, and provides new energy management for various applications such as electric vehicles (EVs), energy storage system, and aerospace satellites. Battery monitoring (including voltage, current, temperature, State of Charge (SOC), State of Health (SOH)) is the most basic and core application of the BMS. In typical BMS, it is necessary to constantly evaluate various parameters pertaining to Li-ion battery packs. Monitoring precision is the fundamental guarantee for the reliability and performance of EVs. Figure 1 presents the structure of the proposed BMS. "One master, many slaves" architecture is used for our BMS. The master unit (MU) mainly measures the total voltage, total current, pressure and collision information of the battery pack, calculates the SOC and SOH values, and controls multiple slave units (SUs). The SUs mainly sense the voltage of each battery cell and the temperature of several points in the BMS box. Communication between MU and SUs is through a controller area network (CAN) interface. The battery monitoring integrated circuit (BMIC) is the most significant device used in the BMS slave unit. It connects directly to the battery pack and is designed to monitor multiple cell voltages and temperatures [1,2]. Figure  In order to achieve a high-integration and low-power BMS design as much as possible, a multiplexer structure is used in the BMIC to expand the number of measurable battery cells, and then a high-precision reference circuit and ADC are used to ensure the measurement accuracy. In this structure, the monitoring error mainly comes from the error on the multi-channel sensing channel, the ADC error and the reference error. The accuracy of the voltage reference is the most important criterion that determines the precision of battery monitoring, and it is also an indispensable part in other precision sensors or applications [3][4][5].
Bandgap voltage reference (BGR) is the mainstream temperature-and voltage-insensitive reference used in the field. In high-precision BGR applications, the use of only firstorder linear compensation [6][7][8][9][10][11][12] is insufficient for achieving the required temperature coefficient (TC). Effective and simple high-order temperature compensation methods have thus become the norm for optimized circuit design. The curvature-compensation methods reported in the literature [13][14][15][16][17][18][19][20][21][22] further offset the temperature nonlinearity of the emitter-base voltage (VEB). The topologies in [13] combine opposing curvature characteristics produced by the two BGR cores to achieve the reference voltage. However, even with high-order temperature compensation, the output voltage inevitably drifts owing to factors such as process spread, device aging, and stress. Therefore, the on-chip calibration or trimming structure after production is important to ensure accuracy. The BGR circuits in [14,16] were designed specifically for battery management applications; specifically, the switched-capacitor bandgap reference in [14] and its high-order compensation are achieved by replacing the analog circuitry with a more sophisticated digital correction algorithm [15]. The internal temperature sensor and a lookup table will incur additional cost. The topologies in [16] have piecewise exponential curvature compensation such that good temperature characteristics can be obtained over a wide temperature range, however, the compensation structure is slightly complicated. A zero TC biased MOSFET compensation method is used in [17], but the untrimmed reference voltage is greatly affected In order to achieve a high-integration and low-power BMS design as much as possible, a multiplexer structure is used in the BMIC to expand the number of measurable battery cells, and then a high-precision reference circuit and ADC are used to ensure the measurement accuracy. In this structure, the monitoring error mainly comes from the error on the multi-channel sensing channel, the ADC error and the reference error. The accuracy of the voltage reference is the most important criterion that determines the precision of battery monitoring, and it is also an indispensable part in other precision sensors or applications [3][4][5].
Bandgap voltage reference (BGR) is the mainstream temperature-and voltage-insensitive reference used in the field. In high-precision BGR applications, the use of only first-order linear compensation [6][7][8][9][10][11][12] is insufficient for achieving the required temperature coefficient (TC). Effective and simple high-order temperature compensation methods have thus become the norm for optimized circuit design. The curvature-compensation methods reported in the literature [13][14][15][16][17][18][19][20][21][22] further offset the temperature nonlinearity of the emitterbase voltage (V EB ). The topologies in [13] combine opposing curvature characteristics produced by the two BGR cores to achieve the reference voltage. However, even with high-order temperature compensation, the output voltage inevitably drifts owing to factors such as process spread, device aging, and stress. Therefore, the on-chip calibration or trimming structure after production is important to ensure accuracy. The BGR circuits in [14,16] were designed specifically for battery management applications; specifically, the switched-capacitor bandgap reference in [14] and its high-order compensation are achieved by replacing the analog circuitry with a more sophisticated digital correction algorithm [15]. The internal temperature sensor and a lookup table will incur additional cost. The topologies in [16] have piecewise exponential curvature compensation such that good temperature characteristics can be obtained over a wide temperature range, however, the compensation structure is slightly complicated. A zero TC biased MOSFET compensation method is used in [17], but the untrimmed reference voltage is greatly affected by process spread. The circuit in [18] is an ultra-low-power BGR structure, but the TC of the reference voltage is extremely large. This paper presents a V EB -based high-order curvature-compensated BGR with a low TC over a temperature range of −40 to 125 • C. The designs in [19] exploit different collector currents to enable logarithmic curvature compensation of ∆V EB . Based on the idea, a new ∆V EB generation structure is also proposed. The remainder of this paper is organized as follows. Section 2 illustrates the principle of the proposed BGR, and Section 3 presents the experimental results; the conclusions are presented in Section 4.

Basic BGR Topologies
The V EB of a bipolar junction transistor (BJTs) (or V BE for an NPN transistor) is a complementary-to-absolute-temperature (CTAT) parameter with a TC of about −1.6 mV/ • C, and the temperature dependence of V EB [23] can be expressed as where V G0 (T r ) is the extrapolated bandgap voltage at a reference temperature T r , η is a temperature-insensitive parameter [24], and θ is the temperature dependence order of the collector current. Figure 3 shows two widely used BGR structures based on the first-order temperature compensation.
ΔVEB generation structure is also proposed. The remainder of this paper is organized as follows. Section 2 illustrates the principle of the proposed BGR, and Section 3 presents the experimental results; the conclusions are presented in Section 4.

Basic BGR Topologies
The VEB of a bipolar junction transistor (BJTs) (or VBE for an NPN transistor) is a complementary-to-absolute-temperature (CTAT) parameter with a TC of about −1.6 mV/°C, and the temperature dependence of VEB [23] can be expressed as where VG0(Tr) is the extrapolated bandgap voltage at a reference temperature Tr, η is a temperature-insensitive parameter [24], and θ is the temperature dependence order of the collector current. Figure 3 shows two widely used BGR structures based on the first-order temperature compensation. The bandgap voltage Vbgr of the voltage-mode BGR [6] in Figure 3a is given by ( ) and the Vbgr of the current-mode BGR [7] in Figure 3b is given as where VT = kT/q is the thermal voltage with a TC of about 85 µV/°C, k is the Boltzmann constant, q is the electron charge, and N is the emitter-area ratio of Q2 to Q1. First-order compensation can only decrease the TC of Vref to about 13 ppm/°C in the presence of nonlinearity [6][7][8][9][10][11][12]. In high-precision battery monitoring, it is necessary to detect voltage changes below 3 mV, and the TC of the reference voltage must be less than The bandgap voltage V bgr of the voltage-mode BGR [6] in Figure 3a is given by and the V bgr of the current-mode BGR [7] in Figure 3b is given as where V T = kT/q is the thermal voltage with a TC of about 85 µV/ • C, k is the Boltzmann constant, q is the electron charge, and N is the emitter-area ratio of Q 2 to Q 1 . First-order compensation can only decrease the TC of V ref to about 13 ppm/ • C in the presence of nonlinearity [6][7][8][9][10][11][12]. In high-precision battery monitoring, it is necessary to detect voltage changes below 3 mV, and the TC of the reference voltage must be less than or equal to 6 ppm/ • C [16]. Therefore, further reduction of the TC requires compensation of the higher-order terms related to Tln(T) in V EB .

Insertion of Nonlinear Compensation in ∆V EB
The current-mode or voltage-mode BGRs primarily use the proportional-to-absolutetemperature (PTAT) characteristic of ∆V EB , where ∆V EB is expressed as If the collector currents I c1 and I c2 of the PNP BJT pair (Q 1 and Q 2 ) have the same temperature characteristics, and ∆V EB is a more easily controllable linear compensation term. However, if the TC of collector currents are different, then a nonlinear term is introduced into ∆V EB through the logarithm function.
Therefore, based on the conventional BGR structures in Figure 3, the principle of the curvature-compensated BGR in this work is shown in Figure 4. Based on the original bias current I x of Q 1 and Q 2 , the current I y is introduced and drawn to form the difference in the collector currents of the BJT pair. I x and I y have different temperature characteristics, which lead to an increase in the nonlinearity of ∆V EB . Hence, ∆V EB is rewritten as perature characteristics, and ΔVEB is a more easily controllable linear compensation However, if the TC of collector currents are different, then a nonlinear term is intro into ΔVEB through the logarithm function. Therefore, based on the conventional BGR structures in Figure 3, the principle curvature-compensated BGR in this work is shown in Figure 4. Based on the origin current Ix of Q1 and Q2, the current Iy is introduced and drawn to form the differe the collector currents of the BJT pair. Ix and Iy have different temperature characte which lead to an increase in the nonlinearity of ΔVEB. Hence, ΔVEB is rewritten as Assuming that Iy/Ix is a temperature-dependent function, i.e., x(T) = Iy/Ix. The n logarithm has the Maclaurin series which converges for |x| < 1. The logarithmic term in ΔVEB can thus be calculated a From the Taylor expansion results, it is evident that the logarithmic functio compensate for the third-order term at least. It is worth noting that |x| < 1 is a nec condition, so it must be guaranteed during circuit design. To simulate the compen Assuming that I y /I x is a temperature-dependent function, i.e., x(T) = I y /I x . The natural logarithm has the Maclaurin series which converges for |x| < 1. The logarithmic term in ∆V EB can thus be calculated as From the Taylor expansion results, it is evident that the logarithmic function can compensate for the third-order term at least. It is worth noting that |x| < 1 is a necessary condition, so it must be guaranteed during circuit design. To simulate the compensation ef-fects of (7) on the nonlinear term Tln(T) in V EB , construct the temperature-related functions F 1 (T) and F 2 (T) for the ideal calculations. F 1 (T) and F 2 (T) are expressed as where r 0 is a constant, and h is a coefficient that ensures hT < 1. F 1 (T) and F 2 (T) were combined in different proportions to obtain the predicted compensation results shown in Figure 5.
Micromachines 2022, 13, x FOR PEER REVIEW 5 of 12 effects of (7) on the nonlinear term Tln(T) in VEB, construct the temperature-related functions F1(T) and F2(T) for the ideal calculations. F1(T) and F2(T) are expressed as where r0 is a constant, and h is a coefficient that ensures hT < 1.  It is observed that the deviation between the maximum and minimum values of F1(T) after compensating for F2(T) is only 4% of that before compensation, which better suppresses the nonlinear term in VEB and realizes curvature compensation.
In Figure 4, after obtaining the ΔVEB with high-order compensation effect, the ΔVEB with the coefficient R2/R1 is obtained through R1, R2, M1 and M3, and it is added to the VEB of Q3 to obtain the compensated bandgap voltage Vbgr. In order to further obtain the required reference voltage, the final reference voltage Vref is obtained through the negative feedback structure composed of R3, R4, Rt1 and the amplifier. Vref can be expressed as where the parameters a is the size ratio of M1 and M3.

Implementation of the Proposed Circuit
According to the ideal results obtained above, the main design goal is to introduce a nonlinear ΔVEB in the BGR core circuit. Figure 6 presents the implementation of the proposed circuit, including a start-up circuit, a nonlinear ΔVEB-based curvature-compensated BGR core circuit, a temperature-independent current generating structure, and a final reference voltage output.
The R5 and NMOS M12, M13, M14 constitute a start-up circuit to drive the reference circuit out of the degenerate bias point when the supply voltage VDD is turned on. When VDD rises, M12 and M13 are turned on, and the gate voltage of the PMOS current mirrors is pulled down. After the whole circuit is started, M14 is turned on, and M12 and M13 are turned off. It is observed that the deviation between the maximum and minimum values of F 1 (T) after compensating for F 2 (T) is only 4% of that before compensation, which better suppresses the nonlinear term in V EB and realizes curvature compensation.
In Figure 4, after obtaining the ∆V EB with high-order compensation effect, the ∆V EB with the coefficient R 2 /R 1 is obtained through R 1 , R 2 , M 1 and M 3 , and it is added to the V EB of Q 3 to obtain the compensated bandgap voltage V bgr . In order to further obtain the required reference voltage, the final reference voltage V ref is obtained through the negative feedback structure composed of R 3 , R 4 , R t1 and the amplifier. V ref can be expressed as where the parameters a is the size ratio of M 1 and M 3 .

Implementation of the Proposed Circuit
According to the ideal results obtained above, the main design goal is to introduce a nonlinear ∆V EB in the BGR core circuit. Figure 6 presents the implementation of the proposed circuit, including a start-up circuit, a nonlinear ∆V EB -based curvature-compensated BGR core circuit, a temperature-independent current generating structure, and a final reference voltage output.  Figure 6. Schematic of the proposed curvature-compensated BGR circuit.
The traditional scheme of ΔVEB generation uses currents with the same temperature characteristics to drive a pair of BJTs. The main difference in the proposed nonlinear ΔVEB generation unit is that two sets of currents with different temperature characteristics are used to drive two sets of BJTs (Q1 and Q3, Q2 and Q4). The ΔVEB of the proposed BGR is then given as where the emitter area ratios of Q3 to Q1 and Q4 to Q2 are both N = 24. Analyzing the collector current of each BJT, Q1 and Q3 are biased from the classic PTAT current (IR1 = ΔVEB/R1). However, the collector currents of Q2 and Q4 are mainly the temperature-insensitive current I0 mirrored by M6, which are changed by the compensation currents Ico1 and Ico2. Thus, the high-order temperature characteristics of ΔVEB are changed. The voltage Vfb is equal to Vref because of the effects of the amplifier and NMOS source follower M9. The temperature-insensitive current I0 can be expressed as where the temperature also affects the resistance, the current obtained is not strictly temperature-independent. Ico1 and Ico2 are obtained by mirroring IR1, and are written as The traditional scheme of ∆V EB generation uses currents with the same temperature characteristics to drive a pair of BJTs. The main difference in the proposed nonlinear ∆V EB generation unit is that two sets of currents with different temperature characteristics are used to drive two sets of BJTs (Q 1 and Q 3 , Q 2 and Q 4 ). The ∆V EB of the proposed BGR is then given as where the emitter area ratios of Q 3 to Q 1 and Q 4 to Q 2 are both N = 24. Analyzing the collector current of each BJT, Q 1 and Q 3 are biased from the classic PTAT current (I R1 = ∆V EB /R 1 ). However, the collector currents of Q 2 and Q 4 are mainly the temperatureinsensitive current I 0 mirrored by M 6 , which are changed by the compensation currents I co1 and I co2 . Thus, the high-order temperature characteristics of ∆V EB are changed. The voltage V fb is equal to V ref because of the effects of the amplifier and NMOS source follower M 9 . The temperature-insensitive current I 0 can be expressed as where the temperature also affects the resistance, the current obtained is not strictly temperature-independent. I co1 and I co2 are obtained by mirroring I R1 , and are written as where y 1 and y 2 are the size ratios between the corresponding metal-oxide semiconductors. The parameters z trim1 and z trim2 are set by the trimming module in Figure 6, and the parameters y 1 and y 2 are adjusted to change the temperature drift of the output. Based on I R1 and I 0 , the corresponding I c1 , I c2 , I c3 , I c4 and parameters are expressed as The drain currents of M 3 , M 8 , M 10 and M 11 are obtained by mirroring M 1 , those of M 2 and M 4 are mirrored from M 6 , and the parameters b, x 1 , x 2 , y 1 and y 2 are the scale coefficients. By substituting (13) into (10), we obtain Assuming that x 2 = cx 1 and y 2 = cy 1 , where c is a constant. (14) can be rewritten as In Equation (15), it can be seen that the curvature compensation term shown as F 2 (T) in Equation (8) is introduced into ∆V EB to compensate for the nonlinearity of V EB . Once the desired ∆V EB is obtained, I R1 is mirrored by M 5 , and the resulting V bgr is expressed as Substitute (16) into (9) to obtain the final reference voltage V ref .

Process Variations and Trimming
The BJTs, resistances, and current mirrors in the proposed BGR circuit are the main sources of error owing to process variations and mismatches. BGR error sources are classified into two types: PTAT and non-PTAT errors. The errors caused by the spread of BJT saturation current and resistances R 1 and R 2 are mainly of the PTAT type. The BJT current gain spread, BJT base resistance, opamp offset, and BJT collector current mismatches mainly constitute the non-PTAT errors.
PTAT errors are easily eliminated; thus, non-PTAT errors often determine the achievable precision of the BGR and require additional structures to ensure circuit accuracy. The proposed circuit contains many current mirror structures to provide bias and compensation currents for different BJTs. To minimize mismatches in the current mirrors, cascode-type current mirrors are used in the circuit to improve precision. In addition, the non-PTAT errors caused by process changes affect the proposed high-order curvature compensation method. The proposed trimming structure is shown in Figure 7.  Figure 7a is a 4-bit trimming resistance network [16] for I0 scaling, which is mainly used to ensure that the I0 change caused by the resistance spread does not affect the curvature compensation precision. At the same time, the change of I0 will also change the parameters c in (16). Figure 7b also depicts a 4-bit trimming structure for scaling the compensation currents Ico1 and Ico2 in the proposed circuit. This trimming structure is connected to the two nodes A and B shown in Figure 6 to change the parameters y1/x1 in (16) and achieve curvature compensation trimming. The two trimming blocks ensure appropriate curvature compensations in the presence of process variations or different application requirements. There are also trimming resistance Rt1 connected to the output to adjust the reference voltage Vref. All trimming signals are generated by a fuse module controlled by the digital unit in our BMIC chip.

Experimental Results
Firstly, the temperature characteristics of some key points are analyzed based on the simulation results. Figure 8a presents the simulation results of VEB and ΔVEB with temperature changes. The nonlinear ΔVEB and VEB present complementary slope trends in the range of −40 to 125 °C. The bandgap voltage Vbgr before and after curvature compensation is shown in Figure 8b. Vbgr-1order is a first-order compensation result achieved after removing nonlinear compensation. The simulated results reveal that the maximum and minimum differences  Figure 7a is a 4-bit trimming resistance network [16] for I 0 scaling, which is mainly used to ensure that the I 0 change caused by the resistance spread does not affect the curvature compensation precision. At the same time, the change of I 0 will also change the parameters c in (16). Figure 7b also depicts a 4-bit trimming structure for scaling the compensation currents I co1 and I co2 in the proposed circuit. This trimming structure is connected to the two nodes A and B shown in Figure 6 to change the parameters y 1 /x 1 in (16) and achieve curvature compensation trimming. The two trimming blocks ensure appropriate curvature compensations in the presence of process variations or different application requirements. There are also trimming resistance R t1 connected to the output to adjust the reference voltage V ref . All trimming signals are generated by a fuse module controlled by the digital unit in our BMIC chip.

Experimental Results
Firstly, the temperature characteristics of some key points are analyzed based on the simulation results. Figure 8a presents the simulation results of V EB and ∆V EB with temperature changes. The nonlinear ∆V EB and V EB present complementary slope trends in the range of −40 to 125 • C.  Figure 7a is a 4-bit trimming resistance network [16] for I0 scaling, which is mainly used to ensure that the I0 change caused by the resistance spread does not affect the curvature compensation precision. At the same time, the change of I0 will also change the parameters c in (16). Figure 7b also depicts a 4-bit trimming structure for scaling the compensation currents Ico1 and Ico2 in the proposed circuit. This trimming structure is connected to the two nodes A and B shown in Figure 6 to change the parameters y1/x1 in (16) and achieve curvature compensation trimming. The two trimming blocks ensure appropriate curvature compensations in the presence of process variations or different application requirements. There are also trimming resistance Rt1 connected to the output to adjust the reference voltage Vref. All trimming signals are generated by a fuse module controlled by the digital unit in our BMIC chip.

Experimental Results
Firstly, the temperature characteristics of some key points are analyzed based on the simulation results. Figure 8a presents the simulation results of VEB and ΔVEB with temperature changes. The nonlinear ΔVEB and VEB present complementary slope trends in the range of −40 to 125 °C. The bandgap voltage Vbgr before and after curvature compensation is shown in Figure 8b. Vbgr-1order is a first-order compensation result achieved after removing nonlinear compensation. The simulated results reveal that the maximum and minimum differences The bandgap voltage V bgr before and after curvature compensation is shown in Figure 8b. V bgr-1order is a first-order compensation result achieved after removing nonlinear compensation. The simulated results reveal that the maximum and minimum differences in V bgr are reduced from 2 mV (without curvature compensation) to 0.2 mV (with curvature compensation) in the range of −40 to 125 • C. The best-found TC of V bgr is 0.7 ppm/ • C in the simulation result shown in Figure 8b. Figure 9 presents the 500 runs Monte Carlo (MC) simulation results of the proposed BGR with a 5 V supply voltage. The variation (σ/µ) of the reference voltage from MC results is 0.271% in Figure 9a. In Figure 9b, the statistical distribution of the TCs indicates that the average TC is 2.63 ppm/ • C and the standard deviation is 1.48 ppm/ • C. The MC simulation results show that the circuit is insensitive to mismatch.
Micromachines 2022, 13, x FOR PEER REVIEW 9 of 12 in Vbgr are reduced from 2 mV (without curvature compensation) to 0.2 mV (with curvature compensation) in the range of −40 to 125 °C. The best-found TC of Vbgr is 0.7 ppm/°C in the simulation result shown in Figure 8b. Figure 9 presents the 500 runs Monte Carlo (MC) simulation results of the proposed BGR with a 5 V supply voltage. The variation (σ/µ) of the reference voltage from MC results is 0.271% in Figure 9a. In Figure 9b, the statistical distribution of the TCs indicates that the average TC is 2.63 ppm/°C and the standard deviation is 1.48 ppm/°C. The MC simulation results show that the circuit is insensitive to mismatch.  Figure 10a presents the chip microphotographs of proposed high-precision BGR circuit in the designed BMIC, which was implemented in a 0.18 µm BCD process. The whole BMIC area is 2.8 × 2.8 mm 2 , and the BGR circuit occupies a chip area of 0.38 × 0.27 mm 2 . We designed a BMIC test circuit to test the temperature and other related characteristics of the reference voltage of the chip. In the test circuit, place the BMIC in a white circle whose size corresponds to the cover of the temperature controller, isolated from other power supply and control modules, as shown in Figure 10b. This is to independently test the BMIC while simulating rapid temperature changes, ensuring accurate testing. At the same time, on the PCB, the relevant signals are connected to the outside of the white circle to ensure that the reference voltage changes can be monitored without affecting the temperature test.    Figure 10a presents the chip microphotographs of proposed high-precision BGR circuit in the designed BMIC, which was implemented in a 0.18 µm BCD process. The whole BMIC area is 2.8 × 2.8 mm 2 , and the BGR circuit occupies a chip area of 0.38 × 0.27 mm 2 . We designed a BMIC test circuit to test the temperature and other related characteristics of the reference voltage of the chip. In the test circuit, place the BMIC in a white circle whose size corresponds to the cover of the temperature controller, isolated from other power supply and control modules, as shown in Figure 10b. This is to independently test the BMIC while simulating rapid temperature changes, ensuring accurate testing. At the same time, on the PCB, the relevant signals are connected to the outside of the white circle to ensure that the reference voltage changes can be monitored without affecting the temperature test.
Micromachines 2022, 13, x FOR PEER REVIEW 9 of 12 in Vbgr are reduced from 2 mV (without curvature compensation) to 0.2 mV (with curvature compensation) in the range of −40 to 125 °C. The best-found TC of Vbgr is 0.7 ppm/°C in the simulation result shown in Figure 8b. Figure 9 presents the 500 runs Monte Carlo (MC) simulation results of the proposed BGR with a 5 V supply voltage. The variation (σ/µ) of the reference voltage from MC results is 0.271% in Figure 9a. In Figure 9b, the statistical distribution of the TCs indicates that the average TC is 2.63 ppm/°C and the standard deviation is 1.48 ppm/°C. The MC simulation results show that the circuit is insensitive to mismatch.  Figure 10a presents the chip microphotographs of proposed high-precision BGR circuit in the designed BMIC, which was implemented in a 0.18 µm BCD process. The whole BMIC area is 2.8 × 2.8 mm 2 , and the BGR circuit occupies a chip area of 0.38 × 0.27 mm 2 . We designed a BMIC test circuit to test the temperature and other related characteristics of the reference voltage of the chip. In the test circuit, place the BMIC in a white circle whose size corresponds to the cover of the temperature controller, isolated from other power supply and control modules, as shown in Figure 10b. This is to independently test the BMIC while simulating rapid temperature changes, ensuring accurate testing. At the same time, on the PCB, the relevant signals are connected to the outside of the white circle to ensure that the reference voltage changes can be monitored without affecting the temperature test.     Figure 11a. Process deviations cause the BGR output voltage to exhibit a positive temperature sensitivity, with an average TC of 26.04 ppm/ • C. Figure 11b presents the measured V ref results after TC trimming and voltage magnitude trimming. The tested optimal and worst TCs were 2.56 and 4.75 ppm/ • C, respectively, and the σ/µ of the reference voltage is 0.11% at room temperature. The untrimmed inaccuracy is about ±0.43% (the maximum and minimum difference of V bgr is 10.3 mV) over a temperature range of 165 • C, which decreases to approximately ±0.05% (the maximum and minimum difference of V ref is 2.4 mV) after trimming at ambient temperature.
Micromachines 2022, 13, x FOR PEER REVIEW 10 of 12 results are shown in Figure 11a. Process deviations cause the BGR output voltage to exhibit a positive temperature sensitivity, with an average TC of 26.04 ppm/°C. Figure 11b presents the measured Vref results after TC trimming and voltage magnitude trimming. The tested optimal and worst TCs were 2.56 and 4.75 ppm/°C, respectively, and the σ/µ of the reference voltage is 0.11% at room temperature. The untrimmed inaccuracy is about ±0.43% (the maximum and minimum difference of Vbgr is 10.3 mV) over a temperature range of 165 °C, which decreases to approximately ±0.05% (the maximum and minimum difference of Vref is 2.4 mV) after trimming at ambient temperature.
(a) (b) Figure 11. Measured TCs of six samples: (a) untrimmed Vbgr as a function of temperature; (b) trimmed Vref as a function of temperature.
In Figure 12a, it can be seen that the Vref remains stable by continuously reducing the input voltage from 5.5 V to 4.5 V. Figure 12b presents the variation of six reference voltages versus supply at room temperature. When the supply voltage is increased from 4.5 to 5.5 V, the average variation in Vref is 0.58 mV. Therefore, the average line sensitivity is 0.023%/V.  Table 1 summarizes the performances of the proposed BGR and compares it with some state-of-the-art designs. Compared to other BGR circuits, the proposed design achieves excellent temperature insensitivity, with a TC of 2.56 ppm/°C in the range of −40 to 125 °C. The current consumption of BGR is 53 µA with a 5 V supply voltage, and the area of the fabricated BGR circuit is 0.103 mm 2 . In Figure 12a, it can be seen that the V ref remains stable by continuously reducing the input voltage from 5.5 V to 4.5 V. Figure 12b presents the variation of six reference voltages versus supply at room temperature. When the supply voltage is increased from 4.5 to 5.5 V, the average variation in V ref is 0.58 mV. Therefore, the average line sensitivity is 0.023%/V. results are shown in Figure 11a. Process deviations cause the BGR output voltage to exhibit a positive temperature sensitivity, with an average TC of 26.04 ppm/°C. Figure 11b presents the measured Vref results after TC trimming and voltage magnitude trimming. The tested optimal and worst TCs were 2.56 and 4.75 ppm/°C, respectively, and the σ/µ of the reference voltage is 0.11% at room temperature. The untrimmed inaccuracy is about ±0.43% (the maximum and minimum difference of Vbgr is 10.3 mV) over a temperature range of 165 °C, which decreases to approximately ±0.05% (the maximum and minimum difference of Vref is 2.4 mV) after trimming at ambient temperature.
(a) (b) Figure 11. Measured TCs of six samples: (a) untrimmed Vbgr as a function of temperature; (b) trimmed Vref as a function of temperature.
In Figure 12a, it can be seen that the Vref remains stable by continuously reducing the input voltage from 5.5 V to 4.5 V. Figure 12b presents the variation of six reference voltages versus supply at room temperature. When the supply voltage is increased from 4.5 to 5.5 V, the average variation in Vref is 0.58 mV. Therefore, the average line sensitivity is 0.023%/V.  Table 1 summarizes the performances of the proposed BGR and compares it with some state-of-the-art designs. Compared to other BGR circuits, the proposed design achieves excellent temperature insensitivity, with a TC of 2.56 ppm/°C in the range of −40 to 125 °C. The current consumption of BGR is 53 µA with a 5 V supply voltage, and the area of the fabricated BGR circuit is 0.103 mm 2 .  Table 1 summarizes the performances of the proposed BGR and compares it with some state-of-the-art designs. Compared to other BGR circuits, the proposed design achieves excellent temperature insensitivity, with a TC of 2.56 ppm/ • C in the range of −40 to 125 • C. The current consumption of BGR is 53 µA with a 5 V supply voltage, and the area of the fabricated BGR circuit is 0.103 mm 2 .

Conclusions
A 2.5 V, 2.56 ppm/ • C high-order curvature-corrected BGR over a temperature range of −40 to 125 • C is presented herein and implemented using 0.18 µm BCD technology. The circuit is based on the classic BGR structure using currents of different ratios and TCs to bias two sets of BJT pairs, thereby introducing nonlinear terms with compensation effects in ∆VEB to achieve temperature-independent voltage. The proposed structure is suitable for high-precision battery monitoring applications, such as EVs, energy storage, etc. Furthermore, this circuit has been used in the designed BMIC.