A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications

This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching energy of 63.56 CVref2, achieving a reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of Vcm and complexity of DAC control logic and DAC driver circuit. Moreover, dynamic circuits and automatic ON/OFF technology are used to reduce power consumption of comparator and SAR logic. The prototype is designed and fabricated in a 180 nm CMOS with a core size of 500 μm × 300 μm (0.15 mm2). It consumes 7.6 nW at 1 kS/s sampling rate and 1.8-V supply with an achieved signal-to-noise-and distortion ratio of 45.90 dB and a resulting figure of merit of 51.7 fJ/conv.-step.


Introduction
The development of low-power integrated circuits (ICs) will help bring portable and implantable biomedical devices and biosensors to the market. Analog front end (AFE) circuits in these products may consume most of the total power budget because they usually need to remain online to sense input signals continuously [1]. Various biomedical signals and their frequency ranges are shown in Table 1. Most biomedical signals have frequencies below 1 kHz. Figure 1 shows the basic processing units in a biomedical implantable device [2]; ADC is an intermediate unit that converts analog signals into digital signals. Successive-approximation register (SAR) analog-to-digital converter (ADC) has become an appropriate choice for low-power biomedical applications in recent years due to its low-power characteristics [2][3][4][5]. Figure 2 shows the basic components in an SAR ADC. Among the building blocks in an SAR ADC, a capacitive DAC always consumes a significant part of the total power consumption [6][7][8]. Recently, some energy-efficient switching schemes have been proposed to reduce the energy consumption of DAC capacitor arrays. [8][9][10]. Compared to conventional techniques [11], Charge-Recovery [8], Charge-Sharing [8], Capacitor-Splitting [8], Set-and-down [10], and V cm -based [9] techniques reduce the switching energy by 12.52%, 24.99%, 37.48%, 81.26%, and 87.52%, respectively. However, these schemes have various drawbacks. Capacitor-Splitting [8] and V cm -based [9] schemes have complex DAC drive circuits, the Set-and-down scheme [10] has large common-mode voltage shift, and the V cm -based scheme [9] has a high dependence on the middle reference voltage (V cm ).

Biomedical Signals Frequency Range
ECG [2] 0.05-100 Hz ECoG [12] 70-110 Hz EMG [13] 50-150 Hz EEG [14] 0-100 Hz  Biomedical Signals Frequency Range ECG [2] 0.05-100 Hz ECoG [12] 70-110 Hz EMG [13] 50-150 Hz EEG [14] 0-100 Hz In this paper, the energy-efficient and low-complexity switching scheme [15] is used to realize successive approximation conversion. In the first comparison, no switching energy was consumed due to the use of top-plate sampling technology [10]. In the second comparison, no switching energy was consumed due to the closed-loop charge recycling method [16]. From the third comparison to the (N−1)th comparison, the reference voltage of the corresponding capacitor in the lower voltage capacitor array changes from gnd to Vref. In the last comparison, the reference voltage of the last capacitor in the lower voltage capacitor array changes from gnd to Vcm. From the third comparison to the last comparison, since there is only one capacitor-switching reference voltage for each comparison, the power consumption is low. As a result, the energy-efficient and low-complexity switching scheme achieves an average switching energy of 63.56 2 ref CV . Compared with the conventional switching scheme [11], this switching scheme reduces the switching energy by 95.34%. In addition, only the least significant bit (LSB) depends on the accuracy of Vcm, and each capacitor only uses two reference voltages, which reduces the dependence on the accuracy of Vcm and the complexity of DAC control logic and DAC driver circuit. An automatic ON/OFF comparator is used to achieve low power consumption. The comparator consists of three parts: the automatic ON/OFF clock circuit, the dynamic preamplifier stage, and the dynamic latch stage. The automatic ON/OFF clock circuit allows the comparator to work only during comparing. Automatic ON/OFF SAR Logic consists of three parts: automatic ON/OFF clock circuit, shift control, data latch. The automatic ON/OFF clock signal is generated by the comparator output signal, and the clock is output only when the comparator is active. In order to simplify the DAC control logic and DAC driver circuit, the latch of SAR logic uses a dynamic latch with differential output. When the proposed SAR ADC uses 180 nm CMOS process and operates at a sampling rate of 1 kS/s, the ADC achieves 45.90 dB SNDR and 58.79 dB SFDR and consumes only 7.6 nW [17]. The proposed SAR ADC is suitable for portable and implantable medical sensors.  Biomedical Signals Frequency Range ECG [2] 0.05-100 Hz ECoG [12] 70-110 Hz EMG [13] 50-150 Hz EEG [14] 0-100 Hz In this paper, the energy-efficient and low-complexity switching scheme [15] is used to realize successive approximation conversion. In the first comparison, no switching energy was consumed due to the use of top-plate sampling technology [10]. In the second comparison, no switching energy was consumed due to the closed-loop charge recycling method [16]. From the third comparison to the (N−1)th comparison, the reference voltage of the corresponding capacitor in the lower voltage capacitor array changes from gnd to Vref. In the last comparison, the reference voltage of the last capacitor in the lower voltage capacitor array changes from gnd to Vcm. From the third comparison to the last comparison, since there is only one capacitor-switching reference voltage for each comparison, the power consumption is low. As a result, the energy-efficient and low-complexity switching scheme achieves an average switching energy of 63.56 2 ref CV . Compared with the conventional switching scheme [11], this switching scheme reduces the switching energy by 95.34%. In addition, only the least significant bit (LSB) depends on the accuracy of Vcm, and each capacitor only uses two reference voltages, which reduces the dependence on the accuracy of Vcm and the complexity of DAC control logic and DAC driver circuit. An automatic ON/OFF comparator is used to achieve low power consumption. The comparator consists of three parts: the automatic ON/OFF clock circuit, the dynamic preamplifier stage, and the dynamic latch stage. The automatic ON/OFF clock circuit allows the comparator to work only during comparing. Automatic ON/OFF SAR Logic consists of three parts: automatic ON/OFF clock circuit, shift control, data latch. The automatic ON/OFF clock signal is generated by the comparator output signal, and the clock is output only when the comparator is active. In order to simplify the DAC control logic and DAC driver circuit, the latch of SAR logic uses a dynamic latch with differential output. When the proposed SAR ADC uses 180 nm CMOS process and operates at a sampling rate of 1 kS/s, the ADC achieves 45.90 dB SNDR and 58.79 dB SFDR and consumes only 7.6 nW [17]. The proposed SAR ADC is suitable for portable and implantable medical sensors. In this paper, the energy-efficient and low-complexity switching scheme [15] is used to realize successive approximation conversion. In the first comparison, no switching energy was consumed due to the use of top-plate sampling technology [10]. In the second comparison, no switching energy was consumed due to the closed-loop charge recycling method [16]. From the third comparison to the (N−1)th comparison, the reference voltage of the corresponding capacitor in the lower voltage capacitor array changes from gnd to V ref . In the last comparison, the reference voltage of the last capacitor in the lower voltage capacitor array changes from gnd to V cm . From the third comparison to the last comparison, since there is only one capacitor-switching reference voltage for each comparison, the power consumption is low. As a result, the energy-efficient and low-complexity switching scheme achieves an average switching energy of 63.56 CV 2 re f . Compared with the conventional switching scheme [11], this switching scheme reduces the switching energy by 95.34%. In addition, only the least significant bit (LSB) depends on the accuracy of V cm , and each capacitor only uses two reference voltages, which reduces the dependence on the accuracy of V cm and the complexity of DAC control logic and DAC driver circuit. An automatic ON/OFF comparator is used to achieve low power consumption. The comparator consists of three parts: the automatic ON/OFF clock circuit, the dynamic preamplifier stage, and the dynamic latch stage. The automatic ON/OFF clock circuit allows the comparator to work only during comparing. Automatic ON/OFF SAR Logic consists of three parts: automatic ON/OFF clock circuit, shift control, data latch. The automatic ON/OFF clock signal is generated by the comparator output signal, and the clock is output only when the comparator is active. In order to simplify the DAC control logic and DAC driver circuit, the latch of SAR logic uses a dynamic latch with differential output. When the proposed SAR ADC uses 180 nm CMOS process and operates at a sampling rate of 1 kS/s, the ADC achieves 45.90 dB SNDR and 58.79 dB SFDR and consumes only 7.6 nW [17]. The proposed SAR ADC is suitable for portable and implantable medical sensors. This paper is organized as follows. Section 2 describes the ADC architecture and low-power circuits. Section 3 shows the measurement results and the comparison with other ADCs. Finally, Section 4 concludes.

Proposed ADC Architecture
As shown in Figure 3, the proposed SAR ADC consists of comparator, SAR logic, capacitor array DAC and DAC drive circuit. Because each capacitor of the capacitor array DAC has only two reference voltages, the DAC drive circuit and DAC control logic are simple. In addition, because the last capacitor uses V cm as the reference voltage, the number of unit capacitors is reduced by half. This paper is organized as follows. Section 2 describes the ADC architecture and lowpower circuits. Section 3 shows the measurement results and the comparison with other ADCs. Finally, Section 4 concludes.

Proposed ADC Architecture
As shown in Figure 3, the proposed SAR ADC consists of comparator, SAR logic, capacitor array DAC and DAC drive circuit. Because each capacitor of the capacitor array DAC has only two reference voltages, the DAC drive circuit and DAC control logic are simple. In addition, because the last capacitor uses Vcm as the reference voltage, the number of unit capacitors is reduced by half.

Switching Scheme
As shown in Figure 4, the operation of the switching scheme can be performed in five phases: sampling, the 1st comparison, the 2nd comparison, the 3rd to (N−1)th comparison, and the Nth comparison.
Sampling: In the sampling phase, the input signals are sampled on the top-plates of all capacitors via sampling switch, with the bottom-plates of the largest capacitors connecting to Vref and other capacitors to gnd.
The 1st comparison: After sampling, the sampling switches are turned off. The output voltages of the DAC capacitor array are found to be The comparator compares the sampling signals (Vip and Vin) and gets D1(MSB). No switching energy is consumed in the first comparison.

Switching Scheme
As shown in Figure 4, the operation of the switching scheme can be performed in five phases: sampling, the 1st comparison, the 2nd comparison, the 3rd to (N−1)th comparison, and the Nth comparison.
Sampling: In the sampling phase, the input signals are sampled on the top-plates of all capacitors via sampling switch, with the bottom-plates of the largest capacitors connecting to V ref and other capacitors to gnd.
The 1st comparison: After sampling, the sampling switches are turned off. The output voltages of the DAC capacitor array are found to be The comparator compares the sampling signals (V ip and V in ) and gets D 1 (MSB). No switching energy is consumed in the first comparison.
The 2nd comparison (level-shift-gnd): If D 1 = 1, the reference voltage of the largest capacitor in the positive capacitor array changes from V ref to gnd. If D 1 = 0, the reference voltage of the largest capacitor in the negative capacitor array becomes gnd. As a result, the voltage of the higher side is decreased by V ref /2, and the output voltages are found to be The 2nd comparison (level-shift-gnd): If D1 = 1, the reference voltage of the largest capacitor in the positive capacitor array changes from Vref to gnd. If D1 = 0, the reference voltage of the largest capacitor in the negative capacitor array becomes gnd. As a result, the voltage of the higher side is decreased by Vref/2, and the output voltages are found to be ( ) The comparator compares VDACP (2) with VDACN(2) and gets D2. Due to the closed-loop charge recycling method [16], there is no switching energy consumption in the second comparison.
The 3rd to (N−1)th comparison ("up" operation): According to the previous comparison results, the reference voltage of the corresponding capacitor in the lower voltage capacitor array is switched from gnd to Vref, while the other one (in the higher voltage capacitor array) remains unchanged. For example, in the third comparison, if D2 = 1, the The comparator compares V DACP (2) with V DACN (2) and gets D 2 . Due to the closedloop charge recycling method [16], there is no switching energy consumption in the second comparison.
The comparator compares V DACP (i) with V DACN (i) and gets D i . During the switching procedure, there is only one capacitor switch for each comparison, resulting in less switch- ing activity and lower energy. Based on the switching energy calculation method in [6], the switching energy of each comparison is found to be Nth comparison: In the Nth comparison, the reference voltage of the last capacitor in the lower side is switched from gnd to V cm while the other one (on the higher side) remains unchanged. The output voltages and switching energy are found to be The average switching energy of the switching scheme is derived as Figure 5 shows switching energy at each output code for different switching schemes. The average switching energy of the switching scheme used for 10-bit SAR ADC is 63.56 CV 2 re f . Compared with the conventional switching scheme [11], the used switching scheme [15] and Capacitor-Splitting [8], Set-and-down [10], and V cm -based [9] schemes reduce the switching energy by 95.34%, 37.48%, 81.26%, and 87.52%, respectively. Figure 6 presents the 500-run Monte Carlo simulation results of the proposed DAC switching scheme with unit capacitor mismatch of σ u /C u = 1%. The RMS DNL and the RMS INL of the proposed DAC switching scheme are 0.325 LSB and 0.326 LSB, respectively.

Automatic ON/OFF Comparator
A low-power two-stage full dynamic comparator is reported in [18]. In order to save more power consumption of the comparator, an automatic ON/OFF clock circuit is added to the comparator. As shown in Figure 7a, the comparator consists of automatic ON/OFF clock circuit, dynamic preamplifier stage, and dynamic latch stage. In the dynamic preamplifier stage, V DACP and V DACN are the output signals of the DAC capacitor array and are connected to the differential inputs of the comparator. AP and AN are differential outputs of the dynamic preamplifier stage. In the dynamic latch stage, COMP and COMN are the comparison results, which are obtained by AP, AN, and CCLK driving the latch. In the process of result latching, no power-to-ground current path is formed, so the comparator only has a dynamic power supply. The automatic ON/OFF clock circuit generates the clock for comparator operation. When the RST is high or P 10 + N 10 (P 10 and N 10 are the 10th comparison result that latched in SAR logic) is high, there is no clock output, the comparator is in the OFF state, and the comparator has no power consumption. Figure 7b shows the timing diagram of the comparator.  [11], red [8], blue [10], green [9], and magenta curves are switching energy.

Automatic ON/OFF Comparator
A low-power two-stage full dynamic comparator is reported in [18]. In order to save more power consumption of the comparator, an automatic ON/OFF clock circuit is added to the comparator. As shown in Figure 7a, the comparator consists of automatic ON/OFF clock circuit, dynamic preamplifier stage, and dynamic latch stage. In the dynamic preamplifier stage, VDACP and VDACN are the output signals of the DAC capacitor array and are connected to the differential inputs of the comparator. AP and AN are differential outputs of the dynamic preamplifier stage. In the dynamic latch stage, COMP and COMN are the comparison results, which are obtained by AP, AN, and CCLK driving the latch. In the process of result latching, no power-to-ground current path is formed, so the comparator switching energy (CV 2 ref ) Figure 5. Switching energy against output codes. The black [11], red [8], blue [10], green [9], and magenta curves are switching energy.

Automatic ON/OFF Comparator
A low-power two-stage full dynamic comparator is reported in [18]. In order to sa more power consumption of the comparator, an automatic ON/OFF clock circuit is add to the comparator. As shown in Figure 7a, the comparator consists of automatic ON/O clock circuit, dynamic preamplifier stage, and dynamic latch stage. In the dynamic pr amplifier stage, VDACP and VDACN are the output signals of the DAC capacitor array and a connected to the differential inputs of the comparator. AP and AN are differential outpu comparator is in the OFF state, and the comparator has no power consumption. Figure 7b shows the timing diagram of the comparator.

Automatic ON/OFF SAR Logic
As shown in Figure 8, the automatic ON/OFF SAR logic consists of an automatic ON/OFF clock circuit, a sequencer, and a data register. The sequencer is a shift register that shifts the set signal through a series of D flip-flops. The set signal is then used to activate the Latch in the data register. When the last D flip-flop in the sequencer is triggered, the sequencer will be reset and await the next conversion cycle. The data register is composed of dynamic latches, which can latch the differential outputs of the comparator and output differential data. Differential output makes DAC logic circuit simpler. The automatic ON/OFF clock circuit is used to provide the drive clock signal for the shift register. Drive clock is only ON while comparison results are being latched, thus reducing SAR logic power consumption. Figure 8b shows the timing diagram of the SAR logic.

Automatic ON/OFF SAR Logic
As shown in Figure 8, the automatic ON/OFF SAR logic consists of an automatic ON/OFF clock circuit, a sequencer, and a data register. The sequencer is a shift register that shifts the set signal through a series of D flip-flops. The set signal is then used to activate the Latch in the data register. When the last D flip-flop in the sequencer is triggered, the sequencer will be reset and await the next conversion cycle. The data register is composed of dynamic latches, which can latch the differential outputs of the comparator and output differential data. Differential output makes DAC logic circuit simpler. The automatic ON/OFF clock circuit is used to provide the drive clock signal for the shift register. Drive clock is only ON while comparison results are being latched, thus reducing SAR logic power consumption. Figure 8b shows the timing diagram of the SAR logic.

DAC Driver Circuit
As shown in Figure 9, each capacitor requires two reference voltages. The reference voltages of C 2 to C 9 capacitors are V ref and gnd, and the drive circuit can be realized by CMOS inverter. The reference voltage of C 1 capacitor is V cm and gnd, and the driving circuit adopts a hybrid structure of CMOS transmission gate and CMOS inverter circuit. Figure 10 illustrates the floorplan of the capacitor array DAC for a single side. Both sides have identical layout design. DAC capacitors and dummy capacitors are represented by squares (unit capacitors) in different colors. DAC capacitors are surrounded by dummy capacitors to minimize the proximity effects and second-order lithographic errors. Additionally, a common centroid layout is used to reduce parasitic effects.

DAC Driver Circuit
As shown in Figure 9, each capacitor requires two reference voltages. The reference voltages of C2 to C9 capacitors are Vref and gnd, and the drive circuit can be realized by CMOS inverter. The reference voltage of C1 capacitor is Vcm and gnd, and the driving circuit adopts a hybrid structure of CMOS transmission gate and CMOS inverter circuit.  Figure 9. DAC driver circuit. Figure 10 illustrates the floorplan of the capacitor array DAC for a single side. Both sides have identical layout design. DAC capacitors and dummy capacitors are represented by squares (unit capacitors) in different colors. DAC capacitors are surrounded by dummy capacitors to minimize the proximity effects and second-order lithographic errors. Additionally, a common centroid layout is used to reduce parasitic effects.  Figure 11 shows the chip micrograph of the ADC prototype fabricated in 180 nm CMOS process with a core area of 0.15 mm 2 (500 µm × 300 µm). Figure 12 shows the measurement environment. The power supply device provides power and reference voltage for the SAR ADC chip. The FPGA generates timing signals to control the work of SAR ADC chip. The signal generator generates a differential sinusoidal signal and connects to the analog signal input of the SAR ADC chip. The logic analyzer is connected to the digital signal output of the SAR ADC chip and collects the output data. The PC takes out the measured data from the logic analyzer and then analyzes various performance indicators of the chip. As shown in Figure 13, the signal-to-noise-and-distortion ratio (SNDR) is 45.15 dB, and the effective number of bits (ENOB) is 7.2 bit at 1.8 V supply and 1 kS/s sampling rate. The SAR ADC consumes 7.6 nW, and the calculated FoM is 51.7 fJ/conv.  Table 2 shows the performance comparison between the proposed ADC and other ADCs. Compared with another 180 nm ADC, the proposed ADC has a convincing performance. If the proposed SAR ADC uses the 65 nm process, it may have better performance. 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 D D D D D D 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 D D D D 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 4 3 1 4 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 4 2 3 4 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 D D D D 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 D D D D D D 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9   Figure 9. DAC driver circuit. Figure 10 illustrates the floorplan of the capacitor array DAC for a single side. Both sides have identical layout design. DAC capacitors and dummy capacitors are represented by squares (unit capacitors) in different colors. DAC capacitors are surrounded by dummy capacitors to minimize the proximity effects and second-order lithographic errors. Additionally, a common centroid layout is used to reduce parasitic effects.  Figure 11 shows the chip micrograph of the ADC prototype fabricated in 180 nm CMOS process with a core area of 0.15 mm 2 (500 µm × 300 µm). Figure 12 shows the measurement environment. The power supply device provides power and reference voltage for the SAR ADC chip. The FPGA generates timing signals to control the work of SAR ADC chip. The signal generator generates a differential sinusoidal signal and connects to the analog signal input of the SAR ADC chip. The logic analyzer is connected to the digital signal output of the SAR ADC chip and collects the output data. The PC takes out the measured data from the logic analyzer and then analyzes various performance indicators of the chip. As shown in Figure 13, the signal-to-noise-and-distortion ratio (SNDR) is 45.15 dB, and the effective number of bits (ENOB) is 7.2 bit at 1.8 V supply and 1 kS/s sampling rate. The SAR ADC consumes 7.6 nW, and the calculated FoM is 51.7 fJ/conv.  7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 D D D D D D 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 D D D D 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 4 3 1 4 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 4 2 3 4 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 5 D D D D 5 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9 9 8 8 8 8 7 7 6 D D D D D D 6 7 7 8 8 8 8 9 9 9 9 9 9 9 9 D D 9 9 9 9 9 9 9  Figure 11 shows the chip micrograph of the ADC prototype fabricated in 180 nm CMOS process with a core area of 0.15 mm 2 (500 µm × 300 µm). Figure 12 shows the measurement environment. The power supply device provides power and reference voltage for the SAR ADC chip. The FPGA generates timing signals to control the work of SAR ADC chip. The signal generator generates a differential sinusoidal signal and connects to the analog signal input of the SAR ADC chip. The logic analyzer is connected to the digital signal output of the SAR ADC chip and collects the output data. The PC takes out the measured data from the logic analyzer and then analyzes various performance indicators of the chip. As shown in Figure 13, the signal-to-noise-and-distortion ratio (SNDR) is 45.15 dB, and the effective number of bits (ENOB) is 7.2 bit at 1.8 V supply and 1 kS/s sampling rate. The SAR ADC consumes 7.6 nW, and the calculated FoM is 51.7 fJ/conv.-step. The Figure-of-Merit (FoM) was calculated from the following equation:

Conclusions
This paper has presented a low-power SAR ADC for biomedical applications. The ADC uses an energy-efficient, low-complexity switching scheme to reduce power consumption. Because of the top-plate sampling and level-shift-gnd operations, the switching scheme did not consume energy in the first and second comparisons. Thanks to the use of Vcm for the last capacitor, the total capacitance is reduced by half, so the energy consumption of DAC is also reduced. In addition, because of the automatic ON/OFF technology, the comparator and SAR logic only generate energy consumption during operation. The proposed SAR ADC achieves FoM of 51.7 fJ/conv.-step at 1.8 V supply and 1 KS/s sampling rate. If the ADC adopts a low-voltage design method, more energy consumption will be saved. The proposed low-power SAR ADC is suitable for biomedical applications.

Conclusions
This paper has presented a low-power SAR ADC for biomedical applications. The ADC uses an energy-efficient, low-complexity switching scheme to reduce power consumption. Because of the top-plate sampling and level-shift-gnd operations, the switching scheme did not consume energy in the first and second comparisons. Thanks to the use of V cm for the last capacitor, the total capacitance is reduced by half, so the energy consumption of DAC is also reduced. In addition, because of the automatic ON/OFF technology, the comparator and SAR logic only generate energy consumption during operation. The proposed SAR ADC achieves FoM of 51.7 fJ/conv.-step at 1.8 V supply and 1 KS/s sampling rate. If the ADC adopts a low-voltage design method, more energy consumption will be saved. The proposed low-power SAR ADC is suitable for biomedical applications.