Applying ZCT to Two-Phase Boost Converter with IGBT Switches Used

A zero-current-transition (ZCT) strategy is proposed herein. This strategy is applied to a two-phase boost converter with isolated gate bipolar transistors (IGBTs) used as main switches. However, IGBTs have a current tail during the switch-off interval. Consequently, the proposed constant-frequency ZCT strategy along with common-ground auxiliary switches is employed to decrease the switching loss generated by the current tail. Furthermore, the light-load efficiency can be upgraded by regulating the switch-off instants and switch-on times of the two auxiliary switches. Moreover, two phases are interleaved with one phase having a phase difference of 180° from the other phase, and controlled by a current-sharing controller so that the input current can be distributed between the two phases as evenly as possible. Moreover, only one current sensing circuit is required to obtain information on currents in the two main switches. Above all, the number of phases can be extended with easy control of the ZCT and current balance.


Introduction
In recent years, due to the impact of the energy crisis, power supply products must have several features, such as power saving, stability and small size, etc. To meet these features, switching power supply will become the trend in power supply development in the future. However, due to the parasitic inductance and parasitic capacitance of the power switch elements in the traditional switching power supply, the power switch will cause switching loss under operation [1]. In addition, if the insulated gate bipolar transistor (IGBT) is used as a power switch, the current tail during the turn-off period will increase the switching loss.
Based on the above, the literature [2][3][4] uses the resonant zero-current switching (ZCS) technique to reduce the switching loss due to hard switching, but the corresponding power switch must withstand extremely high resonant currents, thereby increasing the conduction loss. In addition, since the resonant inductor and the resonant capacitor have a fixed execution time, the ZCS technique requires the use of variable frequency control, so the filter is not easy to design. In the literature [5][6][7][8][9], ZCS techniques with pulse width modulation (PWM) are used. Although this PWM ZCS technique has improved the problem of increased conduction loss and difficulty in filter design, the power switch is still subjected to extremely high resonant inductor currents. In addition, there are many additional components used in [9].
To conquer the shortcomings of the PWM ZCS technique, the zero-current transition (ZCT) [10][11][12] can be realized by fixed frequency control and does not need to increase the current stress of the power switch, thereby reducing the conduction loss and making the filter design easy. In [12], there is a floating auxiliary switch used.
In the following, more papers with a ZCT turn-off are described. The literature [13] starts with the introduction of the conventional ZCT converter. The advantage of this circuit is that it can realize the ZCT turn-off of the main switch without increasing the voltage stress of the main switch, but the disadvantage is that the main switch is hard-switched during the turn-on period, increasing the current stress of the main switch, while the auxiliary switch is also hard-switched during the turn-on and -off period. In [14], a novel improvement is provided by putting a ZCT auxiliary circuit on the secondary side of the circuit, so that the main switch can achieve a ZCT turn-off, although the main switch has no additional current stress during the turn-on period, but on the contrary, the main switch has additional current stress during the turn-off period. The main switch in [15] has no additional current stress during the turn-on period, but the drawback is that the auxiliary switch is floating, which increases the design difficulty of the drive circuit to some extent. In [16], an upgraded method is used to direct the inductive energy that causes the auxiliary switch to have additional voltage stress to the output side through the transformer, and both the main switch and auxiliary switch can achieve a ZCT turn-off, which makes the efficiency improve effectively, but the demerit is that the circuit is complex and has too many switching elements, which increases the difficulty of circuit analysis. In [17], although the circuit is simple and there is no additional current stress on the main switch during the turn-on period, the disadvantage is that the voltage stress on the main switch and auxiliary switch is too large, which requires the use of high voltage withstanding IGBTs and hence increases the cost.
On the other hand, many power supply products nowadays take multiphase interleaved control [18][19][20] to increase the output power. However, the line impedance of each phase is not equal. Consequently, it is necessary to add current sharing control [21][22][23] to distribute the load current evenly in each phase. Furthermore, since the current sharing control should sample the current of each phase, a traditional multi-phase interleaved power supply should have a current sampling circuit for each phase to feedback the current signal of each phase so that the load current can be equally distributed in each phase.
In this paper, we propose a two-phase interleaved boost converter with main IGBT switches having the ZCT turn-on by using the proposed auxiliary circuits, along with the proposed current sensing technique. The basic operating principle and mathematical deduction for the proposed topology are described in detail, then its feasibility is evaluated by the IsSpice software, and finally, a physical prototype, with the FPGA chip utilized as a system control kernel, is provided to demonstrate its effectiveness. Figure 1 shows the proposed two-phase interleaved converter with a new zero current transition. Since this paper adopts the Interleaved PWM technique, the respective duty cycle of one phase differs by 180 • from that of the other and does not overlap with each other. Accordingly, the operating principle of the single-phase circuit will be analyzed.

Proposed Converter
For analysis convenience of analyzing the proposed converter in each operating state, the following assumptions are made first: (i) The active power switch and the passive power switch are ideal; (ii) the input current is constant and the input inductance is much larger than the resonance inductance, which can be considered as a constant current source; (iii) the output voltage is fixed and the output capacitance is much larger than the resonant capacitance, so it can be regarded as a constant voltage source and (iv) Both the capacitance and inductance have no parasitic resistance.
From the above assumptions, the single-phase equivalent circuit will be shown in Figure 2. For analysis convenience of analyzing the proposed converter in each operating state the following assumptions are made first: (i) The active power switch and the passive power switch are ideal; (ii) the input current is constant and the input inductance is much larger than the resonance inductance, which can be considered as a constant curren source; (iii) the output voltage is fixed and the output capacitance is much larger than the resonant capacitance, so it can be regarded as a constant voltage source and (iv) Both the capacitance and inductance have no parasitic resistance.
From the above assumptions, the single-phase equivalent circuit will be shown in Figure 2. Prior to the circuit analysis shown in Figure 2, the relevant component symbols are defined as follows: (i) Vo is the output DC voltage, vgm is the gate signal of the main switch Sm, vSm, is the voltage on the main switch, vga is the gate signal of the common-grounded auxiliary switch Sa, vSa is the voltage on the auxiliary switch, vDa is the voltage on the aux iliary diode Da, vDo is the voltage on the output diode Do, and vCr is the voltage on the resonant capacitor Cr and (ii) Iin is the DC current flowing through the input inductor, iSm is the current flowing through the main switch Sm, iSa is the current flowing through the auxiliary switch Sa, iDa is the current flowing through the auxiliary diode Da, iDo is the cur rent flowing through the output diode Do, and iLr is the current flowing through the reso nant inductor Lr. The internal diode Dsa is connected in parallel with Sa.  For analysis convenience of analyzing the proposed converter in each operating state the following assumptions are made first: (i) The active power switch and the passive power switch are ideal; (ii) the input current is constant and the input inductance is much larger than the resonance inductance, which can be considered as a constant current source; (iii) the output voltage is fixed and the output capacitance is much larger than the resonant capacitance, so it can be regarded as a constant voltage source and (iv) Both the capacitance and inductance have no parasitic resistance.
From the above assumptions, the single-phase equivalent circuit will be shown in Figure 2. Prior to the circuit analysis shown in Figure 2, the relevant component symbols are defined as follows: (i) Vo is the output DC voltage, vgm is the gate signal of the main switch Sm, vSm, is the voltage on the main switch, vga is the gate signal of the common-grounded auxiliary switch Sa, vSa is the voltage on the auxiliary switch, vDa is the voltage on the auxiliary diode Da, vDo is the voltage on the output diode Do, and vCr is the voltage on the resonant capacitor Cr and (ii) Iin is the DC current flowing through the input inductor, iSm is the current flowing through the main switch Sm, iSa is the current flowing through the auxiliary switch Sa, iDa is the current flowing through the auxiliary diode Da, iDo is the current flowing through the output diode Do, and iLr is the current flowing through the resonant inductor Lr. The internal diode Dsa is connected in parallel with Sa. Prior to the circuit analysis shown in Figure 2, the relevant component symbols are defined as follows: (i) V o is the output DC voltage, v gm is the gate signal of the main switch S m , v Sm , is the voltage on the main switch, v ga is the gate signal of the common-grounded auxiliary switch S a , v Sa is the voltage on the auxiliary switch, v Da is the voltage on the auxiliary diode D a , v Do is the voltage on the output diode D o , and v Cr is the voltage on the resonant capacitor C r and (ii) I in is the DC current flowing through the input inductor, i Sm is the current flowing through the main switch S m , i Sa is the current flowing through the auxiliary switch S a , i Da is the current flowing through the auxiliary diode D a , i Do is the current flowing through the output diode D o , and i Lr is the current flowing through the resonant inductor L r . The internal diode D sa is connected in parallel with S a .
According to the on/off situation of the switching elements and the state of the energy storage elements, the main operating waveforms of the converter, shown in Figure 3, can be divided into seven over one switching cycle. According to the on/off situation of the switching elements and the state of the energy storage elements, the main operating waveforms of the converter, shown in Figure 3, can be divided into seven over one switching cycle.         According to Figure 3, the following equations can be obtained as The time experienced in this state, called ∆t 1 , is where ∆t 2 is the time experienced in state 2, ∆t 3 is the time experienced in state 3, ∆t 4 is the time experienced in state 4, and D is the duty cycle. State 2 [t 1 ≤ t ≤ t 2 ]: As shown in Figures 3 and 5, when the time reaches t 1 , the auxiliary switch S a is turned on, and the output voltage V o , resonant inductor L r , and resonant capacitor C r form a resonant circuit. At the same time, the resonant capacitor voltage v Cr rises gradually from v Cr (t 0 ), and the resonant inductor current i Lr starts to fall from zero. Once the voltage v Cr rises to zero, the operating state proceeds to state 3. According to Figure 3, the following equations can be obtained as The time experienced in this state, called Δt1, is where Δt2 is the time experienced in state 2, Δt3 is the time experienced in state 3, Δt4 is the time experienced in state 4, and D is the duty cycle.
]: As shown in Figures 3 and 5, when the time reaches t1, the auxiliary switch Sa is turned on, and the output voltage Vo, resonant inductor Lr, and resonant capacitor Cr form a resonant circuit. At the same time, the resonant capacitor voltage vCr rises gradually from vCr(t0), and the resonant inductor current iLr starts to fall from zero. Once the voltage vCr rises to zero, the operating state proceeds to state 3. The initial conditions of this state are According to Figure 3, the following equations can be obtained as The time experienced in this state, called Δt2, is  The initial conditions of this state are According to Figure 3, the following equations can be obtained as The time experienced in this state, called ∆t 2 , is State 3 [t 2 ≤ t ≤ t 3 ]: As shown in Figures 3 and 5, when the time reaches t 2 , the resonant inductor L r and resonant capacitor C r resonate continuously, and the resonant capacitor voltage v Cr rises from zero, whereas the resonant inductor current i Lr decreases continuously. When the resonant capacitor voltage v Cr is equal to the output voltage V o , the resonant inductor current i Lr climbs upward from the reverse peak current. Once the resonant inductor current i Lr climbs to zero, the operating state enters state 4.
The initial conditions of this state are According to Figure 3, the following equations can be obtained to be The time experienced in this state, called ∆t 3 , is : As shown in Figures 3 and 6, when the time reaches t 3 , the auxiliary switch is cut off, and the resonant inductance L r and resonant capacitance C r continue to resonate, making the auxiliary diode conductive. At the same time, the resonant inductance current i Lr starts to rise. According to Kirchhoff's current law, it can be known that I in = i Sm + i Lr . As the resonant inductance current i Lr rises to the input current I in , the main switch current i Sm drops to zero. At this time, if the main switch is turned off, the ZCT of the main switch can be realized, and this state ends. The initial conditions of this state are Cr in Lr (6) According to Figure 3, the following equations can be obtained to be The time experienced in this state, called Δt3, is ]: As shown in Figures 3 and 6, when the time reaches t3, the auxiliary switch is cut off, and the resonant inductance Lr and resonant capacitance Cr continue to resonate, making the auxiliary diode conductive. At the same time, the resonant inductance current iLr starts to rise. According to Kirchhoff's current law, it can be known that As the resonant inductance current iLr rises to the input current Iin, the main switch current iSm drops to zero. At this time, if the main switch is turned off, the ZCT of the main switch can be realized, and this state ends. The initial conditions of this state are  The initial conditions of this state are According to Figure 3, the following equations can be obtained as The time experienced in this state, called ∆t 4 , is State 5 [t 4 ≤ t ≤ t 5 ]: As shown in Figures 3 and 7, when the time reaches t 4 , the main switch S m is cut off. At the same time, the resonant inductance L r and resonant capac-itance C r continue to resonate. According to Kirchhoff's current law, it can be known that I in = i Da = i Sa + i Lr . Since the resonant inductance current i Lr is greater than the input current I n , the internal diode of the auxiliary switch, called D Sa , is conductive. The moment the resonant inductance current i Lr drops to the input current I in , the operating state enters state 6.
]: As shown in Figures 3 and 7, when the time reaches t4, t switch Sm is cut off. At the same time, the resonant inductance Lr and resonant cap Cr continue to resonate. According to Kirchhoff's current law, it can be know Since the resonant inductance current iLr is greater than the in rent In, the internal diode of the auxiliary switch, called DSa, is conductive. The m the resonant inductance current iLr drops to the input current Iin, the operating stat state 6. The initial conditions of this state are in Lr ω According to Figure 3, the following equations can be obtained as ]: As shown in Figures 3 and 8 . The resonant inductor current iLr is than the input current In, thereby making the internal diode of the auxiliary switch DSa, cut off and the output diode Do conductive. As soon as the resonant inductor iLr drops to zero, the operating state enters state 7. The initial conditions of this state are According to Figure 3, the following equations can be obtained as The time experienced in this state, called ∆t 5 , is State 6 [t 5 ≤ t ≤ t 6 ]: As shown in Figures 3 and 8, when the time reaches t 5 , the resonant inductor L r and resonant capacitor C r resonate continuously, thus causing the resonant inductor current i Lr to drop from the input current I n . According to Kirchhoff's current law, it can be known that I in = i Do + i Lr . The resonant inductor current i Lr is smaller than the input current I n , thereby making the internal diode of the auxiliary switch, called D Sa , cut off and the output diode D o conductive. As soon as the resonant inductor current i Lr drops to zero, the operating state enters state 7.
Micromachines 2022, 13, x According to Figure 3, the following equations can be obtained as The time experienced in this state, called Δt6, is ]: As shown in Figures 3 and 9, when the time reaches t6, th nance of resonant inductor Lr and resonant capacitor Cr is over; the resonant induc rent iLr has dropped to zero, so the auxiliary diode Da is cut off, which is like the netization state of the input inductor of the traditional boost converter. According to Figure 3, the following equations can be obtained as The initial conditions of this state are According to Figure 3, the following equations can be obtained as The time experienced in this state, called ∆t 6 , is State 7 [t 6 ≤ t ≤ t 7 ]: As shown in Figures 3 and 9, when the time reaches t 6 , the resonance of resonant inductor L r and resonant capacitor C r is over; the resonant inductor current i Lr has dropped to zero, so the auxiliary diode D a is cut off, which is like the demagnetization state of the input inductor of the traditional boost converter. According to Figure 3, the following equations can be obtained as ]: As shown in Figures 3 and 9, when the time reaches t6, th nance of resonant inductor Lr and resonant capacitor Cr is over; the resonant induc rent iLr has dropped to zero, so the auxiliary diode Da is cut off, which is like the netization state of the input inductor of the traditional boost converter. According to Figure 3, the following equations can be obtained as According to Figure 3, the following equations can be obtained as The time experienced in this state, called ∆t 6 , is

Proposed Current Sharing Strategy
Since the proposed system uses the interleaved PWM technique, the two phases have a 180 • difference in their individual gate driving signals and do not overlap their individual duty cycles with each other. Accordingly, a new current sampling method is adopted herein. In this paper, we use a new current sampling method to obtain two-phase current signals with only one current sampling circuit, which reduces one current sampling device, one filter circuit, and one analog-to-digital converter (ADC). Figure 10 shows the proposed two-phase current sampling method, where the sampling device for the two-phase current, the main switch current of the first phase, and the main switch current of the second phase are shown. In this system, a current sampling resistor R c is connected in series with the emitters of the main switches of two phases. Based on the digital controller, the first-phase current is sampled from t 0 to t 1 time, and the second-phase current is sampled from t 2 to t 3 times so that the information of the two-phase current signals can be obtained.

Proposed Current Sharing Strategy
Since the proposed system uses the interleaved PWM technique, the two phase a 180° difference in their individual gate driving signals and do not overlap their in ual duty cycles with each other. Accordingly, a new current sampling method is ad herein. In this paper, we use a new current sampling method to obtain two-phase c signals with only one current sampling circuit, which reduces one current sampli vice, one filter circuit, and one analog-to-digital converter (ADC). Figure 10 sho proposed two-phase current sampling method, where the sampling device for th phase current, the main switch current of the first phase, and the main switch cur the second phase are shown. In this system, a current sampling resistor Rc is conne series with the emitters of the main switches of two phases. Based on the digital con the first-phase current is sampled from t0 to t1 time, and the second-phase current i pled from t2 to t3 times so that the information of the two-phase current signals obtained.

Design of Current Sensing Resistor Rc
Prior to this section, the system specifications will be given as shown in Table   Table 1. System specifications.

Design of Current Sensing Resistor R c
Prior to this section, the system specifications will be given as shown in Table 1. Since this converter operates in CCM from light load to rated load, the corresponding duty cycle D is shown as below: The input inductor current ripple ∆i Li1 can be obtained as follows: The maximum input inductor current I L1,max can be obtained as follows: 3.1.2. Current Sensing Resistance Figure 10a shows the isolated gate driver TLP-250 connected between gate G after resistor R 2 and emitter E of the IGBT, whereas Figure 10b shows the current sensing resistor R c for the two phases. From these two figures, it is noted that since the low-level output voltage of the gate driver is connected to point E, the current in the gate driver does not flow through R c , which will guarantee that the IGBT works in the saturation region with V CE(sat) smaller than 2.5 V, which is verified by experiment. The following will talk about how to obtain the value of R c .
Since the used current sensing resistor R c has the loss, this loss due to R c is set at 0.04% of the rated output power, that is, the power dissipated on R c is 400 mW. The current, due to the gate driver, does not flow through R c because the low-level output voltage of the gate driver is connected to point E.
According to Figure 10b, the rms value of the current flowing through R c is Based on (23), two 0.1 Ω resistors connected in parallel are used as the current sensing resistor, where each resistor has a power dissipation of 200 mW, corresponding to the prescribed power dissipation. Since the maximum current flowing through R c is equal to I L1,max , the maximum voltage on R c is 0.1285 V. In addition, the maximum input voltage of the ADC is 5 V. Therefore, the voltage gain of the differential amplifier is set at 20, and hence, the ratio of voltage to current is 1 V/1 A and the maximum voltage on R c is 2.57 V, corresponding to the ADC requirement.

Current Sharing Controller
In this paper, the average current method is used to make the input current evenly distributed between the two phases, as shown in Figure 11. For the average current method to be considered, the sampled current signals of two phases are averaged to generate the current sharing reference command I ref .
Sequentially, each phase current is subtracted from this reference command to generate the current error signal and then feeds this error signal to the corresponding current sharing compensator to obtain the required control force. After this, this control force is added with the voltage control force created from the voltage compensator to control the corresponding switch of each phase, so that current sharing, as well as output voltage stabilization, can be achieved.

of 23
subtracted from this reference command to generate the current error signal and then feeds this error signal to the corresponding current sharing compensator to obtain the required control force. After this, this control force is added with the voltage control force created from the voltage compensator to control the corresponding switch of each phase, so that current sharing, as well as output voltage stabilization, can be achieved.

Design of Resonant Components
This section introduces the resonant component design according to the given system specifications, the resonant inductors and resonant capacitors of two phases are designed. The system specifications are shown in Table 1. First, the on-time of the auxiliary switch should be given, and after this, the values of the resonant components will be calculated under the rated condition as the worst condition. Accordingly, the ZCT operation under the light condition can be guaranteed, and this can be verified by measured waveforms, to be seen later.
From Sec. 2, the turn-on time of the auxiliary switch is used to determine the resonance time. If the auxiliary switch conduction time is too long, it is easy to cause an excessive increase in conduction loss, whereas if the turn-on time of the auxiliary switch is less than the sum of the cut-off delay time Td(off) and falling time Tf of the IGBT, the resonance inductor Lr and the resonance capacitor Cr will resonate several times and affect the operation of the auxiliary circuit. According to Figure 12, the on-time of the auxiliary switch must be greater than the sum of Td(off) and Tf. Therefore, to reduce the effect of the resonance frequency on PWM switching, the resonance period is set between 0.05 times the switching period and 0.1 times the switching period, that is, the resonance period locates between 1 μs and 2 μs, so the turn-on time of the auxiliary switch is taken as 1.5 μs.

Design of Resonant Components
This section introduces the resonant component design according to the given system specifications, the resonant inductors and resonant capacitors of two phases are designed. The system specifications are shown in Table 1. First, the on-time of the auxiliary switch should be given, and after this, the values of the resonant components will be calculated under the rated condition as the worst condition. Accordingly, the ZCT operation under the light condition can be guaranteed, and this can be verified by measured waveforms, to be seen later.
From Sec. 2, the turn-on time of the auxiliary switch is used to determine the resonance time. If the auxiliary switch conduction time is too long, it is easy to cause an excessive increase in conduction loss, whereas if the turn-on time of the auxiliary switch is less than the sum of the cut-off delay time T d(off ) and falling time T f of the IGBT, the resonance inductor L r and the resonance capacitor C r will resonate several times and affect the operation of the auxiliary circuit. According to Figure 12, the on-time of the auxiliary switch must be greater than the sum of T d(off ) and T f . Therefore, to reduce the effect of the resonance frequency on PWM switching, the resonance period is set between 0.05 times the switching period and 0.1 times the switching period, that is, the resonance period locates between 1 µs and 2 µs, so the turn-on time of the auxiliary switch is taken as 1.5 µs.
than the sum of the cut-off delay time Td(off) and falling time Tf of the IGBT, the resonance inductor Lr and the resonance capacitor Cr will resonate several times and affect the operation of the auxiliary circuit. According to Figure 12, the on-time of the auxiliary switch must be greater than the sum of Td(off) and Tf. Therefore, to reduce the effect of the resonance frequency on PWM switching, the resonance period is set between 0.05 times the switching period and 0.1 times the switching period, that is, the resonance period locates between 1 μs and 2 μs, so the turn-on time of the auxiliary switch is taken as 1.5 μs. According to Figure 3, since the resonant inductor and resonant capacitor resonate with two times the turn-on time of the auxiliary switch, the resonant angular frequency can be obtained to be To ensure that the main switch can reach turn-off ZCT from light load to rated load, the peak current of the resonant inductor must be larger than the peak current of the input inductor, and when one phase is broken, the other phase must continue to operate. Therefore, the peak current of the resonant inductor is twice the peak current of the input inductor, and the resonant impedance can be obtained as As shown in Figure 3, the following equation can be approximately obtained to be v Cr (t 0 ) Substituting (22) and (25) By substituting (25) into (26) and (27), the values of the resonant inductor and resonant capacitor can be obtained to be As shown in Figure 3, the maximum voltage across the resonant capacitor is 2V o -v Cr(t 0 ) , i.e., 862 V. Therefore, the resonant capacitor takes a 1.5 kV Mylar capacitor, and the resonant inductor adopts a Sendust core manufactured by CHANGSUNG, with the model number CS270125, 18 turns, and the wire diameter No. 16 AWG.

System Configuration
In Figure 13, the main power stage is composed of a two-phase interleaved step-up converter with a ZCT auxiliary circuit, whereas the peripheral circuit includes a gate driver circuit, a voltage sampling circuit, a two-phase current sampling circuit and an analog-todigital converter; in the controller, the FPGA is used as the control kernel to realize the fully digital interleaved PWM control. The Cyclone II series FPGA chip, manufactured by Altera Co., has a product number of EP2C20F484C8.

Simulated and Measured Waveforms
The simulation shown in Figure 14 is based on the IsSpice software. In the following, the simulated and experimental results are obtained at rated load. Moreover, in Table 2, the part numbers used for the switches and diodes in the simulation and experiment can be configured according to the system specifications and the main operating waveforms.  Figure 15 shows the gate driving signals for main switches vgm1 and vgm2, and auxiliary switches vga1 and vga2. Figure 16 shows the gate driving signal for the phase-1 main switch Sm1, called vgm1, the voltage across Sm1, called vSm1, and the current flowing through Sm1, called iSm1. Figure 17 shows the zoom-in of Figure 16. Figure 18 shows the gate driving  Figure 13. System circuit configuration.

Simulated and Measured Waveforms
The simulation shown in Figure 14 is based on the IsSpice software. In the following, the simulated and experimental results are obtained at rated load. Moreover, in Table 2, the part numbers used for the switches and diodes in the simulation and experiment can be configured according to the system specifications and the main operating waveforms.  Figure 19 shows the zoom-in of Figure 18.       Figure 15 shows the gate driving signals for main switches v gm1 and v gm2 , and auxiliary switches v ga1 and v ga2 . Figure 16 shows the gate driving signal for the phase-1 main switch S m1 , called v gm1 , the voltage across S m1 , called v Sm1 , and the current flowing through S m1 , called i Sm1 . Figure 17 shows the zoom-in of Figure 16. Figure 18 shows the gate driving signal for the phase-1 auxiliary switch S a1 , called v ga1 , the voltage across S a1 , called v Sa1 , and the current flowing through S a1 , called i Sa1 . Figure 19 shows the zoom-in of Figure 18. Figure 20 shows the voltage on the resonant capacitor, called v Cr1 , and the current flowing through the resonant inductor, called i Lr1 .
Micromachines 2022, 13, x 14 of 23 signal for the phase-1 auxiliary switch Sa1, called vga1, the voltage across Sa1, called vSa1, and the current flowing through Sa1, called iSa1. Figure 19 shows the zoom-in of Figure 18.             Figure 21 shows the gate driving signal for the phase-2 main switch Sm2, called vgm2, the voltage across Sm2, called vSm2, and the current flowing through Sm2, called iSm2. Figure  22 shows the zoom-in of Figure 21. Figure 23 shows the gate driving signal for the phase-2 auxiliary switch Sa2, called vSa2, called vga2, the voltage across Sa2, called vSa2, and the current flowing through Sa2, called iSa2. Figure 24 shows the zoom-in of Figure 23. Figure 25 shows the voltage on the resonant capacitor, called vCr2, and the current flowing through the resonant inductor, called iLr2. Figure 26 shows the gate driving signals vgm1 and vgm2, and the resonant inductor currents iLr1 and iLr2.  Figure 21 shows the gate driving signal for the phase-2 main switch S m2 , called v gm2 , the voltage across S m2 , called v Sm2 , and the current flowing through S m2 , called i Sm2 . Figure 22 shows the zoom-in of Figure 21. Figure 23 shows the gate driving signal for the phase-2 auxiliary switch S a2 , called v Sa2 , called v ga2 , the voltage across S a2 , called v Sa2 , and the current flowing through S a2 , called i Sa2 . Figure 24 shows the zoom-in of Figure 23. Figure 25 shows the voltage on the resonant capacitor, called v Cr2 , and the current flowing through the resonant inductor, called i Lr2 . Figure 26 shows the gate driving signals v gm1 and v gm2 , and the resonant inductor currents i Lr1 and i Lr2 .  Figure 21 shows the gate driving signal for the phase-2 main switch Sm2, called vgm2, the voltage across Sm2, called vSm2, and the current flowing through Sm2, called iSm2. Figure  22 shows the zoom-in of Figure 21. Figure 23 shows the gate driving signal for the phase-2 auxiliary switch Sa2, called vSa2, called vga2, the voltage across Sa2, called vSa2, and the current flowing through Sa2, called iSa2. Figure 24 shows the zoom-in of Figure 23. Figure 25 shows the voltage on the resonant capacitor, called vCr2, and the current flowing through the resonant inductor, called iLr2. Figure 26 shows the gate driving signals vgm1 and vgm2, and the resonant inductor currents iLr1 and iLr2.

Waveform Comments
The simulated and experimental results are similar to some extent except for oscillation. From Figure 15, vgm2 is shifted by 180 degrees from vgm1 whereas vga2 is shifted by 180 degrees from vga1. Figure 17 shows Sm1 has turn-off ZCT. Figure 19 shows vSa1 and iSa1, corresponding to near ZCS. Figure 20 shows vCr1 and iLr1, also corresponding to Figure 3. Figure 22 shows Sm2 has turn-off ZCT. Figure 24 shows vSa2 and iSa2, corresponding to near ZCS. Figure 25 shows vCr2 and iLr2, also corresponding to Figure 3. Figure 26 shows iL2 is shifted by 180 degrees from iL2, the average values of the two currents are almost the same, meaning that the output current is almost distributed between the two phases.
In Figure 16 or Figure 21, there are four phenomena to be described. One is the current spike in iSm1 or iSm2 is due to the reverse recovery current of Do1 or Do1, and the voltage vSm1 or vSm2 during the turn-on period is smaller than the maximum on-voltage drop VCE(sat) of 2.5 V based on the STGP10NC60H datasheet, thereby making sure that Sm1 or Sm2 are operated in the saturation region. Another is that iSm1 or iSm2 will have a small increase when the voltage across Sm1 or Sm2 rises since the IGBT needs time to withdraw injected carriers at the emitter of the IGBT during the turn-off period. The other is that as Sa1 or Sa2 is on instantaneously, the corresponding Da1 or Da2 is on, so some of the currents in Sm1 or Sm2 will be shifted to Sa1 or Sa2, resulting in a current dip in current iSm1 or iSm2.
In Figure 18 or Figure 23, there are two ringing voltages on vSa1 or vSa2 to be described. One is that since the reverse recovery current of DSa1 or DSa2 will flow to the resonant path, the first ringing voltage on vSa1 or vSa2 will occur. The other is that when Sm1 or Sm2 turn on

Waveform Comments
The simulated and experimental results are similar to some extent except for oscillation. From Figure 15, v gm2 is shifted by 180 degrees from v gm1 whereas v ga2 is shifted by 180 degrees from v ga1 . Figure 17 shows S m1 has turn-off ZCT. Figure 19 shows v Sa1 and i Sa1 , corresponding to near ZCS. Figure 20 shows v Cr1 and i Lr1 , also corresponding to Figure 3. Figure 22 shows S m2 has turn-off ZCT. Figure 24 shows v Sa2 and i Sa2 , corresponding to near ZCS. Figure 25 shows v Cr2 and i Lr2 , also corresponding to Figure 3. Figure 26 shows i L2 is shifted by 180 degrees from i L2 , the average values of the two currents are almost the same, meaning that the output current is almost distributed between the two phases.
In Figure 16 or Figure 21, there are four phenomena to be described. One is the current spike in i Sm1 or i Sm2 is due to the reverse recovery current of D o1 or D o1 , and the voltage v Sm1 or v Sm2 during the turn-on period is smaller than the maximum on-voltage drop V CE(sat) of 2.5 V based on the STGP10NC60H datasheet, thereby making sure that S m1 or S m2 are operated in the saturation region. Another is that i Sm1 or i Sm2 will have a small increase when the voltage across S m1 or S m2 rises since the IGBT needs time to withdraw injected carriers at the emitter of the IGBT during the turn-off period. The other is that as S a1 or S a2 is on instantaneously, the corresponding D a1 or D a2 is on, so some of the currents in S m1 or S m2 will be shifted to S a1 or S a2 , resulting in a current dip in current i Sm1 or i Sm2 .
In Figure 18 or Figure 23, there are two ringing voltages on v Sa1 or v Sa2 to be described. One is that since the reverse recovery current of D Sa1 or D Sa2 will flow to the resonant path, the first ringing voltage on v Sa1 or v Sa2 will occur. The other is that when S m1 or S m2 turn on instantaneously, the reverse recovery current of D o1 or D o2 will flow to the resonant path through D a1 or D a2 , so the second ringing voltage on v Sa1 or v Sa2 will occur.
In Figure 20 or Figure 25, the peak value of the resonant inductor current is smaller than the designed value due to the presence of parasitic resistance in the actual circuit, and the peak value of the resonant capacitor voltage is larger than the designed value due to the tolerance of the resonant capacitance. From Figure 27, it is noted that at light load, the main switches S m1 and S m2 still have ZCT turn-off, corresponding to the requirements.
through Da1 or Da2, so the second ringing voltage on vSa1 or vSa2 will occur.
In Figure 20 or Figure 25, the peak value of the resonant inductor current is smaller than the designed value due to the presence of parasitic resistance in the actual circuit, and the peak value of the resonant capacitor voltage is larger than the designed value due to the tolerance of the resonant capacitance. From Figure 27, it is noted that at light load, the main switches Sm1 and Sm2 still have ZCT turn-off, corresponding to the requirements.  Figure 28 shows the waveforms of Sa1 under 25% load by not adjusting the on-time and off-triggering moment of Sa1. As can be seen from this figure, when the proposed converter is operated under a light load, the current flowing through Dsa1 is larger than that under a rated load. Therefore, the reverse recovery current of this diode is larger than that under a rated load, so a voltage spike on Sa1 is likely to be caused. Figure 29 shows the waveforms of Sa1 under 25% load by adjusting the on-time and off-triggering moment of Sa1. The peak value of the voltage spike will be reduced from 620 V to 460 V, thereby making the light-load efficiency improved. This description can be applied to phase-2 Sa2.  Figure 28 shows the waveforms of S a1 under 25% load by not adjusting the on-time and off-triggering moment of S a1 . As can be seen from this figure, when the proposed converter is operated under a light load, the current flowing through D sa1 is larger than that under a rated load. Therefore, the reverse recovery current of this diode is larger than that under a rated load, so a voltage spike on S a1 is likely to be caused. Figure 29 shows the waveforms of S a1 under 25% load by adjusting the on-time and off-triggering moment of S a1 . The peak value of the voltage spike will be reduced from 620 V to 460 V, thereby making the light-load efficiency improved. This description can be applied to phase-2 S a2 .  Figure 28 shows the waveforms of Sa1 under 25% load by not adjusti and off-triggering moment of Sa1. As can be seen from this figure, when converter is operated under a light load, the current flowing through Dsa that under a rated load. Therefore, the reverse recovery current of this diod that under a rated load, so a voltage spike on Sa1 is likely to be caused. Fi the waveforms of Sa1 under 25% load by adjusting the on-time and off-trigg of Sa1. The peak value of the voltage spike will be reduced from 620 V to making the light-load efficiency improved. This description can be applied   Figure 30 shows the efficiency measurement block diagram. From this figure, a cur rent sampling resistor is connected in series with the input current path. The input curren and input voltage are multiplied to obtain the input power. To measure the output powe an electronic load, named Prodigit 3254, is used to provide the required load current, an a digital voltmeter, named Fluke 8050 A, is used to measure the output voltage, which i multiplied by the load current to obtain the output power. Eventually, the output powe at each load is divided by the corresponding input power to obtain a curve of efficienc versus load current shown in Figure 31. In Figure 31, there are three cases to be compared Case 1 has the ZVT turn-on without the on-time and the off-triggering instant of Sa1 an Sa2 adjusted. Case 2 has the ZVT turn-on with the on-time and the off-triggering instant o Sa1 and Sa2 adjusted. Case 3 has no ZVT. From this figure, Case 2 has better light-loa efficiency than the other two. The rated load efficiencies for Case 1, Case 2 and Case 3 ar 96.3%, 96.4% and 94.8%, respectively. Since the power loss relevant to the tail current i quite difficult to estimate [24], we use the rated-load efficiencies for Case 3 and Case 1 t figure out the individual power losses of 54.8 W and 38.4 W, respectively, and then th power loss associated to the falling current can be approximately estimated out by th difference in power loss between these two cases, equal to 16.4 W.   Figure 30 shows the efficiency measurement block diagram. From this figure, a current sampling resistor is connected in series with the input current path. The input current and input voltage are multiplied to obtain the input power. To measure the output power, an electronic load, named Prodigit 3254, is used to provide the required load current, and a digital voltmeter, named Fluke 8050 A, is used to measure the output voltage, which is multiplied by the load current to obtain the output power. Eventually, the output power at each load is divided by the corresponding input power to obtain a curve of efficiency versus load current shown in Figure 31. In Figure 31, there are three cases to be compared. Case 1 has the ZVT turn-on without the on-time and the off-triggering instant of S a1 and S a2 adjusted. Case 2 has the ZVT turn-on with the on-time and the off-triggering instant of S a1 and S a2 adjusted. Case 3 has no ZVT. From this figure, Case 2 has better light-load efficiency than the other two. The rated load efficiencies for Case 1, Case 2 and Case 3 are 96.3%, 96.4% and 94.8%, respectively. Since the power loss relevant to the tail current is quite difficult to estimate [24], we use the rated-load efficiencies for Case 3 and Case 1 to figure out the individual power losses of 54.8 W and 38.4 W, respectively, and then the power loss associated to the falling current can be approximately estimated out by the difference in power loss between these two cases, equal to 16.4 W.  Figure 30 shows the efficiency measurement block diagram. From this figure, a cur rent sampling resistor is connected in series with the input current path. The input curren and input voltage are multiplied to obtain the input power. To measure the output power an electronic load, named Prodigit 3254, is used to provide the required load current, and a digital voltmeter, named Fluke 8050 A, is used to measure the output voltage, which i multiplied by the load current to obtain the output power. Eventually, the output powe at each load is divided by the corresponding input power to obtain a curve of efficienc versus load current shown in Figure 31. In Figure 31, there are three cases to be compared Case 1 has the ZVT turn-on without the on-time and the off-triggering instant of Sa1 and Sa2 adjusted. Case 2 has the ZVT turn-on with the on-time and the off-triggering instant o Sa1 and Sa2 adjusted. Case 3 has no ZVT. From this figure, Case 2 has better light-load efficiency than the other two. The rated load efficiencies for Case 1, Case 2 and Case 3 ar 96.3%, 96.4% and 94.8%, respectively. Since the power loss relevant to the tail current i quite difficult to estimate [24], we use the rated-load efficiencies for Case 3 and Case 1 t figure out the individual power losses of 54.8 W and 38.4 W, respectively, and then th power loss associated to the falling current can be approximately estimated out by th difference in power loss between these two cases, equal to 16.4 W.