A 100 KS/s 8–10-Bit Resolution-Reconfigurable SAR ADC for Biosensor Applications

A DAC switching scheme that combines energy efficiency and resolution reconfigurability is proposed. Compared with the conventional switching scheme, the proposed scheme achieves 93.8%, 96.1%, and 97.3% switching energy saving in 8-bit, 9-bit, and 10-bit modes, respectively. Based on the proposed switching scheme, an 8–10-bit resolution-reconfigurable SAR ADC for biosensor applications is designed. The ADC consists of resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, sampling switch, and the resolution-control SAR logic. Simulated in 180 nm CMOS process and 100 kS/s sampling rate, the ADC achieves the 46.80/53.89/60.14 dB signal-to-noise and distortion ratio (SNDR), the 55.22/62.51/73.09 dB spurious-free dynamic range (SFDR) and the 0.81/0.91/1.01 μW power consumption in 8/9/10-bit mode, respectively.


Introduction
In recent years, successive-approximation register (SAR) analogue-to-digital converters (ADCs) have been preferred for biosensor applications [1][2][3][4][5]. SAR ADC is based on a successive approximation algorithm, which is suitable for designing resolution-reconfigurable SAR ADCs [6][7][8]. Resolution-reconfigurable ADCs can choose the appropriate resolution according to the characteristics of the biomedical signal, thus reducing energy consumption. Recently, several energy-efficient DAC switching schemes have been developed to improve the power efficiency of DAC capacitor arrays [9][10][11]. Compared to a conventional switching scheme [12], capacitor splitting [9], set and down [10], and V cm -based [11] reduce the switching energy by 37.4%, 81.3%, and 87.5%, respectively. However, their switching energy doubles as the number of bits increases by one. Taking the V cm -based switching scheme as an example, the average switching energy of 8-bit, 9-bit and 10-bit is 42.2 CV 2 re f , 84.8 CV 2 re f and 170.2 CV 2 re f , respectively. In this paper, a DAC switching scheme that combines energy efficiency and resolution reconfigurability is proposed. The average switching energy of the proposed switching scheme for 8-bit, 9-bit, and 10-bit SAR ADCs is 21.2 CV 2 re f , 26.5 CV 2 re f , and 37.1 CV 2 re f , which amounts to a reduction of 93.8%, 96.1% and 97.3% in the switching energy compared with a conventional switching scheme [9]. Based on the proposed switching scheme, a 100 KS/s 8-10-bit resolution-reconfigurable SAR ADC for biosensor applications is designed and simulated. In order to reduce the on-resistance of the sampling switch and reduce the sampling error, the sampling switch adopts a bootstrap switch circuit [13]. A two-stage full dynamic comparator is used to achieve low power consumption [14]. To improve the performance of SAR logic, a dynamic logic unit is used [15]. Based on the SAR logic, we design a resolution control circuit for bit control. When the SAR ADC is operating in 8-bit or 9-bit resolutions, in order to save power, two or one dynamic logic units need to be skipped, respectively. The frequency range of various biomedical signals are shown in Table 1. The 100KS/s sampling rate can meet these biomedical signal sensing applications. This paper is organized as follows: Section 2 describes the ADC architecture and presents the techniques used to achieve resolution reconfigurability and low power; the simulated results and the comparison with the state of the art are provided in Section 3. The conclusion is drawn in Section 4. Figure 1 shows the architecture of the proposed 8-10-bit resolution-reconfigurable SAR ADC. It comprises a resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, sampling switch, and the resolution-control SAR logic.

Proposed SAR ADC Architecture
Micromachines 2022, 13, x FOR PEER REVIEW 2 of 25 on the SAR logic, we design a resolution control circuit for bit control. When the SAR ADC is operating in 8-bit or 9-bit resolutions, in order to save power, two or one dynamic logic units need to be skipped, respectively. The frequency range of various biomedical signals are shown in Table 1. The 100KS/s sampling rate can meet these biomedical signal sensing applications. This paper is organized as follows: Section 2 describes the ADC architecture and presents the techniques used to achieve resolution reconfigurability and low power; the simulated results and the comparison with the state of the art are provided in Section 3. The conclusion is drawn in Section 4.  Figure 1 shows the architecture of the proposed 8-10-bit resolution-reconfigurable SAR ADC. It comprises a resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, sampling switch, and the resolution-control SAR logic. Figure 1. Architecture of 8-10-bit resolution-reconfigurable SAR ADC.

Proposed DAC Switching Scheme
The proposed DAC switching scheme is similar to a Vcm-based switching scheme [11]. However, the proposed DAC has replaced the dummy capacitor with the C-2C capacitors, which add one bit of accuracy, and adds some switches (S1 and S2) to adjust the resolution. As shown in Table 2, resolutions of ADC are adjusted by S1 and S2. In the 8-bit mode, S1 and S2 are always opened (except in the sampling phase). For the 9-bit mode, S1 will be closed in the 3rd comparison, with S2 remaining open. For the 10-bit mode, S1 will be closed in the 3rd comparison and S2 will be closed in the 4th comparison. A special reference switching method, which is shown in Tables 3 and 4, is used for the references (RP2, RN2, RP3 and RN3) associated with switches S1 and S2. Table 3 shows the references of RP2 and RN2 for each phase in 9-bit and 10-bit modes. The references of RP2 and RN2 are determined by the results of the 1st comparison (D1) and the 2nd comparison (D2). Table 4

Proposed DAC Switching Scheme
The proposed DAC switching scheme is similar to a V cm -based switching scheme [11]. However, the proposed DAC has replaced the dummy capacitor with the C-2C capacitors, which add one bit of accuracy, and adds some switches (S1 and S2) to adjust the resolution. As shown in Table 2, resolutions of ADC are adjusted by S1 and S2. In the 8-bit mode, S1 and S2 are always opened (except in the sampling phase). For the 9-bit mode, S1 will be closed in the 3rd comparison, with S2 remaining open. For the 10-bit mode, S1 will be closed in the 3rd comparison and S2 will be closed in the 4th comparison. A special reference switching method, which is shown in Tables 3 and 4, is used for the references (R P2 , R N2 , R P3 and R N3 ) associated with switches S1 and S2. Table 3 shows the references of R P2 and R N2 for each phase in 9-bit and 10-bit modes. The references of R P2 and R N2 are determined by the results of the 1st comparison (D 1 ) and the 2nd comparison (D 2 ). Table 4 shows the references of R P3 and R N3 for each phase in 10-bit mode. R P3 and R N3 are determined by the results of the first comparison (D 1 ) and the 3rd comparison (D 3 ).  Table 3. R P2 and R N2 for each phase of 9-bit and 10-bit mode.
To explain the operation of the SAR ADC, the proposed switching scheme in the three modes is used as follows.

Proposed 8-Bit Mode Switching Scheme
The steps of the conversion process of 8-bit mode are illustrated in Figure 2. Initially, in the sampling phase, all switches are closed, and the reference voltage of all capacitors is set to V cm . The input voltage is sampled onto the top plates of the capacitors.
In the 1st comparison, all switches are opened, and the output voltage of the capacitor array is found to be Initially, in the sampling phase, all switches are closed, and the reference voltage of all capacitors is set to Vcm. The input voltage is sampled onto the top plates of the capacitors.
In the 1st comparison, all switches are opened, and the output voltage of the capacitor array is found to be ( ) ( ) The comparator compares the sampling signals (Vip and Vin) and obtains D1.
In the 2nd comparison, if D1 is 1, the reference voltage of RP1 is changed from Vcm to gnd, and RN1 is changed from Vcm to Vref.. If D1 is 0, the reference voltage of RP1 is changed from Vcm to Vref, and RN1 is changed from Vcm to gnd. The output voltage is found to be The comparator compares VP (2) with VN(2) and obtains D2. The comparator compares the sampling signals (V ip and V in ) and obtains D 1 .
In the 2nd comparison, if D 1 is 1, the reference voltage of R P1 is changed from V cm to gnd, and R N1 is changed from V cm to V ref .. If D 1 is 0, the reference voltage of R P1 is changed from V cm to V ref , and R N1 is changed from V cm to gnd. The output voltage is found to be The comparator compares V P (2) with V N (2) and obtains D 2 .
In the 3rd comparison, if D 2 is 1, the reference voltage of R P4 is changed from V cm to gnd, and R N4 is changed from V cm to V ref . If D 4 is 0, the reference voltage of R P4 is changed from V cm to V ref , and R N4 is changed from V cm to gnd. The output voltage is found to be The comparator compares V P (3) with V N (3) and obtains D 3 . From the 3rd comparison to the 8th comparison, the DAC performs V cm -based switching scheme [11].

Proposed 9-Bit Mode Switching Scheme
The steps of the conversion process of 9-bit mode are illustrated in Figure 3.  Figure 3. Proposed 9-bit mode switching scheme. From the sampling phase to the 2nd comparison, a conversion process of 9-bit mode is the same as that of 8-bit mode.
In the 3rd comparison, S1 is closed. If D 1 D 2 is 11, the reference voltage of R P2 is changed from V cm to gnd, and R N2 is changed from V cm to V ref . If D 1 D 2 is 00, the reference voltage of R P2 is changed from V cm to V ref , and R N2 is changed from V cm to gnd. If D 1 D 2 is 01 or 10, the reference voltage of R P2 and R N2 remains unchanged. The output voltage is shown in equation 3. The comparator compares V P (3) with V N (3) and obtains D 3 .
In the 4th comparison, if D 3 is 1, the reference voltage of R P4 is changed from V cm to gnd, and R N4 is changed from The comparator compares V P (4) with V N (4) and obtains D 4 . From the 4th comparison to the 9th comparison, the DAC performs a V cm -based switching scheme [11].

Proposed 10-Bit Mode Switching Scheme
The steps of the conversion process of 10-bit are illustrated in Figures 4 and 5. From the sampling phase to the 3rd comparison, the conversion process of 10-bit mode is the same as that of 9-bit mode.
In the 4th comparison, S2 is closed.
is 01 or 10, the reference voltage of R P3 and R N3 remains unchanged. The output voltage is found to be The comparator compares V P (4) with V N (4) and obtains D 4 . In the 5th comparison, if D 4 is 1, the reference voltage of R P4 is changed from V cm to gnd, and R N4 is changed from V cm to V ref . If D 4 is 0, the reference voltage of R P4 is changed from V cm to V ref , and R N4 is changed from V cm to gnd. The output voltage is found to be The comparator compares V P (5) with V N (5) and obtains D 5 . From the 5th comparison to the 10th comparison, the DAC performs a V cm -based switching scheme [11]. Because the large capacitor does not participate in the first and second comparisons, it is more energy-efficient than a V cm -based switching scheme.
Based on the switching energy calculation method in [9], the switching energy of different switching schemes is calculated and shown in Figure 6 and Table 5. Figure 6 shows switching energy at each output code for different switching schemes. Benefiting from the resolution-reconfigurable technology, the proposed switching scheme has lower switching energy in middle output codes for the 9-bit and 10-bit modes. As shown in Table 5 for the proposed switching scheme, the more bits, the more energy is saved; the scheme saves 96.1% and 97.3% of switching energy in 9-bit and 10-bit modes, respectively.     Figure 5. The 5th comparison diagram of the proposed 10-bit mode switching scheme.   [12], red [9], blue [10], green [11]and magenta curves in the three figures are switching energy.  [12], red [9], blue [10], green [11] and magenta curves in the three figures are switching energy..

Sampling Switch
In order to reduce the on-resistance of the sampling switch and reduce the sampling error, the sampling switch adopts a bootstrap switch circuit [13]. The voltage bootstrap sampling circuit is shown in Figure 8. When the "Sample" voltage is low, the transistors MS1 and MS3 are turned on, MS2 and MS4 are turned off, the voltage of node A is charged to V DD , and the "Sample_high" voltage is low. When the "Sample" voltage becomes high, the transistor MS1 is turned off, MS2 is turned on, MS3 is turned off, and MS4 is turned on; the voltage of node A is boosted to 2V DD by the capacitor C B , and the "Sample_high" voltage starts to increase. The "Sample_high" voltage boost expression is as follows: (c) Figure 6. Switching energy against output codes: (a) 8-bit; (b) 9-bit; (c) 10-bit. The black, red, blue, green and magenta curves in the three figures are switching energy from Ref. [12], [9], [10], [11] and this paper.   on; the voltage of node A is boosted to 2VDD by the capacitor CB, and the "Sampl voltage starts to increase. The "Sample_high" voltage boost expression is as follows C L is the parasitic capacitance. If C B is much larger than C L , the "Sample_high" voltage is raised to about twice V DD . Figure 9 illustrates the voltage bootstrap of the sampling switch. The FFT of the sampling switch is shown in Figure 10. The spurious-free dynamic range (SFDR) and the signal-to-noise-plus-distortion ratio (SNDR) of the sampling switch are 75.30 and 74.65 dB, respectively. CL is the parasitic capacitance. If CB is much larger than CL, the "Sample_high" voltage is raised to about twice VDD. Figure 9 illustrates the voltage bootstrap of the sampling switch. The FFT of the sampling switch is shown in Figure 10. The spurious-free dynamic range (SFDR) and the signal-tonoise-plus-distortion ratio (SNDR) of the sampling switch are 75.30 and 74.65 dB, respectively.

Comparator
To decrease the power consumption of the comparator, a two-stage full dynamic comparator [14] is used. Figure 11 shows the schematic diagram of the comparator. The first stage is the dynamic preamplifier stage, and V P and V N are the output signals of the capacitor array DAC, connected to the differential input of the comparator. AN and AP are differential outputs of the dynamic preamplifier stage. The second stage is the dynamic latch stage, which is responsible for the two-stage amplification and the result latch, and OUTP and OUTN are the comparison results.

Comparator
To decrease the power consumption of the comparator, a two-stage full dynamic comparator [14] is used. Figure 11 shows the schematic diagram of the comparator. The first stage is the dynamic preamplifier stage, and VP and VN are the output signals of the capacitor array DAC, connected to the differential input of the comparator. AN and AP are differential outputs of the dynamic preamplifier stage. The second stage is the If SP or SN rises to the threshold voltage, M7 or M8 will be turned on, positive feedback will start to work, and one of SP and SN quickly rises to high and the other pulls low to complete the latching of the comparison result. Since the dynamic comparator does not form a power-to-ground path when operating, the comparator has only dynamic power. The transient simulation of the comparator is shown in Figure 12. Figure 13 shows the Monte Carlo simulations that are performed to observe the effect of mismatches and process variations on offset voltage. Offset voltage has a mean value of −18.053 µV with the standard deviation (SD) of 1.21052 mV. If SP or SN rises to the threshold voltage, M7 or M8 will be turned on, positive feedback will start to work, and one of SP and SN quickly rises to high and the other pulls low to complete the latching of the comparison result. Since the dynamic comparator does not form a power-to-ground path when operating, the comparator has only dynamic power. The transient simulation of the comparator is shown in Figure 12. Figure

SAR Control Logic
To improve the performance of SAR logic, a dynamic logic unit is used [15]. As shown in Figure 14, the SAR logic is composed of dynamic logic units, one by one. The dynamic logic unit has both a shift function and a function of storing comparison results, which saves many transistors compared to conventional shift registers. The 10-bit SAR logic has 10 dynamic logic units. When the SAR ADC is operating in 8-bit or 9-bit resolutions, in order to save power, two or one dynamic logic units need to be skipped, respectively. As shown in Figure 15, a resolution control circuit is added to SAR logic. The resolution of SAR logic is controlled by MO1 and MO2. Different resolutions will form different circuit paths. The resolution settings are shown in Table 6.

SAR Control Logic
To improve the performance of SAR logic, a dynamic logic unit is used [15]. As shown in Figure 14, the SAR logic is composed of dynamic logic units, one by one. The dynamic logic unit has both a shift function and a function of storing comparison results, which saves many transistors compared to conventional shift registers. The 10-bit SAR logic has 10 dynamic logic units. When the SAR ADC is operating in 8-bit or 9-bit resolutions, in order to save power, two or one dynamic logic units need to be skipped, respectively. As shown in Figure 15, a resolution control circuit is added to SAR logic. The resolution of SAR logic is controlled by MO1 and MO2. Different resolutions will form different circuit paths. The resolution settings are shown in Table 6.

SAR Control Logic
To improve the performance of SAR logic, a dynamic logic unit is used [15]. As shown in Figure 14, the SAR logic is composed of dynamic logic units, one by one. The dynamic logic unit has both a shift function and a function of storing comparison results, which saves many transistors compared to conventional shift registers. The 10-bit SAR logic has 10 dynamic logic units. When the SAR ADC is operating in 8-bit or 9-bit resolutions, in order to save power, two or one dynamic logic units need to be skipped, respectively. As shown in Figure 15, a resolution control circuit is added to SAR logic. The resolution of SAR logic is controlled by MO1 and MO2. Different resolutions will form different circuit paths. The resolution settings are shown in Table 6. (b) Figure 14. SAR based on dynamic logic.  Figure 15a shows the 8-bit mode work diagram of SAR control logic. When MO1 = 1 and MO2 = 0, the circuit is set to 8-bit operating mode, the transmission gate TG1 is turned on, the AND gates AND1 and AND2 are turned off, and the transmission gates TG2 and TG3 are turned off. Then, the output Q 1 of the first dynamic logic unit is directly connected to the input D 4 of the fourth dynamic logic unit; the second and third dynamic logic units are skipped. Figure 15b shows the 9-bit mode work diagram of SAR control logic. When MO1 = 0 and MO2 = 1, the circuit is set to 9-bit operating mode, AND1 and TG2 are turned on, and AND2, TG1, and TG3 are turned off. Then, the output Q 2 of the second dynamic logic unit is directly connected to the input D 4 of the fourth dynamic logic unit; the third dynamic logic unit is skipped. Figure 15c shows the 10-bit mode work diagram of SAR control logic. When MO1 = 0 and MO2 = 0, the circuit is set to 10-bit operating mode, AND1, AND2 and TG3 are turned on, and TG1 and TG2 are turned off. In this case, no dynamic logic cells are skipped. Dynamic logic unit (c) Figure 15. SAR control logic with bit control circuit: (a) 8-bit mode; (b) 9-bit mode; (c) 10-bit mode.

Results
The proposed ADC was designed and post-simulated using 180 nm CMOS technology. Figure 16 shows the layout of the ADC with a total area of 360 µm × 325 µm. Figure 17 shows the FFT spectrum of the proposed ADC in 8-bit, 9-bit, and 10-bit modes with the 1.8 V full swing inputs at 46.243 kHz and the sampling rate at 100 kS/s; the ADC achieves the 46.80/53.89/60.14 dB signal-to-noise and distortion ratio (SNDR) and 55.22/62.51/73.09 dB spurious-free dynamic range (SFDR), respectively. Figure 18 shows the SNDR and SFDR of the proposed SAR ADC with respect to the input frequency. Figure 19 shows the SNDR and SFDR of the proposed SAR ADC with respect to the sampling frequency. The proposed ADC consumes 0.81/0.91/1.01 µW corresponding to the 8/9/10-bit mode, respectively. Figure 20 shows the power breakdown of the ADC.   Table 7 compares the proposed ADC with other ADCs [16][17][18][19]. As shown in Table 7, the performance of the proposed ADC is still competitive when it is implemented in 0.

Conclusions
In this paper, a reconfigurable 8-10-bit SAR ADC with an energy-efficient DAC switching scheme for biosensor applications is presented. Several techniques are used to enable the reconfiguration. Simulated with a 180 nm CMOS process and 100 kS/s sampling  Table 7 compares the proposed ADC with other ADCs [16][17][18][19]. As shown in Table 7, the performance of the proposed ADC is still competitive when it is implemented in 0.18 µm 1.8 V CMOS process. The Figure-of-Merit (FoM) was calculated from the following equation:

Conclusions
In this paper, a reconfigurable 8-10-bit SAR ADC with an energy-efficient DAC switching scheme for biosensor applications is presented. Several techniques are used to enable the reconfiguration. Simulated with a 180 nm CMOS process and 100 kS/s sampling rate,