An Inductorless Gain-Controllable Wideband LNA Based on CCCIIs

In this paper, an inductorless and gain-controllable 0.5~2.5 GHz wideband low noise amplifier (LNA) based on second generation current controlled current conveyors (CCCIIs) is presented. The proposed wideband LNA utilizes CCCIIs as building blocks to implement the amplifier stage and impedance matching stage. By varying the DC biasing current of the CCCII, the voltage gain of the proposed LNA is controllable in the range of 1~18 dB. In the frequency range of 0.5~2.5 GHz, the post-layout simulation results show that the proposed LNA has a typical voltage gain S21 of 12.6 dB with a gain ripple of ±1.5 dB, an input and output return loss (S11 and S22) of, respectively, −21.4 dB to −16.6 dB and −18.6 dB to −10.6 dB, and a high reverse isolation S12 of −65.2 dB to −39.5 dB. A noise figure of 4.05~4.35 dB is obtained across the whole band, and the input third-order intercept point (IIP3) is −2.5 dBm at 1.5 GHz. Using a 0.18 μm RF CMOS technology, the LNA occupies an active chip area of only 0.096 mm2 with a power consumption of 12.0 mW.


Introduction
In the last few years, in the software-defined and multi-standard wireless communication systems, a radio frequency (RF) transceiver must be able to support several applications simultaneously, such as 3G/4G/5G mobile communication network, wireless local area network (WLAN), wireless sensor network (WSN), ZigBee (IEEE 802. 15.4), and many others [1][2][3][4]. Therefore, the research of the wideband RF transceiver front-end is significant and requires the research of RF circuits, whose impedances are matched over wide bands and whose frequency characteristics are stable over several GHz.
As the first active block after the antenna, the wideband LNA constitutes one of the essential elements in a wideband RF front-end [5,6]. The most important parameters of wideband LNA are voltage gain, noise figure (NF), bandwidth, linearity, impedance matching, power consumption, and chip area. The goals in wideband LNA design include providing moderate to high gain with good linearity, minimizing its noise figure to enhance the sensitivity of a receiver, and establishing wideband input/output impedance matching to reduce the return loss. The additional constraints of low power consumption and small chip area are imposed in portable systems.
In the published literature, various wideband LNA circuit techniques in submicron technologies have been proposed, such as a filter matching network amplifier, distributed amplifier, feed-forward noise canceling amplifier, and resistive shunt feedback amplifier. The filter matching network amplifier can consume a small amount of power and achieve wideband input impedance matching. However, the utilization of the filter at the input needs a great deal of inductor components [7][8][9]. The distributed amplifier is usually used to improve voltage gain at high frequency and therefore can extend the bandwidth, which has the inherent advantages of temperature-insensitive wideband input/output impedance matching and wideband voltage gain, but it dissipates a large chip area owing to the cascade of several stages [10,11]. The feed-forward noise canceling amplifier has been proposed to break the trade-off between input impedance matching and noise figure. However, its bandwidth is limited without the use of the inductor components [12,13]. The resistive shunt feedback amplifier can improve gain flatness and provide wideband input impedance matching, but it is difficult to satisfy noise figure and voltage gain requirements simultaneously [14,15].
As can be seen from the above techniques, in the design of wideband LNAs, the inductor components are extensively used to design impedance matching circuits, resonator networks and to widen the −3 dB bandwidth. However, the on-chip inductor components are large in size and cannot be converted easily from one technology to the next. The on-chip inductor components can result in a significant increase in the chip area and therefore the implementation cost. On the other hand, the feasibility of a wideband LNA to multi-mode and multi-standard is not only dependent on its bandwidth, it should also be able to support variable signal gain according to necessity. For example, when the linearity requirement is more important, a moderate gain is required because the linearity is usually inversely proportional to the gain. When the receiver's NF is required for good performance, the LNA needs to provide high gain to decrease noise contributions of the latter stages. The wideband LNA should be gain-controllable so that it can moderate gain amplification of the strong signals and high gain amplification of the weak signals.
In this paper, a new design for the inductorless gain-controllable wideband LNA using second generation current controlled current conveyors (CCCIIs) has been presented and simulated in a 0.18 µm RF CMOS technology. For the realization of this LNA, three different CCCIIs, as the main building blocks, which are symbolized CCCII 1 to CCCII 3, can provide voltage signal amplification and wideband output impedance matching. Compared to other wideband LNA designs, this kind of LNA can exhibit a smaller chip area, a wider gain-controllable range, and a good high frequency performance. This paper is organized as follows. In Section 2, the operation principle and some RF applications of current conveyor are discussed, then, the design schematic of a new LNA based on CCCIIs is analyzed. In Section 3, the post-layout simulation results of the proposed wideband LNA are introduced, meanwhile, we present comparisons with the recent works to show the advantages of the new LNA. Finally, a conclusion on this LNA is given in Section 4.

Current Conveyor Principle of Operation
The current conveyors (CCs) can be used with the other active/passive components in a specific circuit configuration to implement many analogue signal functions [16,17]. Usually, CCs simplify analogue circuit design to implement functions, such as impedance converters, filters, gyrators, inductances, oscillators, and operational amplifiers, etc. In the last few years, CCs have also received much attention for their use as RF basic building blocks [18,19]. The advantages of using CCs in RF circuit design are that they do not require inductor components to make the impedance matching circuit and that the voltage gain can be made controllable by only varying a DC biasing current.
In this paper, the use of second-generation current conveyor (CCII) to implement the wideband RF LNA has been proposed. The CCII is an active device comprised of the three ports, denoted port X, port Y, and port Z. Far from being ideal in their operation, the three ports of the CCII are beset by many parasitic elements, represented by the impedances Z X (R X in series with L X ), Z Y (R Y in series with C Y ), and Z Z (R Z in series with C Z ) at ports X, Y, and Z, respectively. Here, the Z Y and Z Z are impedances with very high values. While α(s) and β(s) represent the unity current (from port X to port Z) and voltage (from port Y to port X) transfer functions, ideally α(s) and β(s) are equal to 1. As shown in Figure 1, the value of these impedances, in particular Z X (with a very small value), can be changed by varying the DC biasing current I o of the conveyor, giving rise to the concept of second generation current controlled current conveyor (CCCII). voltage (from port Y to port X) transfer functions, ideally (s)  and (s)  are equal to 1. As shown in Figure 1, the value of these impedances, in particular ZX (with a very small value), can be changed by varying the DC biasing current Io of the conveyor, giving rise to the concept of second generation current controlled current conveyor (CCCII).
The CCCII acts as a current follower (between port X and port Z), a voltage follower (between port Y and port X), and a transconductor (between port Z and port Y). The possibility of controlling ZX (mainly consists of the parasitic resistance RX) using the DC biasing current Io, has made it to extend the applications of CCCIIs to the domain of controlled electronic functions.

The CCCII-Based LNA Principle of Operation
The CCCII is an increasingly popular building block for RF functions [20][21][22]. The CCCII can be used to design a gain-controllable LNA, the gain of which can be controlled by the DC biasing current Io. For the realization of this LNA, three different CCCIIs, as the main building blocks, which are symbolized as CCCII 1 to CCCII 3, can provide voltage signal amplification and wideband output impedance matching when connected, as shown in Figure 2. The current conveyor CCCII 1 converts the input voltage signal into a current signal, the connection of the two current conveyors, CCCII 1 and CCCII 2, amplify this current signal, and the current conveyor CCCII 2 converts the amplified current signal into the output voltage signal. Besides, the current conveyor CCCII 3 is the Z-match block on the output of the LNA, which adjusts the output impedance of the LNA to an ideal value.
The input voltage signal Vin(t) is provided at port Y1 of the current conveyor CCCII 1. Port Z1 of current conveyor CCCII 1 and port X2 of the current conveyor CCCII 2 are connected to each other, and the output voltage signal V'out(t) is tapped at this common connection. Assuming ZX1 and ZX2 to be purely resistive in nature (as LX1 and LX2 are the negligible parasitic inductances), with RX1 and RX2, Vin(t) is first converted by RX1 into IX1(t), which is given by The governing equation of the CCCII can be given in matrix form as: The CCCII acts as a current follower (between port X and port Z), a voltage follower (between port Y and port X), and a transconductor (between port Z and port Y). The possibility of controlling Z X (mainly consists of the parasitic resistance R X ) using the DC biasing current I o , has made it to extend the applications of CCCIIs to the domain of controlled electronic functions.

The CCCII-Based LNA Principle of Operation
The CCCII is an increasingly popular building block for RF functions [20][21][22]. The CCCII can be used to design a gain-controllable LNA, the gain of which can be controlled by the DC biasing current I o . For the realization of this LNA, three different CCCIIs, as the main building blocks, which are symbolized as CCCII 1 to CCCII 3, can provide voltage signal amplification and wideband output impedance matching when connected, as shown in Figure 2. The current conveyor CCCII 1 converts the input voltage signal into a current signal, the connection of the two current conveyors, CCCII 1 and CCCII 2, amplify this current signal, and the current conveyor CCCII 2 converts the amplified current signal into the output voltage signal. Besides, the current conveyor CCCII 3 is the Z-match block on the output of the LNA, which adjusts the output impedance of the LNA to an ideal value.
Micromachines 2022, 13, 1832 4 of 12 IX1(t) is copied to port Z1 as IZ1(t) (as to the current conveyor CCCII 1 between its port X1 and port Z1 is a current follower). Because of the connection of the two current conveyors CCCII 1 and CCCII 2, this current signal IZ1 comes into port X2 of the current conveyor CCCII 2. Therefore, the current signal IX1 = IZ1 = IX2 can be converted to a voltage signal owing to the parasitic resistance RX2 of CCCII 2. The resulting output voltage signal V'out(t) is given by In a typical CCCII operation, the parasitic resistance RX at port X is inversely proportional to the DC biasing current Io of the current conveyor, which is the fundamental property of the CCCII [20]. Then, the voltage gain (G) of the designed LNA is given by The input voltage signal V in (t) is provided at port Y 1 of the current conveyor CCCII 1. Port Z 1 of current conveyor CCCII 1 and port X 2 of the current conveyor CCCII 2 are connected to each other, and the output voltage signal V out (t) is tapped at this common connection. Assuming Z X1 and Z X2 to be purely resistive in nature (as L X1 and L X2 are the negligible parasitic inductances), with R X1 and R X2 , V in (t) is first converted by R X1 into I X1 (t), which is given by I X1 (t) is copied to port Z 1 as I Z1 (t) (as to the current conveyor CCCII 1 between its port X 1 and port Z 1 is a current follower). Because of the connection of the two current conveyors CCCII 1 and CCCII 2, this current signal I Z1 comes into port X 2 of the current conveyor CCCII 2. Therefore, the current signal I X1 = I Z1 = I X2 can be converted to a voltage signal owing to the parasitic resistance R X2 of CCCII 2. The resulting output voltage signal V out (t) is given by In a typical CCCII operation, the parasitic resistance R X at port X is inversely proportional to the DC biasing current I o of the current conveyor, which is the fundamental property of the CCCII [20]. Then, the voltage gain (G) of the designed LNA is given by where R x1 and R x2 represent the parasitic resistances at port X of the corresponding current conveyor and I o1 and I o2 are their respective DC biasing currents. Under a certain DC biasing current I o2 range condition, the inverse relationship of voltage gain G to DC biasing current I o2 enables higher voltage gain at lower DC biasing current and, thus, at lower power consumption.

The CCCII-Based LNA Circuit Design
One of the base demands in the wideband RF LNA design is to have 50 Ohm input impedance matching [5]. According to the schematic as shown in Figure 2, the input signal is fed at port Y 1 of CCCII 1, at which intrinsic impedance Z Y1 (R Y1 in series with C Y ) at port Y 1 is of some tens or hundreds of kOhm. However, port X 1 of CCCII 1 has impedance R X1 lower than some hundreds of Ohm. On the other hand, the impedance R X1 can be reduced to 50 Ohm for higher values of the DC biasing current I o1 . Hence, the input signal is changed from port Y 1 to port X 1 . The following optimization of the circuit architecture leads to the schematic of the proposed CCCII-based LNA as presented in Figure 3. As can be seen from Figure 3, the proposed LNA utilizes two simplified class A CCCIIs [23] as building blocks to implement the amplifier stage. The current conveyor CCCII 1 consists of an input common gate gain stage MA1 and the other current mirror transistors M1~M5, and the current conveyor CCCII 2 consists of a source follower stage MA2-MA3 and the other current mirror transistors M6~M10. The output of the input transistor MA1 is connected to the input of the source follower MA2. Note that the core of the  Figure 3. The schematic of the proposed CCCII-based LNA.
As can be seen from Figure 3, the proposed LNA utilizes two simplified class A CCCIIs [23] as building blocks to implement the amplifier stage. The current conveyor CCCII 1 consists of an input common gate gain stage M A1 and the other current mirror transistors M 1~M5 , and the current conveyor CCCII 2 consists of a source follower stage M A2 -M A3 and the other current mirror transistors M 6~M10 . The output of the input transistor M A1 is connected to the input of the source follower M A2 . Note that the core of the proposed LNA comprises only three NMOS transistors (M A1~MA3 ) in its signal path, thereby allowing for a higher bandwidth to be obtained and improving the noise performance. The current sources I o1 and I o2 are used to bias the main NMOS transistors M A1 and M A2 -M A3 , as explained later, to adjust the voltage gain and to match the input impedance without the inductor components.
Based on a first order analysis in the wideband operation mode of Figure 3, a voltage gain can be given by where C T is the total parasitic capacitance at the output node of port Z 1 with the input node of port X 2 and port Y 3 , while g m1 and g m2 are the transconductances of M A1 and M A2 , respectively. This transfer function obtains a single dominant pole frequency, which approximately determines the amplifier bandwidth by And the DC voltage gain approximately by At the low frequency band, the input impedance can be approximately described by Equations (6) and (7) show that a compromise on g m1 and g m2 , hence on the transistor sizes, as well as the DC biasing currents I o1 and I o2 of M A1 and M A2 , respectively, is necessary to optimize voltage gain and bandwidth. As can be seen, I o1 through g m1 affects the gain but has a little effect on the bandwidth, whereas I o2 controls both gain and bandwidth through g m2 . Therefore, varying I o2 , g m2 can be varied and the gain bandwidth product can be suitably adjusted. Increasing I o1 boosts the gain up again, but should be optimized to keep the power consumption sufficiently low. Under a certain DC biasing current I o2 range condition, the inverse relationship of voltage gain G to DC biasing current I o2 enables higher gain at lower DC biasing current and, therefore, at lower power consumption. Meanwhile, without the need of an LC matching network, Equation (8) indicates Z in can be matched to the source impedance (50 Ohm) through I o1 . From Figure 3, the proposed wideband LNA is an inductorless circuit, its chip area is smaller than the most other LNAs.
In Figure 3, the number of components in the signal chain is low: only three NMOS transistors M A1~MA3 . The main noise sources of the proposed LNA are contributed by the input NMOS transistor M A1 . When neglecting the parasitic capacitances and the noise of I o1 and I o2 , the noise figure of the LNA is approximately given by The excess noise factor γ is a constant that depends on the transistor size, and g m5 represents the transconductance of M 5 . As shown from Equation (9), the noise figure decreases when g m1 is increased. It can be achieved by increasing the transistor size of M A1 or the DC biasing current I o1 .

The Output Impedance Matching Design
In Figure 2, the Z-match block on the output is the impedance conversion circuit, which uses a translinear CCCII in the voltage follower mode to adjust the output impedance of the LNA to an ideal value. This design makes the output impedance of the LNA fully independent of its gain. In Figure 3, the core of translinear CCCII is composed of NMOS transistors (M C2 and M C4 ) and PMOS transistors (M C1 and M C3 ) as a translinear loop. At the same time, the transistors M C6 and M C4 , respectively, M C5 and M C3 , implement the other feedback loops to adjust the output impedance at port X 3 of the conveyor CCCII 3. The DC biasing current I o1 is copied to the required branches using current mirror transistors M 1 and M 11 -M 12 . The signal to be adapted, V out , is fed at port Y 3 of the current conveyor CCCII 3 (V out = V Y3 ), which can be considered an open circuit since its intrinsic resistance, R Y3 , is very high. The output is tapped at port X 3 of the current conveyor CCCII 3 (V out = V X3 ). The voltage transfer function β(s) (ideally equal to 1) of the voltage follower mode is The output impedance, at port X 3 of the conveyor CCCII 3, consists of resistance R X3 in series with a negligible parasitic inductance L X3 . By changing the DC biasing current I o1 of the conveyor, different resistance R X3 values can be obtained.
As can be seen in Figure 3, the CCCII-based output impedance matching circuit in this section has several advantages. Firstly, according to the Friis equation [24], the proposed impedance matching circuit is located at the output of the LNA, so its insertion has a little effect on the overall noise figure. Secondly, the gain-controllable characteristic of the LNA is not impacted by the insertion of the matching circuit, therefore there is no attenuation of the amplifying signal. Thirdly, the additional transistors in the signal path led to an increased immunity to reverse signal propagation. As a result, the insertion of the matching circuit led to the output impedance being perfectly matched to the ideal value (50 Ohm).
Compared to the traditional passive component solutions, the output impedance matching circuit of the proposed CCCII-based LNA is vastly superior by being: the small chip area without the inductor components, the flexible matching circuit to adjust any impedance to the ideal value, and a novel example of wideband output matching for the RF LNA applications.

Simulation Results and Discussion
The proposed wideband LNA has been realized using a GlobalFoundries' 0.18 µm single-poly six-metal CMOS technology and simulated using Cadence SpectreRF simulator. The GlobalFoundries' Design Rule (YI-093-DR001_Rev1V_1.8V-3.3V) and GlobalFoundries' Spice Model spec (yi093dr001_1v_00_20090731a) are used. During the design process, a very important step is the realization of the layout. To maximize RF performance, the layout was made by following classical design rules commonly used for analogue RF circuit synthesis (e.g., transistor matching, symmetric design, etc.). In order to validate the design approach, optimization of biasing currents and width of transistors with extensive DC analysis are simulated. The layout of the proposed wideband LNA is presented in Figure 4, which takes an active chip area, including testing pads of 0.42 mm × 0.23 mm. The absence of inductor components results in a very small chip area (0.096 mm 2 ). Figure 5 presents the simulated input return loss (S11) with I o1 = 1.25 mA, I o2 = 50 µA, and V DC = ±1.5 V. At a frequency of 1.0 GHz, S11 has a value of −21.4 dB and it remains below −16.6 dB for frequencies from 0.5 GHz to 2.5 GHz. As a critical parameter of the LNA, the S11 provides a good wideband input matching performance without the LC matching network. Figure 5 also presents the simulated output return loss (S22), which uses the translinear CCCII 3 in voltage follower mode as the output impedance matching circuit. The simulated S22 is from −10.6 dB to −18.6 dB over the entire frequency band of 0.5~2.5 GHz, indicating a reasonably acceptable output matching condition. and VDC = ±1.5 V. At a frequency of 1.0 GHz, S11 has a value of −21.4 dB and it remains below −16.6 dB for frequencies from 0.5 GHz to 2.5 GHz. As a critical parameter of the LNA, the S11 provides a good wideband input matching performance without the LC matching network. Figure 5 also presents the simulated output return loss (S22), which uses the translinear CCCII 3 in voltage follower mode as the output impedance matching circuit. The simulated S22 is from −10.6 dB to −18.6 dB over the entire frequency band of 0.5~2.5 GHz, indicating a reasonably acceptable output matching condition. In the proposed LNA, gain control over a wide range is achieved by varying the DC biasing current, Io2, of the CCCII 2. Figure 6 shows that the voltage gain of the proposed LNA can be controllable between 18 dB and 1 dB when Io2 varies between 30 μA and 400 μA, at the same time, the LNA consumes between 3.8 mA and 5 mA for the entire range of Io2. The inversely proportional relationship between the voltage gain and the DC biasing current indicates that better gain is achieved at the lower power consumption.  As described by Equations (6) and (7), the voltage gain increased and bandwidth decreased when Io2 decreased. In order to control the LNA performance over the 0.5~2.5 GHz bandwidth of interest, the currents Io1 and Io2 are fixed at 1.25 mA and 50 μA for this design. Under these conditions, the typical voltage gain (S21) and reverse isolation (S12) performances are present in Figure 7. The simulated S21 shows a typical voltage gain of 12.6 dB with a gain ripple of ±1.5 dB from 0.5 GHz to 2.5 GHz. According to Figure 7, the simulated S12 is from −65.2 dB to −39.5 dB in the required band, which indicates that the designed LNA can achieve a good stability characteristic. The better S12 can decrease the subsequent local oscillation (LO) leakage, arising from the substrate coupling and the capacitive paths. In the proposed LNA, gain control over a wide range is achieved by varying the DC biasing current, I o2 , of the CCCII 2. Figure 6 shows that the voltage gain of the proposed LNA can be controllable between 18 dB and 1 dB when I o2 varies between 30 µA and 400 µA, at the same time, the LNA consumes between 3.8 mA and 5 mA for the entire range of I o2 . The inversely proportional relationship between the voltage gain and the DC biasing current indicates that better gain is achieved at the lower power consumption.
As described by Equations (6) and (7), the voltage gain increased and bandwidth decreased when I o2 decreased. In order to control the LNA performance over the 0.5~2.5 GHz bandwidth of interest, the currents I o1 and I o2 are fixed at 1.25 mA and 50 µA for this design. Under these conditions, the typical voltage gain (S21) and reverse isolation (S12) performances are present in Figure 7. The simulated S21 shows a typical voltage gain of 12.6 dB with a gain ripple of ±1.5 dB from 0.5 GHz to 2.5 GHz. According to Figure 7, the simulated S12 is from −65.2 dB to −39.5 dB in the required band, which indicates that the designed LNA can achieve a good stability characteristic. The better S12 can decrease the subsequent local oscillation (LO) leakage, arising from the substrate coupling and the capacitive paths.  As described by Equations (6) and (7), the voltage gain increased and bandwidth decreased when Io2 decreased. In order to control the LNA performance over the 0.5~2.5 GHz bandwidth of interest, the currents Io1 and Io2 are fixed at 1.25 mA and 50 μA for this design. Under these conditions, the typical voltage gain (S21) and reverse isolation (S12) performances are present in Figure 7. The simulated S21 shows a typical voltage gain of 12.6 dB with a gain ripple of ±1.5 dB from 0.5 GHz to 2.5 GHz. According to Figure 7, the simulated S12 is from −65.2 dB to −39.5 dB in the required band, which indicates that the designed LNA can achieve a good stability characteristic. The better S12 can decrease the subsequent local oscillation (LO) leakage, arising from the substrate coupling and the capacitive paths. As shown in Figure 8, the proposed wideband LNA is simulated for different temperatures and corner processes. The wideband LNA designed here has an excellent thermal stability: in the temperature range of −25 °C to 75 °C, the gain S21 drops about by ±1 dB. As the temperature increases, the gain S21 of the wideband LNA gradually decreases.  As shown in Figure 8, the proposed wideband LNA is simulated for different temperatures and corner processes. The wideband LNA designed here has an excellent thermal stability: in the temperature range of −25 • C to 75 • C, the gain S21 drops about by ±1 dB. As the temperature increases, the gain S21 of the wideband LNA gradually decreases.
Owing to noise concerns, Figure 9 shows the simulated NF of the wideband LNA with I o1 = 1.25 mA and I o2 = 50 µA. It has a relatively flat and low NF performance across the entire 2 GHz bandwidth. From Figure 9, an excellent NF of 4.05~4.35 dB in the frequency range of 0.5~2.5 GHz is achieved. The maximum NF is 4.35 dB at 0.5 GHz and the minimum NF is 4.05 dB at 1.5 GHz, with an average NF of 4.2 dB.
To observe the nonlinear behavior, the two-tone signals at 1.50 GHz and 1.51 GHz with equal power levels are applied to the wideband LNA. The two-tone signals with 10 MHz spacing are used to simulate the fundamental and third-order inter-modulation (IM3) output power, versus input power, characteristics. As shown in Figure 10, an input third-order intercept point (IIP3) of −2.5 dBm and an input 1 dB compression point of −12.5 dBm are achieved. These results show that the designed LNA can achieve good linearity even with the low NF. As shown in Figure 8, the proposed wideband LNA is simulated for different temperatures and corner processes. The wideband LNA designed here has an excellent thermal stability: in the temperature range of −25 °C to 75 °C, the gain S21 drops about by ±1 dB. As the temperature increases, the gain S21 of the wideband LNA gradually decreases. Owing to noise concerns, Figure 9 shows the simulated NF of the wideband LNA with Io1 = 1.25 mA and Io2 = 50 μA. It has a relatively flat and low NF performance across the entire 2 GHz bandwidth. From Figure 9, an excellent NF of 4.05~4.35 dB in the frequency range of 0.5~2.5 GHz is achieved. The maximum NF is 4.35 dB at 0.5 GHz and the minimum NF is 4.05 dB at 1.5 GHz, with an average NF of 4.2 dB. To observe the nonlinear behavior, the two-tone signals at 1.50 GHz and 1.51 GHz with equal power levels are applied to the wideband LNA. The two-tone signals with 10 MHz spacing are used to simulate the fundamental and third-order inter-modulation (IM3) output power, versus input power, characteristics. As shown in Figure 10, an input third-order intercept point (IIP3) of −2.5 dBm and an input 1 dB compression point of −12.5 dBm are achieved. These results show that the designed LNA can achieve good linearity even with the low NF. For I o2 = 50 µA, and at a dual supply voltage of ±1.5 V, the CCCII-based LNA consumes a current of 4 mA which results in a total power consumption of 12 mW. Finally, Table 1 is a summary of the proposed CMOS 0.5~2.5 GHz wideband LNA and reports recent CMOS state-of-the-art wideband LNA designs. Compared to other wideband LNA designs, the post-layout simulation results show that the proposed LNA can achieve a good wideband input/output impedance matching by using the CCCIIs, and further benefits include its inductorless design with smaller chip area and the capability of gaincontrollability by varying a DC biasing current (I o2 ).
To observe the nonlinear behavior, the two-tone signals at 1.50 GHz and 1.51 GHz with equal power levels are applied to the wideband LNA. The two-tone signals with 10 MHz spacing are used to simulate the fundamental and third-order inter-modulation (IM3) output power, versus input power, characteristics. As shown in Figure 10, an input third-order intercept point (IIP3) of −2.5 dBm and an input 1 dB compression point of −12.5 dBm are achieved. These results show that the designed LNA can achieve good linearity even with the low NF. For Io2 = 50 μA, and at a dual supply voltage of ±1.5 V, the CCCII-based LNA consumes a current of 4 mA which results in a total power consumption of 12 mW. Finally, Table 1 is a summary of the proposed CMOS 0.5~2.5 GHz wideband LNA and reports recent CMOS state-of-the-art wideband LNA designs. Compared to other wideband

Conclusions
In this paper, a new wideband LNA which utilizes current conveyors as building blocks has been presented. Thanks to the use of three different CCCIIs for conveying the signal, the proposed wideband LNA has the following notable advantages over recent works: the total absence of inductor components, and thus, the LNA has an active chip area of only 0.096 mm 2 ; wideband input/output impedance matching and stable frequency responses in the required 0.5~2.5 GHz band; easily gain-controllable over a wide range (from 1 dB to 18 dB). The above excellent performances have shown that the proposed CCCII-based wideband LNA is suited to the software-defined and multi-standard wireless communication systems.

Data Availability Statement:
The data that support the findings of this study are available within the article.