A Fully Integrated Low-Dropout Regulator with Improved Load Regulation and Transient Responses

A fully integrated low-dropout (LDO) regulator with improved load regulation and transient responses in 40 nm technology is presented in this paper. Combining adjustable threshold push–pull stage (ATPS) and master–slave power transistors topology, the proposed LDO maintains a three-stage structure within the full load range. The proposed structure ensures the steady-state performance of LDO and achieves 0.017 mV/mA load regulation. The ATPS consumes little quiescent current at light load current condition, and the turn-on threshold of the ATPS can be adjusted by a current source. Once the value of current source is set, the turn-on threshold is also determined. A benefit of the proposed structure is that the LDO can be stable from 0 to 100 mA load current with a maximum 100 pF parasitic load capacitance and a 0.7 pF compensation capacitor. It also shows good figure of merit (FOM) without an extra transient enhanced circuit. For the maximum 100 mA load transient with 100 ns edge time, the undershoot and overshoot are less than 33 mV. The dropout voltage of the regulator is 200 mV with input voltage of 1.1 V. The total current consumption of the LDO was 24.6 μA at no load.


Introduction
The low-dropout linear regulator is a power converter that is widely used in power management, as it can provide low-ripple, low-noise and precision-regulated supply voltages for high-performance and noise-sensitive analog/mixed-signal blocks. The conventional PMOS LDO regulator, normally, needs a bulky off-chip capacitor in the range of several µF to achieve fast transient response and maintain stable [1,2]. For SoC application, removal of the off-chip capacitor can reduce the area of the printed circuit board (PCB) and the number of I/O pads on the chip, which is significantly beneficial in terms of integration. Therefore, in recent years, fully integrated LDO (or OCL-LDO) regulators have been widely studied and reported [3][4][5][6][7][8][9][10][11][12][13][14][15][16]. The output load capacitor C L mainly comes from parasitics of the power line, which is generally modeled from a few decades to 100 pF, and several orders lower than the off-chip capacitor. As a result, the major performance requirements of the fully integrated LDO will inevitably degrade aspects such as transient response and power-supply rejection (PSR). Therefore, the performance of a fully integrated LDO depends more on unity-gain bandwidth (UGB) and slew rate [15].
A series of technologies for improving the performance of fully integrated LDO are proposed. The push-pull stage is widely used to drive the power transistor in LDO regulators because the push-pull structure has greater driving ability [9,10]. LDO regulators making use of advanced compensation technology, which achieve more than 100 MHz UGB, have been proposed in [5,15]. However, it is worth noting that their load capacitor is limited below 5 pF, and their minimum load current is more than 120 µA. This is because if the load current is too low, the nondominant complex poles with a large Q factor cause a magnitude peaking near the unity gain frequency [16]. Thus, they are unattractive in low-power or large capacitive load applications. The flipped voltage follower (FVF) [12][13][14]-based LDO regulator is one of the most popular architectures due to its simplicity and its potential for fast transient response. In [14], an ultra-fast low-gain loop realized excellent transient response, and an additional loop is introduced to improve the DC accuracy. Nevertheless, its max load current is only 10 mA, and it consumes a large chip area to fabricate a 140 pF on-chip capacitor. Master-slave power transistors topology is popular in recent years, and it is used for ultra-low power design in [6,7], in which the LDOs transform between two-stage and three-stage cascaded topology at different load conditions. They can achieve ultra-low power consumption and good transient response. However, in order to maintain stable operation, the two-stage topology under light load comes at the cost of low accuracy. Especially in advanced processes, such as the 40 nm process, the small loop gain of LDO will lead to large dc error. In this paper, a LDO that combines master-slave power transistor topology and an adjustable threshold push-pull stage (ATPS) with improved transient response and load regulation is proposed.

Conventional Three-Stage LDO Regulators
Conventional three-stage LDO regulators with single miller compensation can be modeled as Figure 1a. The dominant pole is located at the output of the first stage. Compared with the two-stage LDO regulator in [10], an additional stage G m2 is added. Ignoring the presence of parasitic C G , the LDO can be simplified as a second-order system with two poles. The second and the power stages together can be considered as a large G m stage with an effective G m of G m2 R 2 G mP , which is much higher than G mP alone, and the nondominant pole would be at G m2 R 2 G mP /C L . However, this is an ideal assumption, because the decrease in the quiescent current leads to an increase in the impedance at each node and reduction in transconductance in each gain stage. The nondominant pole moves toward low frequency under both zero-load current, low quiescent current and large-load capacitor condition. Especially in less advanced processes, large C G makes the system third-order and the nondominant poles become complex [15] with large Q ( = R 2 G m2 G mP C gsP /C L ).
Complex poles locate at low frequency with large Q may lead to system instability [16]. As shown in Figure 1b, for a buffer impedance attenuation-based LDO regulator [1], the impedance (R G ) at the gate of the power transistor is attenuated by a buffer, such that the pole at the gate of the power transistor is pushed to high frequency. However, this kind of LDO regulator requires an additional V SG to ensure the operation. So, the LDO regulator struggles to fulfill the headroom budget in low-supply-voltage application [9]. Simultaneously, the gain of the buffer is approximately equal to one, so the buffer-based LDO regulator, in fact, is a two-stage LDO, and the loop gain is sacrificed.

Proposed ATPS
A gm-boosting push-pull stage is shown in Figure 2a. M 11 and M 12 have the same aspect ratio. M 12 , M 13 and M 8 , M 9 are two pairs of k-times current mirrors, and the effective transconductance is increased by 2k times. A push-pull output stage composed of M 13 and M 9 can charge and discharge the gate parasitic capacitance more effectively, since the bias current is increased by k times. To have a larger g m and driving ability, a larger proportionality factor k can be adopted, but at the expense of a quiescent current as the design trade off.
So, an adjustable threshold push-pull stage is proposed in this paper, as shown in Figure 2b. Compared with Figure 2a, ATPS has one more current source, I 0 . Due to the existence of current source I 0 , when the potential of V in is relatively high, the current of M 14 and M 19 is small. The drain of M 14 is pulled to the ground; thus, M 17 has no current, and the drain of M 21 is pulled to power V DD . At this time, the ATPS is turned off and only M 18 and I 0 consume very little quiescent current. The turn-on threshold can be adjusted by the value of I 0 . Once the fixed bias I 0 is set, the turn-on threshold is also determined. When the ATPS turned on, it works like the g m boosting push-pull stage. With a large k, g m and driving ability significantly improved, without significantly increasing the quiescent current under light load.

Circuit Implementation
A simplified structure block diagram is shown in Figure 3. The corresponding schematic of the regulator is depicted in Figure 4. The gm boosting push-pull stage and ATPS correspond to M 7 -M 13 and M 14 -M 21 , respectively. The feedback factor, β = R 1 /(R 1 + R 2 ), is 5/9 in this design and the reference voltage V re f is 500 mV. M 2 -M 6 form the differential input stage. The aspect ratio of M p2 is 60 times that of M p1 . In this design, the turn-on threshold of ATPS is designed to be I LOAD = 500 µA by setting the current of M 15 to 2.5 µA.
When load current is less than about 500 µA, the ATPS and M p2 , dotted line in the Figure 3, is off. When load current is more than about 500 µA, the ATPS turns on and two power transistors work together to provide load current. Compared with [1,6,7], the structure proposed in this letter maintains a three-stage structure within the full load range rather than two-stage or three-stage cascaded topology at different load conditions. The proposed structure ensures the steady-state performance of LDO, such as load regulation. Compared with conventional LDO at light load condition, since the master power transistor is turned off, the gate parasitic capacitance of the power transistor with large aspect ratio can be considered "reduced". So, the Q is reduced at light load condition. The parasitic capacitance is related to the nondominant poles, which also means the nondominant pole in this structure is moved to a higher frequency, benefiting from frequency compensation. When the load current increases, the potential at the output of the error amplifier decreases and the ATPS turns on. Then, the current in M 17 and M 21 naturally increases. Therefore, they can drive the power transistor more effectively.  The detailed overall operating waveform of the proposed LDO is shown in Figure 5. EA_out, PPS_out and ATPS_out are the output voltage of error amp, push-pull stage and ATPS, respectively, in Figure 3; I MP1 and I MP2 are the current of M P1 and M P2 , respectively, in Figure 3; I M21 is the current of M 21 in Figure 4. When the LDO is under light load condition, the ATPS is off. So ATPS_out, I MP2 and I M21 remain unchanged, and only M P1 provides current for the load. When load current is more than 500 µA, ATPS is on and M P1 and M P2 provides current for the load together. Meanwhile, I M21 increases as the load current increases, which improves transient response under heavy load.

Stability Analysis
The stability of the LDO regulator is realized by single miller compensation. Due to the structural transformation, the stability of the proposed fully integrated LDO regulator will be discussed on the basis of ATPS on and off structure, as shown in Figure 6. The transfer function is derived using the following assumptions: (a) the gains in the first stage, pushpull stage and ATPS are much larger than one, (b) g mi is defined as the transconductance of the respective device, C i and R i denote the respective lumped output parasitic capacitance and output resistance of each node, (c) the capacitances C L C m , C 4 C 1 , C 2 , (d) g mp2 g mp1 . Case I (I LOAD < 500 µA): When I LOAD < 500 µA the ATPS is off, the gate's potential of the M p2 is pulled to power V DD . Thus, ATPS and M p2 can be ignored in the analysis of Case I. Figure 6a shows the small-signal model, which is similar to Figure 1a, except for the parasitic capacitor at the gate of the power transistor. The effective output resistance for Case I is R o − 1 =r oMp1 //R FB //R LOAD , where r oMp1 , R FB and R LOAD are the output resistance of the slave-power transistor, feedback network resistance and load resistance, respectively. The derived transfer function is shown as Equation (1).
where G 1 = K 1 g m11 + g m7 . Because C 2 C L , the three poles are separated real poles. The low-frequency gain A V0 and dominant pole p −3dB are given as The gain-bandwidth product is given by GBW = g m3 /C m . The nondominant poles can be given as p 2 = −G 1 R 2 g mP1 /C L , p 3 = −1/(R 2 C 2 ). Since the zeros are located at a higher frequency, they are neglected. The worst PM occurs when the load current is zero and the load capacitance is 100 pF, because p 2 is inversely proportional to C L and proportional to g mp1 . Additionally, g mp1 is proportional to the square root of the load current. Thus, the PM is enhanced when the load current increases. The p 3 is located at higher frequency and has little impact on PM. The PM can be derived as From Equations (3) and (4), we see that as C 2 decreases and p 3 is pushed to higher frequency, the minimum C m required is reduced.
Case II (I LOAD ≥ 500 µA): When I LOAD ≥ 500 µA the ATPS is on, both ATPS and M p2 should be considered in the stability analysis. Figure 6b shows the small-signal model. R o − 2 =r oMp1 //r oMp2 //R FB //R LOAD is the effective output resistance for Case II, where r oMp2 is the resistance of the master power transistor. The transconductance g mp2 is much larger than g mp1 . The derived transfer function is shown as Equation (5), G 2 = K 2 g m19 + K 3 g m14 .
Because C 2 C L , the three poles are separated real poles. The low-frequency gain A V0 and dominant pole p −3dB are given as The nondominant complex poles can be approximately derived as From Equation (8), |p 2,3 | relies on g mP2 R o − 2 and locates at high frequency. A higher frequency pole locates at p 4 = − 1 R o − 2 C L . Since zeros are located at a higher frequency, they are neglected. Similar to [6,9,16], the worst PM occurs when I L OAD is minimum and C L is maximum, so the LDO can be stable as long as C L is less than 100 pF.

Open-Loop Frequency Response
The simulated open-loop frequency responses of the proposed LDO regulator at different Load conditions are shown in Figure 7. The regulator achieves a minimum phase margin of 60°with a 100 pF load capacitor. As previously analyzed, PM increases with the increase in the load current. To verify the stability when the load capacitance is zero, open-loop frequency responses are simulated and shown in Figure 7b. A better PM is achieved, because nondominant poles are shifted to higher frequencies. The result of the 400-run Monte Carlo analysis for mismatch and process variations is shown in Figure 8. The µ and σ of phase margin are 63.3°and 4.6°, respectively.  Figure 9 illustrates the load transient response with a full load current step from 0 A to 100 mA at the edge time of 100 ns of proposed LDO and conventional LDO. The conventional LDO is a three-stage LDO with a g m -boosting push-pull stage as the second stage. The quiescent current of proposed LDO and conventional LDO are the same at no load. The undershoot and overshoot of the proposed LDO are 32 mV and 33 mV, respectively, and are better than conventional LDO. The reference voltage, V re f , is 0.5 V, so the minimum output voltage is 0.5 V when feedback is unit gain negative feedback. Figure 10 shows the load transient response with 0-100 mA load current step at the edge time of 100 ns of the proposed LDO when V DD = 1.1 V, V OUT = 0.5 V, C L = 100 pF. The undershoot and overshoot are 31 mV and 24 mV, respectively.

ATPS
The quiescent current of ATPS is the current of M 14 , M 18 and M 21 . As shown in Figure 12a, in the off state, the quiescent current of ATPS is 3.8 µA. With the increase in the load current, the quiescent current of ATPS will increase to 37 µA. As previously analyzed, the dynamic bias strategy of ATPS not only improves the efficiency under light load, but also improves the transient response under heavy load.
As shown in Figure 12b, with the increase in the load current, V G remains unchanged and then decreases. With the increase in load current, I Mp2 remains unchanged and then decreases. V G is the gate voltage of M p2 and also the output of ATPS; I Mp2 is the current of M p2 . The simulation results verify the previous analysis: the gate of the power transistor M p2 is pulled to V DD by ATPS, and the M p2 turns off under light load.

Power-Supply Rejection
The PSR of a LDO can be given as [17] where ω o is the pole at the output of the LDO, LG(s) is the loop gain and R L and r ds denote the load resistance and the output impedance of M P , respectively. If the dominant pole is inside the loop and the output is the nondominant pole, loop gain rolls off at the −20 dB/decade slope, causing the PSR to degrade at the same rate from ω dominant . This degradation continues until the loop-gain unity-gain frequency, ω ugb , after which PSR remains flat because the ripple is only reduced by the resistive divider formed between R L and r ds [17]. Simulated PSR performance of the proposed LDO at 100 mA load current, 0-pF C L and 200 mV dropout is shown in Figure 13. The PSR of the proposed LDO is −46 dB at 1 KHz and −2.5 dB at 1.1 MHz. The PSR degrades at −20 dB/decade from ω dominant (about 5 kHz) and remains flat after ω ugb (about 1.1 MHz), which corresponds to the analysis in [17] and the simulated open-loop frequency response in Figure 7b. In Figure 7b, the dominant pole and the unity-gain bandwith is located at about 5 kHz and 1.1 MHz, respectively.

Performance Comparison
For different processes, the minimum channel length (L) will affect the parasitic capacitance of the power transistor. If a process has a shorter minimum L, the FOM could be smaller owing to the smaller parasitic capacitance of the transistor. For fair comparison, the figure-of-merit (FOM) equation, as given below, which was originally proposed in [11], considering minimum L is adopted to compare the transient response.
The performance comparison of the proposed LDO with several state-of-the-art fully integrated LDOs is shown in Table 1. The proposed LDO has achieved quite comparable load regulation and FOM. [*] FOM = T edge ·∆V OUT · (I Q + I LOAD(min) )/(∆I LOAD · L 2 ) proposed in [11].

Conclusions
A transient-enhanced, fully integrated LDO regulator is presented in this paper. Through the combination of ATPS and master-slave power transistor topology, the LDO regulator can achieve good transient response, without significantly increasing quiescent current at light load. In the full load range, the LDO always maintains a three-stage structure, which ensures the loop gain and accuracy and achieves good load regulation. The proposed fully integrated LDO regulator achieves stability from 0 to 100 mA without the minimum load current limit. The miller compensation capacitor for stability can be reduced, as well.