2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation

This paper provides modeling and simulation insights into field-effect transistors based on graphene (GFET), focusing on the devices’ architecture with regards to the position of the gate (top-gated graphene transistors, back-gated graphene transistors, and top-/back-gated graphene transistors), substrate (silicon, silicon carbide, and quartz/glass), and the graphene growth (CVD, CVD on SiC, and mechanical exfoliation). These aspects are explored and discussed in order to facilitate the selection of the appropriate topology for system-level design, based on the most common topologies. Since most of the GFET models reported in the literature are complex and hard to understand, a model of a GFET was implemented and made available in MATLAB, Verilog in Cadence, and VHDL-AMS in Simplorer—useful tools for circuit designers with different backgrounds. A tutorial is presented, enabling the researchers to easily implement the model to predict the performance of their devices. In short, this paper aims to provide the initial knowledge and tools for researchers willing to use GFETs in their designs at the system level, who are looking to implement an initial setup that allows the inclusion of the performance of GFETs.


Introduction
The development of CMOS (complementary metal-oxide semiconductor) transistors is achieving its performance limit, due to the maximum downscaling according to Moore's law. Several new materials have appeared with the potential to overcome silicon devices' performance; most of these rely on two-dimensional (2D) materials. Those families of materials feature dangling-bond free surfaces exhibiting excellent electronic and optical properties. Such materials range from graphene to other 2D materials, such as the transition metal dichalcogenides (TMDCs). TMDCs have a finite bandgap, which is essential to enable low-power digital electronics. The state of the art of the TMDC transistors and silicon transistors is similar, as reported in [1], where MoS 2 was used as the channel of the transistor, achieving an intrinsic maximum oscillation frequency (f max ) of 50 GHz at low temperatures. Despite the promising results at cryogenic temperatures, the FET mobility at room temperature remains low for TMDCs. Because of that, graphene (a monolayer of carbon atoms in a honeycomb lattice) is being widely pursued as an enabling material; it has amazing properties at room temperature, such as high saturation velocity and high carrier mobility, which make this material suitable for radiofrequency (RF) applications, for example.
Since the discovery of graphene by Geim and Novoselov in 2004 [2], it continues to attract the interest of the scientific community, both for the prospects it offers in fundamental research [3,4], and for applied physics [5,6]. Graphene is a 2D material, consisting of a sheet of carbon atoms arranged in a honeycomb lattice, weakly bonded to a supporting substrate [7]. The absence of a band gap in the band structure of graphene [8] is a serious obstacle for the development of digital applications based on this material (in contrast with the TMDCs); nevertheless, this is not a limiting factor for analog applications. Given the broad potential of graphene, several GFETs (graphene field-effect transistors) have been reported in the literature; these range from biosensing applications to flexible electronics or radiofrequency circuits [9][10][11].
From initial measurements, performed on monolayer graphene, a very high mobility of about 20,000 cm 2 V −1 s −1 was observed at low temperature (with high mobility also observed at room temperature), suggesting the possibility of the use of this material in very fast analog electronics, due to the very short carrier transit time. However, it must be noted that the properties of graphene-mainly its high mobility-change with the substrate where the graphene lays, as suggested in [12]. High mobility was achieved on suspended graphene on a SiO 2 substrate, which suggests that high mobility can be achieved even after the graphene's transfer to a substrate [13]. Despite this, suspended membranes of graphene are not suitable for the fabrication of GFETs, due to their non-compatibility with the conventional CMOS processes.
The good potential of graphene in GFETs-mainly in radiofrequency, where graphene's high mobility is essential to achieve a good performance-is demonstrated by the cutoff frequency ( f T ) of 100 GHz achieved in devices with a gate length of 240 nm in SiC substrates [14], or by the f T of 155 GHz in 40 nm gate length devices by PE-CVD-grown graphene transferred to DLC (diamond-like carbon substrates) [15]. Despite these promising results, research is still required, from different research fields, to achieve better performance in GFETs, as well to incorporate this technology at the system level. Thus, simple models that can help the researchers to predict the GFETs' behavior need to be made available for integration in circuit-level tools.
In this paper, a review will be performed regarding the most common graphene field-effect transistors (GFETs) and their applications, along with discussion of how they can be modeled for use in tools that allow circuit-and/or system-level simulation, in order to assess the performance of electronic or sensing circuitry based on such GFETs. This paper is divided into four sections: firstly, a discussion of the different architectures for the graphene transistors is presented; then, the different fabrication techniques are presented and discussed; in the third section, the different substrates for GFET fabrication are addressed; finally, a model of the graphene transistor is presented, and its potential use discussed. This model was implemented in MATLAB, Verilog in Cadence, and VHDL-AMS in Simplorer, which are three tools widely used for electronic circuit simulation.

Most Common Graphene Transistor Topologies
A field-effect transistor is a device characterized mainly by its three terminals (four terminals, considering the bulk terminal): the drain, the source, and the gate. The drain and the source are interconnected by the graphene channel. The gate is isolated from the channel by a gate dielectric. The channel is characterized by its length (L) and its width (W). For a given drain-source voltage (V DS ) a current (I DS ) flows through the channel, from drain to source. By applying a potential (V GS ) on the third terminal (the gate), this current can be modulated by adjusting the charge of the channel through the induced electric field-the basic operation of the field-effect transistors. A GFET is a particular implementation of the above description, where the channel is implemented using a graphene layer.
This section is dedicated to describing the three most common topologies of graphene transistors. From the literature, as shown in Figure 1, we may identify three main types of GFET, classified essentially by the gate position: top-gated graphene transistor, back-gated graphene transistor, and top-/back-gated graphene transistor. The selection of one of the previous topologies will have implications for the fabrication methodology or for available applications, as well as for expected performance and modeling considerations. The next sections will address such issues, giving some insights about topology selection.

Top-Gated Graphene Transistor
Top-gated GFETs are widely found in publications related to RF applications [16][17][18], and are also very promising in the development of graphene-based liquid-gate transistors (SGFETs), with a wide range of applications in biosensors [19].
In Figure 2, three different examples of top-gated devices reported in the literature are shown. In Figure 2a, a simple case of a top-gated graphene transistor is presented. Figure 2b presents a top-two-fingers-gated device. In Figure 2c a double-top-gated equivalent topology is presented. In Figure 2d,e, a biosensor with a top-liquid gate and its architecture are presented, respectively.  [16]; (b) two-fingers [18]; (c) topology of the two-fingers transistor; (d) top-liquid gate [19]; and (e) topology of the top-liquid gate.
Top-gated graphene transistors are a suitable approach to applications where a thin oxide layer gate is required. This is necessary to exert more control over the electrostatically doped carriers in the channel and, consequently, a lower gate bias is required to modulate the channel. Despite all the advantages of this approach, the difficulty of growing an oxide on top of the graphene, without damaging its lattice and degrading its The selection of one of the previous topologies will have implications for the fabrication methodology or for available applications, as well as for expected performance and modeling considerations. The next sections will address such issues, giving some insights about topology selection.

Top-Gated Graphene Transistor
Top-gated GFETs are widely found in publications related to RF applications [16][17][18], and are also very promising in the development of graphene-based liquid-gate transistors (SGFETs), with a wide range of applications in biosensors [19].
In Figure 2, three different examples of top-gated devices reported in the literature are shown. In Figure 2a, a simple case of a top-gated graphene transistor is presented. Figure 2b presents a top-two-fingers-gated device. In Figure 2c a double-top-gated equivalent topology is presented. In Figure 2d,e, a biosensor with a top-liquid gate and its architecture are presented, respectively. The selection of one of the previous topologies will have implications for the fabrication methodology or for available applications, as well as for expected performance and modeling considerations. The next sections will address such issues, giving some insights about topology selection.

Top-Gated Graphene Transistor
Top-gated GFETs are widely found in publications related to RF applications [16][17][18], and are also very promising in the development of graphene-based liquid-gate transistors (SGFETs), with a wide range of applications in biosensors [19].
In Figure 2, three different examples of top-gated devices reported in the literature are shown. In Figure 2a, a simple case of a top-gated graphene transistor is presented. Figure 2b presents a top-two-fingers-gated device. In Figure 2c a double-top-gated equivalent topology is presented. In Figure 2d,e, a biosensor with a top-liquid gate and its architecture are presented, respectively.  [16]; (b) two-fingers [18]; (c) topology of the two-fingers transistor; (d) top-liquid gate [19]; and (e) topology of the top-liquid gate.
Top-gated graphene transistors are a suitable approach to applications where a thin oxide layer gate is required. This is necessary to exert more control over the electrostatically doped carriers in the channel and, consequently, a lower gate bias is required to modulate the channel. Despite all the advantages of this approach, the difficulty of growing an oxide on top of the graphene, without damaging its lattice and degrading its  [16]; (b) two-fingers [18]; (c) topology of the two-fingers transistor; (d) top-liquid gate [19]; and (e) topology of the top-liquid gate.
Top-gated graphene transistors are a suitable approach to applications where a thin oxide layer gate is required. This is necessary to exert more control over the electrostatically doped carriers in the channel and, consequently, a lower gate bias is required to modulate the channel. Despite all the advantages of this approach, the difficulty of growing an oxide on top of the graphene, without damaging its lattice and degrading its mobility, remains a problem. To solve this, several approaches have been developed, such as the physical transfer of a nanowire with an oxide shell to act as a gate electrode [16]. Standard fabrication processes are being researched to prevent the graphene lattice, such as the use of ALD (atomic layer deposition) to grow Al 2 O 3 , or the thermal growth of Al 2 O 3 after the evaporation of a native layer of aluminum. Another approach could be the use of the boron nitride (h-BN) films to act as a gate dielectric. The h-BN film has a dielectric constant of~3.4; however, due to the similarity with the hexagonal graphene's structure, it is the suitable oxide to be used together with graphene due to the absence of dangling bonds on its surface, which makes this a chemically inert material. With this approach, the graphene's mobility could be improved by one order of magnitude when compared with other approaches. In Table 1 several top-gated graphene devices are summarized. The reported devices consist of several devices that are under research to increase the transconductance (g m ), RF performance, or drain-current saturation of GFETs. As it is possible to observe in Table 1, the performance of top-gated graphene transistors may be increased by the correct choice of the gate dielectric, the self-alignment of the source and drain electrodes (which reduce the ungated region of the channel, and are very important to increase the RF performance), and by using complex gate structures (for example, the T-shaped gates, reducing the gate resistance). For biosensors, this approach enables the detection of lower concentrations of analytes.

Back-Gated Graphene Transistor
Another very widely used structure for GFET devices is the back-gated topology. From the literature, this group of GFETs is mostly used in biosensors [24,25] or photodetectors [26][27][28]. In this topology approach, the final device has the graphene of the channel exposed, which is very useful for sensors or for light collection. In this kind of device, the interaction of the graphene's surface with light (photodetectors) or with molecules (biosensors) produces changes in graphene's properties, which lead to a change in the graphene's transfer curve, enabling the quantitative evaluation of the element that induced this change. However, with this topology, high transconductance is hard to achieve, given the small geometric capacitance of the gate. Typically, this kind of transistor is operated with high back-gate voltages, reaching dozens of volts, which is out of the range of the common applications of the electronic circuits. In Figure 3, some examples of back-gated devices are presented, being used as biosensors or photodetectors.

Back-Gated Graphene Transistor
Another very widely used structure for GFET devices is the back-gated topology. From the literature, this group of GFETs is mostly used in biosensors [24,25] or photodetectors [26][27][28]. In this topology approach, the final device has the graphene of the channel exposed, which is very useful for sensors or for light collection. In this kind of device, the interaction of the graphene's surface with light (photodetectors) or with molecules (biosensors) produces changes in graphene's properties, which lead to a change in the graphene's transfer curve, enabling the quantitative evaluation of the element that induced this change. However, with this topology, high transconductance is hard to achieve, given the small geometric capacitance of the gate. Typically, this kind of transistor is operated with high back-gate voltages, reaching dozens of volts, which is out of the range of the common applications of the electronic circuits. In Figure 3, some examples of back-gated devices are presented, being used as biosensors or photodetectors.  [25]; (b) topology of the biosensor; (c) graphene photodetector [28]; and (d) the topology of the photodetector; (e) graphene FET used for the study of the saturation velocity with h-BN as a gate dielectric [29]; (f) graphene photodetector [30]; and (g) the topology of (f).
These devices (buried gates, in contrast with the back-gated devices) are very useful, mainly in RF applications, given the small achievable gate capacitance, reducing the parasitic capacitance, which increases the RF performance. In this approach, the common issues associated with the growth of an oxide on top of the graphene are avoided. In Table  2, several back-gated devices are reported and analyzed in terms of purpose and performance; they are mostly biosensors and photodetectors. Other devices are also present, where the focus of the device is the study of some of the transistor's properties, and where the conservation of the graphene's lattice is required. Devices where the h-BN films were used as back-gate dielectrics are also presented given their amazing properties when used together with graphene, as discussed earlier in this paper. Annealing in Ar/ before functionalization Detection limit depends on the length of the DNA, for 60-mer DNA the detection limit is 1 fM.
These devices (buried gates, in contrast with the back-gated devices) are very useful, mainly in RF applications, given the small achievable gate capacitance, reducing the parasitic capacitance, which increases the RF performance. In this approach, the common issues associated with the growth of an oxide on top of the graphene are avoided. In Table 2, several back-gated devices are reported and analyzed in terms of purpose and performance; they are mostly biosensors and photodetectors. Other devices are also present, where the focus of the device is the study of some of the transistor's properties, and where the conservation of the graphene's lattice is required. Devices where the h-BN films were used as back-gate dielectrics are also presented given their amazing properties when used together with graphene, as discussed earlier in this paper.

Top-/Back-Gated Transistor
For several applications, it is necessary to shift the Dirac point in order to electrostatically dope the graphene, adjusting the operation of the transistor. With this purpose, back gates are added to top-gated transistors. Figure 4 shows one top-/back-gated transistor and its topology. In fact, since graphene transistor research is only in the early stages, most of reported top-gated graphene transistors have back gates. Such devices are useful to tune all of the transistors to the same point (by tuning them all to the same Dirac point), reducing the variability between GFETs, which is a big drawback of GFETs today. In Table 3, several transistors with this configuration are presented.

Fabrication Methods
After presenting a set of GFETs in each topology, briefly discussing their applications and performance, this section will present the issues related to the fabrication aspects that are necessary to consider while selecting one of the previous options to obtain 2D electronic circuits.
Despite the promising properties of GFETs, several issues need to be solved to increase the performance of such devices to the required levels, e.g., the low on/off ratio of the graphene devices is a big limitation on the use of these devices for logic applications [44]. However, despite the high carrier mobility of graphene, such mobility is highly affected by the surrounding materials and the growth method, such as the used polymer in graphene transfer or the gate oxide for GFET fabrication [45]. The high contact resistance between graphene and metals is also a limitation on the performance of GFETs, mainly for RF applications [34]. Finally, the access resistance (caused by the ungated zone be- In fact, since graphene transistor research is only in the early stages, most of reported top-gated graphene transistors have back gates. Such devices are useful to tune all of the transistors to the same point (by tuning them all to the same Dirac point), reducing the variability between GFETs, which is a big drawback of GFETs today. In Table 3, several transistors with this configuration are presented.

Fabrication Methods
After presenting a set of GFETs in each topology, briefly discussing their applications and performance, this section will present the issues related to the fabrication aspects that are necessary to consider while selecting one of the previous options to obtain 2D electronic circuits.
Despite the promising properties of GFETs, several issues need to be solved to increase the performance of such devices to the required levels, e.g., the low on/off ratio of the graphene devices is a big limitation on the use of these devices for logic applications [44].
However, despite the high carrier mobility of graphene, such mobility is highly affected by the surrounding materials and the growth method, such as the used polymer in graphene transfer or the gate oxide for GFET fabrication [45]. The high contact resistance between graphene and metals is also a limitation on the performance of GFETs, mainly for RF applications [34]. Finally, the access resistance (caused by the ungated zone between drain/source and channel) is also an important aspect in the fabrication of GFETs [46]. To ensure good performance in GFETs, a good graphene quality is necessary, as well as a fabrication methodology that preserves the graphene's quality, while obtaining the device or the full system. Table 4 shows different ways to obtain different GFET devices, with different topologies, where the graphene-the core material-was obtained via different techniques. Such techniques will have an impact on final device performance, fabrication complexity, and fabrication repeatability, as well as on cost. Back [54] Being the fundamental material to support the device characteristics, the methodology to obtain the graphene and transfer it to the fabrication steps has been widely explored. Several methods to obtain graphene have been developed, with the most common growing solutions being CVD on a metal foil [55], CVD on SiC substrates [56], and mechanical exfoliation from bulk material (graphite) [57].

Graphene Fabrication Options
In addition to the final performance considerations, the chosen method to obtain graphene constrains the GFET fabrication process and, eventually, the transistor's topology. For example, when the graphene is obtained via mechanical exfoliation, the flake needs to be identified, and the structures of the source, drain, and gate are then fabricated [21], which make buried gated structures hard to fabricate, also limiting the scalability of the process. On the other hand, when CVD graphene is grown on metallic foils, since it needs to be transferred to the final substrate, and a large area could be covered by this kind of graphene, the structures of the source/drain and gate could be fabricated before or after the graphene transfer. However, degradation in the mobility of the graphene may be observed due to the transfer process [20]. In graphene grown on SiC substrates, the fabrication process is almost limited to top-gated structures [44]. Figure 5 summarizes the three main methodologies used to obtain the graphene for GFET fabrication. The selection of the appropriate methodology will be dependent on the available processing methods at each facility, on the required application, and on the integration level and scalability desired.

Substrate for Graphene Transistors
Another relevant aspect that has an impact on the performance and/or fabrication steps, as well as integration potential, is the base substrate that is used to fabricate the GFET devices. The substrate may be imposed by the fabrication facilities, by the integration methodology required, or by the graphene fabrication and processing steps, with the latter being the topic of the next discussion.
Graphene transistors can be fabricated on several substrates, with the most common being Si/SiO2 [58], SiC [59], and glass and quartz [60]. Graphene transistors are also reported in flexible substrates such as polyethylene naphthalate (PEN) [60] or polyethylene terephthalate (PET) [61]. These are very useful in nonplanar applications (wearables for example), with their low insertion loss being a good characteristic for THz applications [62]. The most commonly used substrate is Si/SiO2, due to their compatibility with the standard fabrication processes and the easy optical identification of the graphene on SiO2. This property makes these the most suitable substrates for the fabrication of high-quality CVD-grown graphene devices after graphene transfer. The presence of a thick layer of SiO2 on top of the Si substrate makes this substrate also very useful in RF applications, decreasing the parasitic substrate capacitances. SiC substrates are often used for the epitaxial growth of graphene for electronics applications, with the advantages of the use of the conventional top-down lithography techniques well established in nanotechnology [60]. In contrast to CVD-grown graphene, graphene grown on SiC substrates does not require a transfer. However, SiC-grown graphene remains cost-ineffective. Insulator substrates such as glass or quartz are very useful in graphene FET fabrication. These substrates bring advantages for RF applications due to their ability to reduce the parasitic substrate capacitance, reducing the RF losses associated with the substrates [23]. The selection of the appropriate methodology will be dependent on the available processing methods at each facility, on the required application, and on the integration level and scalability desired.

Substrate for Graphene Transistors
Another relevant aspect that has an impact on the performance and/or fabrication steps, as well as integration potential, is the base substrate that is used to fabricate the GFET devices. The substrate may be imposed by the fabrication facilities, by the integration methodology required, or by the graphene fabrication and processing steps, with the latter being the topic of the next discussion.
Graphene transistors can be fabricated on several substrates, with the most common being Si/SiO 2 [58], SiC [59], and glass and quartz [60]. Graphene transistors are also reported in flexible substrates such as polyethylene naphthalate (PEN) [60] or polyethylene terephthalate (PET) [61]. These are very useful in nonplanar applications (wearables for example), with their low insertion loss being a good characteristic for THz applications [62]. The most commonly used substrate is Si/SiO 2 , due to their compatibility with the standard fabrication processes and the easy optical identification of the graphene on SiO 2 . This property makes these the most suitable substrates for the fabrication of high-quality CVDgrown graphene devices after graphene transfer. The presence of a thick layer of SiO 2 on top of the Si substrate makes this substrate also very useful in RF applications, decreasing the parasitic substrate capacitances. SiC substrates are often used for the epitaxial growth of graphene for electronics applications, with the advantages of the use of the conventional top-down lithography techniques well established in nanotechnology [60]. In contrast to CVD-grown graphene, graphene grown on SiC substrates does not require a transfer. However, SiC-grown graphene remains cost-ineffective. Insulator substrates such as glass or quartz are very useful in graphene FET fabrication. These substrates bring advantages for RF applications due to their ability to reduce the parasitic substrate capacitance, reducing the RF losses associated with the substrates [23].

Overview of Graphene Transistors
From the above analysis, it is possible to conclude that the fabrication of graphene transistors remains a challenging task. For different purposes, several aspects should be taken into consideration in order to ensure that the best design can be selected. Final performance can be a quantitative means of selecting a GFET solution, but there are other aspects to take into consideration. Table 5 presents, qualitatively, a few parameters that should be taken into consideration while evaluating which GFET to select. Since this type of analysis is always subjective, these are aspects to take into consideration while starting a new design. The definition of the evaluation criteria was based on [63], where a review of the nanofabrication processes was addressed, focusing on the issues experienced when working with graphene. Despite this being applied to biosensors, the issues are the same regarding the other applications (in optics, for example). The increased complexity of RF applications could be supported by works such as those reported in [17] or [32].

Performance Assessment Based on GFET Simulation
Before fabricating new devices or systems, it is highly desirable to have models that can predict the behavior of the devices, allowing, for example, the performance assessment of full electronic systems. Hence, this section will describe how to implement a model for monolayer/bilayer graphene transistors, using different tools, as well as how such a model can be used in DC analysis. Since the reported model describes the intrinsic behavior of the GFET, making the presented analysis valid for DC or low-frequency, adding external parasitic capacitances can further extend the model to specific applications, such as the performance of the GFET in high-frequency applications. The implemented model can be integrated in circuits such as frequency multipliers-a very common application of GFETs, used in many cases to validate the performance of the fabricated GFETs. More complex circuits can be simulated, such as inverters-a very important building block in logic circuits. The implemented model was obtained from [64,65]. In [65], a more detailed explanation is presented regarding the applications of the model. Despite the implemented model being optimized for top-/back-gated GFETs (the more complex GFET topology), it could be easily adapted to the other topologies by removing the parameters of the equation according to the structure (for example, for top-gated devices, removing all of the parameters that refer to the back-gate). This model was implemented in MATLAB, VHDL-AMS in Simplorer, and in Verilog to be used in Virtuoso from Cadence, for example. It should be noted that these models were made available online.

GFET Transfer Characteristic Curve
The general I DS -V GS characteristic curve, when V DS is constant, is shown in Figure 6a. As shown in this figure, the Dirac point is the V GS value were the GFET has its minimum I DS . As will be further shown, this point is obtained by setting V GS0 and V BS0 in Equation (2) (for top-/back-gated graphene transistors). These values are obtained empirically, extracted from the GFET transfer curve of the real device that is intended to be modulated. Figure 6b shows the general output characteristic curves (I DS -V DS ) for a graphene transistor. It is possible to observe two regions in the figure: firstly, the conduction is performed through electrons, when V GS > V 0 with I DS and V DS positive, and secondly, conduction performed by holes, when V GS < V 0 with I DS and V DS negative. The electron conduction is composed of three regions-namely, the triode region, the unipolar saturation region, and the ambipolar saturation region-along with the charge interaction in the channel. For hole-based conduction, these three regions are also present. These DC characteristic curves can be obtained by using the implemented model, which indicates the correct behavior of the model and its ability to be useful, mainly in DC simulations, as will be shown in the next section.
transistor. It is possible to observe two regions in the figure: firstly, the conduction is performed through electrons, when VGS > V0 with IDS and VDS positive, and secondly, conduction performed by holes, when VGS < V0 with IDS and VDS negative. The electron conduction is composed of three regions-namely, the triode region, the unipolar saturation region, and the ambipolar saturation region-along with the charge interaction in the channel. For hole-based conduction, these three regions are also present. These DC characteristic curves can be obtained by using the implemented model, which indicates the correct behavior of the model and its ability to be useful, mainly in DC simulations, as will be shown in the next section.

GFET Simulation Platforms
As was previously mentioned, this model was implemented in MATLAB, VHDL-AMS in Simplorer, and in Verilog to be used in Virtuoso from Cadence. The models are available as Supplementary Material S1. These languages were selected since they are a set of tools widely used by the multidisciplinary research community in this field. Since this paper intends to be used in different areas of research, from electronics to health sciences, the authors consider them to be the most appropriate. MATLAB was chosen because of its wide application in different areas such as nanotechnology or life sciences, allowing the researchers to easily integrate our platform with their models. The selection of VHDL-AMS and Verilog languages (hardware description languages, used to model electronic systems following the proprietary language standardized in IEEE: standard IEEE 1076.1999 for VHDL-AMS, and the IEEE 1364.2001 for Verilog) were selected to provide tools for circuit designers to integrate graphene transistors in their circuits, exploiting the full potential of graphene technology, potentially leading to the development of new devices. In this section, those platforms where the model was implemented will be presented. These models are available in the Supplementary Materials. A small tutorial of how to apply this model is presented. In Figure 7, it is possible to observe the tree interfaces developed under this work.

GFET Simulation Platforms
As was previously mentioned, this model was implemented in MATLAB, VHDL-AMS in Simplorer, and in Verilog to be used in Virtuoso from Cadence. The models are available as Supplementary Material S1. These languages were selected since they are a set of tools widely used by the multidisciplinary research community in this field. Since this paper intends to be used in different areas of research, from electronics to health sciences, the authors consider them to be the most appropriate. MATLAB was chosen because of its wide application in different areas such as nanotechnology or life sciences, allowing the researchers to easily integrate our platform with their models. The selection of VHDL-AMS and Verilog languages (hardware description languages, used to model electronic systems following the proprietary language standardized in IEEE: standard IEEE 1076.1999 for VHDL-AMS, and the IEEE 1364.2001 for Verilog) were selected to provide tools for circuit designers to integrate graphene transistors in their circuits, exploiting the full potential of graphene technology, potentially leading to the development of new devices. In this section, those platforms where the model was implemented will be presented. These models are available in the Supplementary Materials. A small tutorial of how to apply this model is presented. In Figure 7, it is possible to observe the tree interfaces developed under this work. Among the several possible applications of GFETs, one is to use this device as a frequency doubler, due to the V-shaped I-V output characteristic curve of GFETs. To show the correct behavior of the model, a frequency doubler was implemented using Simplorer and Cadence, as shown in Figure 8, where a sinusoidal wave of 1 kHz was used as an input signal. Among the several possible applications of GFETs, one is to use this device as a frequency doubler, due to the V-shaped I-V output characteristic curve of GFETs. To show the correct behavior of the model, a frequency doubler was implemented using Simplorer and Cadence, as shown in Figure 8, where a sinusoidal wave of 1 kHz was used as an input signal.
As can be shown, since the GFET rectifies the input signal, the output signal is a wave with new frequency components-namely, the double frequency. In this way, it is shown that we can use this model to rectify a signal, or as a multiplier.
Despite the graphical aspects related to the model display, which are straightforward in each tool, it is necessary to define a solution to implement the model for each desired GFET (how to set the specific GFET parameters into the model), as well as to define how the calculations will be performed. As can be shown, since the GFET rectifies the input signal, the output signal is a wave with new frequency components-namely, the double frequency. In this way, it is shown that we can use this model to rectify a signal, or as a multiplier.
Despite the graphical aspects related to the model display, which are straightforward in each tool, it is necessary to define a solution to implement the model for each desired GFET (how to set the specific GFET parameters into the model), as well as to define how the calculations will be performed. Figure 9 presents a flowchart of the implemented model of the graphene FET, showing the steps that must be implemented to compute the required voltages and currents. Figure 8a presents the principle of the modeling of the graphene transistors in DC mode. Firstly, the user sets the physical and geometric input parameters. According to this, the next parameters should be provided by the user, such as the electric charge (q), substrate thickness (Hsub), top-gate dielectric thickness (tox), channel width (W), gate length (L), back-gate dielectric constant at the Dirac point (VBS0), top-gate voltage at Dirac point (VGS0), charge density (ntop), critical electric Field (Ec) and electron/hole mobility (µ), back-gate dielectric thickness (Hsub), top-gate dielectric constant (ℇt), series resistance (Rs), and the reduced Planck's constant (h). As soon as the user writes all the necessary data, as a first step, the program must calculate the capacitances and the voltages. After that, a comparison between VGS and V0 (threshold voltage) is performed to select the adequate conduction region, performed by holes or electrons. The surface potential of the channel (Vc) is also calculated. Then, a validation is performed to evaluate in which region the GFET is being operated (as shown in Figure 9b). The variables addressed in the flowchart represented in Figure 9 will be explained in the next section.  As can be shown, since the GFET rectifies the input signal, the output signal is a wave with new frequency components-namely, the double frequency. In this way, it is shown that we can use this model to rectify a signal, or as a multiplier.
Despite the graphical aspects related to the model display, which are straightforward in each tool, it is necessary to define a solution to implement the model for each desired GFET (how to set the specific GFET parameters into the model), as well as to define how the calculations will be performed. Figure 9 presents a flowchart of the implemented model of the graphene FET, showing the steps that must be implemented to compute the required voltages and currents. Figure 8a presents the principle of the modeling of the graphene transistors in DC mode. Firstly, the user sets the physical and geometric input parameters. According to this, the next parameters should be provided by the user, such as the electric charge (q), substrate thickness (Hsub), top-gate dielectric thickness (tox), channel width (W), gate length (L), back-gate dielectric constant at the Dirac point (VBS0), top-gate voltage at Dirac point (VGS0), charge density (ntop), critical electric Field (Ec) and electron/hole mobility (µ), back-gate dielectric thickness (Hsub), top-gate dielectric constant ( ℇ t), series resistance (Rs), and the reduced Planck's constant (h). As soon as the user writes all the necessary data, as a first step, the program must calculate the capacitances and the voltages. After that, a comparison between VGS and V0 (threshold voltage) is performed to select the adequate conduction region, performed by holes or electrons. The surface potential of the channel (Vc) is also calculated. Then, a validation is performed to evaluate in which region the GFET is being operated (as shown in Figure 9b). The variables addressed in the flowchart represented in Figure 9 will be explained in the next section. t), series resistance (Rs), and the reduced Planck's constant (h). As soon as the user writes all the necessary data, as a first step, the program must calculate the capacitances and the voltages. After that, a comparison between V GS and V 0 (threshold voltage) is performed to select the adequate conduction region, performed by holes or electrons. The surface potential of the channel (V c ) is also calculated. Then, a validation is performed to evaluate in which region the GFET is being operated (as shown in Figure 9b). The variables addressed in the flowchart represented in Figure 9 will be explained in the next section.

GFET Model Parameters Computation
After the explanation of use, and about the parameters that can be modified in each model to compute the GFET characteristics, the equations that define the transistors will be presented.
To model the top-/back-gated transistor, it is necessary to compute the capacitances of the device-namely, the effective gate capacitance (Ctop), the back-gate capacitance (Cback), and the channel capacitance, which are dependent on the quantum capacitance (Cq) and the capacitance between gate and channel (Ce). Those parameters are calculated following the expressions in Equation (1) The surface potential of the channel (Vc) depends on the critical electric field (Ec) and the gate length (L), while the threshold voltage (Vo) depends of the gate voltage at the Dirac point (VGS0), the capacitance between the back gate and the channel (Cback), the effective gate capacitance (Ctop), the back-gate voltage at the Dirac point (VBS0) and the backgate voltage (VBS). These relationships are presented in Equation (2): As previously mentioned, to select the region where the graphene FET is being operated, a comparison between the gate voltage (VGS) and the threshold voltage (V0) must be performed. If (VGS > V0), the transistor is working via hole conduction; otherwise, the transistor works in electron conduction. Figure 8b shows the sub-function diagram of the hole conduction and the electron conduction. For both, this function starts with the calculation of VDS-sat1 and VDS-sat2 for the hole conduction and the electron conduction, as shown in Equation (3) [65]:

GFET Model Parameters Computation
After the explanation of use, and about the parameters that can be modified in each model to compute the GFET characteristics, the equations that define the transistors will be presented.
To model the top-/back-gated transistor, it is necessary to compute the capacitances of the device-namely, the effective gate capacitance (C top ), the back-gate capacitance (C back ), and the channel capacitance, which are dependent on the quantum capacitance (C q ) and the capacitance between gate and channel (C e ). Those parameters are calculated following the expressions in Equation (1) [64]: The surface potential of the channel (V c ) depends on the critical electric field (Ec) and the gate length (L), while the threshold voltage (Vo) depends of the gate voltage at the Dirac point (V GS0 ), the capacitance between the back gate and the channel (C back ), the effective gate capacitance (C top ), the back-gate voltage at the Dirac point (V BS0 ) and the back-gate voltage (V BS ). These relationships are presented in Equation (2): As previously mentioned, to select the region where the graphene FET is being operated, a comparison between the gate voltage (V GS ) and the threshold voltage (V 0 ) must be performed. If (V GS > V 0 ), the transistor is working via hole conduction; otherwise, the transistor works in electron conduction. Figure 8b shows the sub-function diagram of the hole conduction and the electron conduction. For both, this function starts with the calculation of V DS-sat1 and V DS-sat2 for the hole conduction and the electron conduction, as shown in Equation (3) [65]: where α = βWµC top R s , with 1 < β < 1.4 as a constant to help in the fitting of real data. The output current is presented in Equation (4) for the different regions [64,65]:

Conclusions
In this paper, an overview of different graphene transistor topologies was presented, looking for the most common gate topologies present in the literature, and taking into consideration the base substrate and the fabrication technology. It was found that topgated transistors are more widely used for applications where the fine control of the graphene channel is required, such as high-frequency applications. Back-gated devices, including the buried gated devices, were found to be widely used for applications in sensors, photodetectors, and biosensors, due to the full exposure of the graphene to the entity that will be transduced. Buried gates are very useful in RF applications, presenting the advantages of top-gated devices while reducing the parasite capacitances, which are a known limiting factor in the RF performance of the devices. The top-/back-gated devices are very useful due to the addition of the possibility of the tuning of the Dirac point by adding a back gate to the top-gated devices, useful to set different transistors for approximately the same work regions at the same voltages, reducing the variability between devices.
Graphene FETs are generally fabricated using Si/SiO 2 as a substrate, due to its advantageous compatibility with standard fabrication processes. Another substrate that is used is SiC, which has the advantage that graphene developed on SiC substrates does not require the transfer steps, and can be used in high-temperature applications. The other types of insulating substrates, such as glass or quartz, have the advantage of allowing a much-reduced parasitic capacitance, which decreases the RF losses associated with the substrates. Regarding the graphene growth, despite the better quality of exfoliated graphene from graphite, CVD-grown graphite is the preferred method, since it has a good quality and enables the growth of large areas, being suitable for large-scale fabrication, while the epitaxial graphene grown on SiC remains expensive. Thus, it is possible to conclude that the fabrication of graphene transistors remains challenging. For different purposes, several aspects should be taken into consideration in order that the best design can be selected. In general, for RF applications, top-gated transistors or buried gates are preferable, since they enable better control of the graphene's channel. For sensors (biosensors and photodetectors), the most common topology reported in the literature is back-gated devices, due to the existence of an exposed graphene gate owing to its easy functionalization, as well as allowing for liquid top-gated devices.
Finally, this paper presents a tutorial to be used in simulation tools and to allow the performance assessment of GFETs using a model of graphene transistors using MATLAB, VHDL-AMS, and Verilog. Those models are available in the Supplementary Materials to be used in MATLAB, Simplorer, and Virtuoso from Cadence.