Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage

This study proposes negative capacitance vacuum channel transistors. The proposed negative capacitance vacuum channel transistors in which a ferroelectric capacitor is connected in series to the gate of the vacuum channel transistors have the following two advantages: first, adding a ferroelectric capacitor in series with a gate capacitor makes the turn-on voltage lower and on–off transition steeper without causing hysteresis effects. Second, the capacitance matching between a ferroelectric capacitor and a vacuum channel transistor becomes simplified because the capacitance of a vacuum channel transistor as seen from a ferroelectric capacitor is constant.


Introduction
Over the past 60 years of the semiconductor industry, the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) has been scaled down obeying Moore's law: feature sizes of transistors are scaled at a rate of approximately 0.7 times every 18 months. As the semiconductor market size increases, its applications extend beyond consumer electronics, extending, for example, to transistors, microchips, solar cells, and light-emitting diodes. Recently, electronic devices have faced burgeoning demand from aerospace and extreme-environment applications. For example, in the case of aerospace applications, many kinds of challenges from harsh environments exist. Extremely low and high temperature and high levels of cosmic ray and radiation lead to catastrophic damage to the electronic systems without proper shielding packages. Unfortunately, it is well-known that MOSFETs, which are the most widely used electronic devices, are difficult to use for these applications because they are vulnerable to radiation and temperature [1][2][3][4][5][6][7][8][9][10][11]. Even if state-of-the-art shielding methods can protect MOSFETs from harsh environments, the following issues still remain: large volume, large weight, high power consumption, and complex system design.
Thus, as an alternative, a vacuum channel transistor has been proposed, which replaces the semiconductor channel with a vacuum channel. Owing to the unique properties of a vacuum channel, vacuum channel transistors are robust even if they are exposed to radiation and high or low temperatures [12]. Furthermore, it is well-known that a vacuum environment is superior to a solid one in terms of carrier transport because ballistic transport is feasible in the former while the latter experiences various scattering mechanisms, such as lattice vibration scattering, ionized impurity scattering, surface roughness scattering, etc. [13]. For example, the electron velocities in vacuum and silicon are theoretically 3 × 10 10 cm/s and~10 7 cm/s. Thus, vacuum channel transistors have the potential to implement higher performance and power gain than MOSFETs. In spite of the above-mentioned advantages, vacuum channel transistors experience a high operating voltage (V DD ) [14], which is due to their current flowing mechanism: Fowler-Nordheim tunneling, where electrons tunnel through the barrier in the presence of a high electric field [15,16]. Because Fowler-Nordheim tunneling makes electrons tunnel through a rounded triangular barrier generated at the source-to-channel junction, electrons tunnel from the source tip into the vacuum channel with a positive drain voltage (V D ) when the gate voltage (V G ) exceeds the turn-on voltage. In the case of the optimized vacuum channel transistors, an insulated-gate structure with a pyramidal source and a flat drain is introduced to boost the on-current (I on ) and gate controllability by increasing the local electric field [17,18]. However, despite the optimization and downscaling of vacuum channel transistors, their V DD is still higher than that of MOSFETs, which makes them hard to utilize in low-power extreme-environment applications.
In this paper, for a low V DD , a negative capacitance vacuum channel transistor is proposed for the first time, as shown in Figure 1a. The gate of a vacuum channel transistor is connected to a ferroelectric capacitor to combine the advantages of vacuum channel transistors with negative capacitance. The negative capacitance effects of ferroelectric materials have recently been exploited to induce internal voltage gain out of the gate stack [19]. The underlying physics for an abrupt on-off switching operation of a negative capacitance transistor is the passive amplification of the gate voltage at the interface between the FE gate oxide and the semiconductor channel. Essentially, the charge balance between the series-connected ferroelectric and linear positive capacitor induces a depolarization field and stabilizes the ferroelectric capacitor at a negative capacitance state that in turn amplifies the surface potential of the electron device. It has been reported that there are two important aspects of a negative capacitance transistor: amplification and stabilization. The differential amplification of the gate voltage at the interface between the surface channel and the gate oxide makes the on-off transition of a negative capacitance transistor more abrupt. On the other hand, negative capacitance is unstable by nature. Thus, the positive capacitances can stabilize the ferroelectric in its negative capacitance state, leading to a stable voltage amplification. Conventionally, a metallic layer is located between the gate and vacuum channel transistor to average out the nonuniform potential profile along the source-drain direction and the charge nonuniformity coming from domain formation in the ferroelectric. It makes the single-domain Landau-Khalatnikov (LK) equation valid. The influence of the internal voltage gain stemming from negative capacitance has also been recently confirmed in the case of polymer ferroelectric bulk MOSFETs [20][21][22][23], negative capacitance finFETs [24][25][26], and negative capacitance nanoelectromechanical (NEM) relays [27]. This manuscript is the first application of negative capacitance to vacuum channel transistors whose channel is vacuum rather than semiconductor.
The proposed negative capacitance vacuum channel transistors have the following two benefits: first, adding a ferroelectric capacitor in series with a gate dielectric capacitor makes the turn-on voltage lower and on-off transition more abrupt without causing unwanted hysteresis effects. Second, the capacitance matching between a ferroelectric capacitor and a vacuum channel transistor is simplified because the capacitance of a vacuum channel transistor as seen from a ferroelectric capacitor is constant. When a vacuum channel transistor is connected to ferroelectric materials, the capacitance matching between the ferroelectric-layer (C FE ) and the vacuum channel transistor (C VCT ) is important. As capacitance matching is improved, the subthreshold swing (SS) and transconductance of vacuum channel transistors improve, which leads to a lower V DD [28]. For the optimized matching condition, C VCT −1 + C FE −1 needs to be made as small as possible while maintaining positive values for all charges to minimize SS and avoiding hysteresis effects: [20], where Q G is the gate charge. However, in the case of MOSFETs, their gate capacitance is dependent on bias conditions, which makes the capacitance matching of negative capacitance MOSFETs difficult [29]. For example, as V G increases, the gate capacitance of n-channel MOSFETs increases nonlinearly from the subthreshold to a strong inversion. In contrast, the capacitance matching of negative capacitance vacuum channel transistors is expected to be simplified and stable because there is no semiconductor channel region. The ferroelectric capacitor in standalone condition cannot show the negative capacitance behavior because to stabilize the total system, it is necessary to introduce a series combination of a ferroelectric capacitor and a linear positive capacitor connected to a voltage source. The C VCT remains constant regardless of the Q G , because the Q G of the vacuum channel transistors increases linearly with the increment of the back-gate voltage (V BG ). The advantages of negative capacitance vacuum channel transistors are discussed in detail in the following section.
advantages of negative capacitance vacuum channel transistors are discussed in detail in the following section.  Figure 1b summarizes the simulation procedure of the negative capacitance vacuum channel transistors. First, the drain current (ID) and QG of vacuum channel transistors are calculated as a function of VBG using a commercial three-dimensional technology computer-aided design (TCAD) simulator [30]. The simulation models include band-to-band tunneling, Fowler-Nordheim tunneling, Fermi distribution, Shockley-Read-Hall (SRH) recombination, and dynamic nonlocal tunneling models. HfSiO and SiO2 are used as ferroelectric and gate dielectric materials, respectively. The work function of the back-gate, source, and drain is 4.32 eV, which corresponds to that of tungsten. The physical parameters of the simulated negative capacitance vacuum channel transistors are as follows: the channel (tch) and oxide thickness (tox) are 15 nm and 5 nm, respectively. The source length (LS), channel length (Lch), and channel width (Wch) are 200 nm, 10 nm, and 30 nm, respectively. Parasitic capacitance components of vacuum channel transistors are included in the TCAD simulation, while the leakage through the ferroelectric layer is ignored for concise discussion. Second, to derive the voltage drop (VFE) and capacitance (CFE) across the ferroelectric capacitor, the LK equation is coupled with TCAD simulation using Equations (1) and (2) [20].  Figure 1b summarizes the simulation procedure of the negative capacitance vacuum channel transistors. First, the drain current (I D ) and Q G of vacuum channel transistors are calculated as a function of V BG using a commercial three-dimensional technology computer-aided design (TCAD) simulator [30]. The simulation models include band-to-band tunneling, Fowler-Nordheim tunneling, Fermi distribution, Shockley-Read-Hall (SRH) recombination, and dynamic nonlocal tunneling models. HfSiO and SiO 2 are used as ferroelectric and gate dielectric materials, respectively. The work function of the back-gate, source, and drain is 4.32 eV, which corresponds to that of tungsten. The physical parameters of the simulated negative capacitance vacuum channel transistors are as follows: the channel (t ch ) and oxide thickness (t ox ) are 15 nm and 5 nm, respectively. The source length (L S ), channel length (L ch ), and channel width (W ch ) are 200 nm, 10 nm, and 30 nm, respectively. Parasitic capacitance components of vacuum channel transistors are included in the TCAD simulation, while the leakage through the ferroelectric layer is ignored for concise discussion. Second, to derive the voltage drop (V FE ) and capacitance (C FE ) across the ferroelectric capacitor, the LK equation is coupled with TCAD simulation using Equations (1) and (2) [20].

Simulation Method
where α 0 , β 0 , and γ 0 refer to the Landau coefficients of HfSiO (α 0 = −1.73 × 10 9 m/F, β 0 = 7.68 × 10 10 m 5 /F/C 2 , and γ 0 = 0 m 9 /F/C 4 , as presented in [31]). The value of α 0 is negative for all known ferroelectric materials below Curie temperature, which leads to hysteretic characteristics of ferroelectrics. It shows the double-well shape of free energy for negative capacitance behavior of ferroelectric capacitors. t FE is the ferroelectric layer thickness. Equations (1) and (2) calculate V FE and C FE by using Q G values obtained in the first step. Finally, the calculated V FE is added to V BG to obtain V G , as shown in Figure 1a.
Then, simulated I D vs. V G and I D vs. V D curves of negative capacitance vacuum channel transistors are generated. Figure 2 shows the I D vs. V BG and I D vs. V D curves of a vacuum channel transistor, which corresponds to negative capacitance vacuum channel transistors without ferroelectric capacitors. The output curves in Figure 2b show the typical current vs. voltage characteristics of Fowler-Nordheim tunneling. Thus, V BG rather than V G controls the vacuum channel transistor. As previously reported, the dominant carrier transport mechanisms of vacuum channel transistors are Fowler-Nordheim tunneling and thermionic emission [13], as shown in Figure 3. In the case of vacuum channel transistors, the semiconductor channel is replaced with a vacuum channel. In the case of MOSFETs, carriers stored in the source region are injected into the semiconductor channel region by lowering the energy barrier height using the V G . Then, the carriers move from the source into the semiconductor channel using thermionic emission: high-energy carriers following the Fermi-Dirac distribution are injected over the energy barrier. Subsequently, the carriers move along the channel while experiencing scattering events, which are described by a carrier mobility. On the contrary, in the case of vacuum channel transistors, the carriers stored in the source need to overcome the energy barrier between the source and vacuum channel. Fowler-Nordheim tunneling is a more viable option than thermionic emission, because the vacuum level is significantly higher than the energy level of the semiconductor. Once the V BG is high enough to narrow the source-to-channel barrier width, the source carriers begin to be injected into the channel region. After the injection, the carriers drift through the channel into the drain without experiencing scattering events analogous to ballistic transport in extremely short-channel semiconductor MOSFETs. During this process, vacuum channel transistors generally experience a high V DD . For efficient source carrier injection, the electric field or energy band bending near the source-to-channel junction must be increased. To meet this condition, the source tip is sharpened, as shown in Figure 1a, and a multiple-gate structure is introduced. However, these geometrical approaches are insufficient to obtain a dramatic reduction in V DD and SS. Thus, the introduction of a ferroelectric capacitor is helpful for alleviating the weal spots of vacuum channel transistors.      In Figure 2, the threshold voltage (V T ) extracted by the linear extrapolation method is~7.7 V at V D = 5 V. Even if V G increases up to 10 V, I D only reaches~3 nA per source tip. Then, ferroelectric materials such as HfSiO are connected in series with the back-gate stack of negative capacitance vacuum channel transistors whose polarization (P) vs. electric field across a ferroelectric layer (E FE ) curve is shown in Figure 4. On the Landau curve, the operating points corresponding to V D = 5 V and V G = −5-10 V are shown. If the operating point is located at A, it lowers the gate voltage (V G = V BG + V FE ) required to reach the same value of I D . This leads to a higher I on and lower turn-on voltage. At operating point B, E FE is still positive, which means that V BG is negative even when V G = 0 V. This leads to a lower off-current (I off ).

Simulation Results
Micromachines 2020, 9, x 6 of 11 In Figure 2, the threshold voltage (VT) extracted by the linear extrapolation method is ~7.7 V at VD = 5 V. Even if VG increases up to 10 V, ID only reaches ~3 nA per source tip. Then, ferroelectric materials such as HfSiO are connected in series with the back-gate stack of negative capacitance vacuum channel transistors whose polarization (P) vs. electric field across a ferroelectric layer (EFE) curve is shown in Figure 4. On the Landau curve, the operating points corresponding to VD = 5 V and VG = −5-10 V are shown. If the operating point is located at A, it lowers the gate voltage (VG = VBG + VFE) required to reach the same value of ID. This leads to a higher Ion and lower turn-on voltage. At operating point B, EFE is still positive, which means that VBG is negative even when VG = 0 V. This leads to a lower off-current (Ioff).  Figure 5 shows the influence of the ferroelectric capacitor on the transfer and output curves of negative capacitance vacuum channel transistors with the variation of tFE. This clearly shows the performance boosting of negative capacitance vacuum channel transistors as tFE increases. The surface potential of vacuum channel transistors can be higher than the applied VG, resulting in negative capacitance effects of the ferroelectric material. As tFE increases, turn-on voltage decreases, Ion increases, and SS improves. Among the values of tFE, 60 nm is considered to be an optimal value because minimal SS is achieved without hysteresis effects, whereas turn-on voltage is < 1 V. If tFE exceeds 60 nm, the hysteresis operation featuring S-shaped transfer curves becomes more pronounced.  Figure 5 shows the influence of the ferroelectric capacitor on the transfer and output curves of negative capacitance vacuum channel transistors with the variation of t FE . This clearly shows the performance boosting of negative capacitance vacuum channel transistors as t FE increases. The surface potential of vacuum channel transistors can be higher than the applied V G , resulting in negative capacitance effects of the ferroelectric material. As t FE increases, turn-on voltage decreases, I on increases, and SS improves. Among the values of t FE , 60 nm is considered to be an optimal value because minimal SS is achieved without hysteresis effects, whereas turn-on voltage is <1 V. If t FE exceeds 60 nm, the hysteresis operation featuring S-shaped transfer curves becomes more pronounced.

Discussion
For more detailed analysis, Figure 6a and b shows QG vs. VBG and CVCT vs. QG of vacuum channel transistors. It should be noted that CVCT remains constant regardless of bias conditions unlike negative capacitance MOSFETs. Although CFE is a nonlinear function of QG, it can be matched with CVCT around zero QG. It means that perfect capacitance matching between CVCT and CFE is easier in the case of negative capacitance vacuum channel transistors than negative capacitance MOSFETs: minimizing SS without causing hysteresis effects as shown in Figure 7a,b. Considering the equivalent capacitance model in Figure 1a, the body factor (m) of negative capacitance vacuum channel transistors can be expressed as [19] which determines the coupling between the CVCT and CFE. For the minimization of m without hysteresis effects, the following two requirements must be met: first, total capacitance (Ctotal) should remain positive in the entire range of operation; Ctotal −1 = CFE −1 + CVCT −1 ≥ 0, which means CVCT −1 ≥ −CFE −1 [22]. Second, Ctotal −1 should be made as small as possible [20]. As shown in Figure 7a, as CVCT −1 ,

Discussion
For more detailed analysis, Figure 6a,b shows Q G vs. V BG and C VCT vs. Q G of vacuum channel transistors. It should be noted that C VCT remains constant regardless of bias conditions unlike negative capacitance MOSFETs. Although C FE is a nonlinear function of Q G , it can be matched with C VCT around zero Q G . It means that perfect capacitance matching between C VCT and C FE is easier in the case of negative capacitance vacuum channel transistors than negative capacitance MOSFETs: minimizing SS without causing hysteresis effects as shown in Figure 7a,b. Considering the equivalent capacitance model in Figure 1a, the body factor (m) of negative capacitance vacuum channel transistors can be expressed as [19] which determines the coupling between the C VCT and C FE . For the minimization of m without hysteresis effects, the following two requirements must be met: first, total capacitance (C total ) should remain positive in the entire range of operation; C total −1 = C FE −1 + C VCT −1 ≥ 0, which means [22]. Second, C total −1 should be made as small as possible [20]. As shown in Figure 7a, as C VCT −1 , which is independent of Q G , decreases down to C FE −1 , the gap between C VCT −1 and C FE −1 becomes narrower, which leads to a reduced SS. For example, in Figure 7a, the value of C VCT −1 is constant: 1.04 cm 2 /µF. In contrast, when V G is 0.4 V and t FE is 60 nm, the value of −C FE −1 is 1.03 cm 2 /µF.
This implies that m = 0 is feasible by adjusting t FE . Thus, Figure 5 shows that the increase in I D is steepest near V G = 0.4 V when t FE is optimized to 60 nm. Figure 7b shows the relationship between C VCT −1 C −1 FE and Q G with the variation of t FE . As t FE becomes greater than 60 nm, −C FE −1 exceeds C VCT −1 near Q G = 0, making two intersections, which lead to hysteresis effects or the S shape of the transfer curves. On the contrary, if t FE becomes less than 60 nm, and −C FE −1 becomes less than C VCT −1 for all QGs. Even if no hysteresis effect is observed, SS reduction is limited. Figure 8 shows the SS vs. I D curves under the three t FE conditions. As t FE increases, SS decreases. If I D is fixed at 10 −9 nA, SS becomes 118 mV/dec, 74 mV/dec, and 25 mV/dec at t FE = 0 nm, 30 nm, and 60 nm, respectively. As shown in Figure 5, the 60-nm-t FE case shows minimal SS without causing hysteresis effects.
Micromachines 2020, 9, x 8 of 11 which is independent of QG, decreases down to CFE −1 , the gap between CVCT −1 and CFE −1 becomes narrower, which leads to a reduced SS. For example, in Figure 7a, the value of CVCT −1 is constant: 1.04 cm 2 /μF. In contrast, when VG is 0.4 V and tFE is 60 nm, the value of −CFE −1 is 1.03 cm 2 /μF. This implies that m = 0 is feasible by adjusting tFE. Thus, Figure 5 shows that the increase in ID is steepest near VG = 0.4 V when tFE is optimized to 60 nm. Figure 7b shows the relationship between CVCT −1 1 FE C − and QG with the variation of tFE. As tFE becomes greater than 60 nm, −CFE −1 exceeds CVCT −1 near QG = 0, making two intersections, which lead to hysteresis effects or the S shape of the transfer curves. On the contrary, if tFE becomes less than 60 nm, and −CFE −1 becomes less than CVCT −1 for all QGs. Even if no hysteresis effect is observed, SS reduction is limited. Figure 8 shows the SS vs. ID curves under the three tFE conditions. As tFE increases, SS decreases. If ID is fixed at 10 −9 nA, SS becomes 118 mV/dec, 74 mV/dec, and 25 mV/dec at tFE = 0 nm, 30 nm, and 60 nm, respectively. As shown in Figure 5, the 60-nm-tFE case shows minimal SS without causing hysteresis effects.

Conclusions
In this paper, the low-voltage operation of negative capacitance vacuum channel transistors are simulated using the unique property of ferroelectric materials. In addition, a negative capacitance effect is achieved for abrupt on-off transition without causing hysteresis effects through capacitance matching to stabilize the total system. The ferroelectric capacitor can amplify the V BG , the SS can be lowered, and the I D vs. V G curve steepens. The operation voltage can be lowered below 1 V at the 60-nm thickness HfSiO without showing hysteresis behavior. The Q G of the vacuum channel transistor is constantly increased as V BG increases, and C VCT is constant as Q G increases. Thus, the negative capacitance vacuum channel transistor is relatively simple to match the vacuum channel transistor capacitance and ferroelectric capacitance. Therefore, the SS characteristic is better because the difference between C VCT −1 and −C FE −1 is reduced compared to the solid-state device with fluctuating gate capacitance.
Thus, the SS of the negative capacitance vacuum channel transistor could be approximately 20 mV/dec. In this paper, the negative capacitance vacuum channel transistor has been proven to be an important position in industrial applications.