Compact 20-W GaN Internally Matched Power Amplifier for 2.5 GHz to 6 GHz Jammer Systems.

In this paper, we demonstrate a compact 20-W GaN internally matched power amplifier for 2.5 to 6 GHz jammer systems which uses a high dielectric constant substrate, single-layer capacitors, and shunt/series resistors for low-Q matching and low-frequency stabilization. A GaN high-electron-mobility transistor (HEMT) CGH60030D bare die from Wolfspeed was used as an active device, and input/output matching circuits were implemented on two different substrates using a thin-film process, relative dielectric constants of which were 9.8 and 40, respectively. A series resistor of 2.1 Ω was chosen to minimize the high-frequency loss and obtain a flat gain response. For the output matching circuit, double λ/4 shorted stubs were used to supply the drain current and reduce the output impedance variation of the transistor between the low-frequency and high-frequency regions, which also made wideband matching feasible. Single-layer capacitors effectively helped reduce the size of the matching circuit. The fabricated GaN internally matched power amplifier showed a linear gain of about 10.2 dB, and had an output power of 43.3-43.9 dBm (21.4-24.5 W), a power-added efficiency of 33.4%-49.7% and a power gain of 6.2-8.3 dB at the continuous-wave output power condition, from 2.5 to 6 GHz.


Introduction
GaN high-electron-mobility transistor (HEMT) wideband power amplifiers have been studied for multi-mode communication systems, electronic warfare systems, and other frequency-agile systems that required high-power operation over a wide frequency range [1][2][3][4][5][6][7][8][9][10]. While the transistor gain decreases with the frequency, a wideband power amplifier requires a flat gain performance in the interested bandwidth. In addition, the inherent reactance of the transistor, mainly due to its drain-to-source capacitance, limits the frequency bandwidth of the power amplifier as the Bode-Fano gain-bandwidth product describes [11,12]. To overcome this limitation, a multiple inductor-capacitor (LC) ladder configuration may be a proper choice, but it is area-inefficient and degrades the cost competitiveness, especially for expensive GaN monolithic microwave integrated circuits.
In this paper, we present a compact 20-W internally matched power amplifier for 2.5 to 6 GHz electronic warfare jammer applications which uses a GaN HEMT device and can be integrated into a small metal package. The novelty of this work originates in a practical combination of a series resistor, a shunt resistor-capacitor (RC)sub-circuit, a high dielectric constant matching substrate, and single-layer capacitors to maximize the size reduction effect. Input and output matching circuits for the power amplifier are implemented on two different thin-film substrates with the relative dielectric constants of 9.8 and 40, and, as a part of the matching circuit, single-layer capacitors and thin-film shunt/series resistors are utilized to achieve the circuit stabilization and flat gain, in addition to its compact size.
shunt/series resistors are utilized to achieve the circuit stabilization and flat gain, in addition to its compact size.

Device Description
The GaN HEMT bare die with the 0.4 μm gate length (CGH60030D, Wolfspeed, Inc., Research Triangle Park, NC, USA) that is provided by Wolfspeed has a typical power density of 4.5 W/mm and a maximum output power of 30 W at the drain pad and is applicable up to 6 GHz. Considering the loss of the matching circuit itself and the impedance mismatch loss, CGH60030D is a proper choice for the output power of more than 20 W from 2.5 to 6 GHz. Figure 1 and Table 1 show the photograph and device parameters of CGH60030D [13]. The transistor bare die consists of two 10 × 360 μm cells and has four pads on the gate and drain sides. Because the large-signal model provided by the manufacturer has only two ports for the gate and drain pads, it is difficult to fully include the bonding wire effect and the phase balance on each pad. In our work, we use a modified large-signal model combining the transistor unit cell model, which is based on the manufacturer's foundry process, with three-dimensional electromagnetic simulation models of the gate/drain pads and bonding wires [14,15]. Figure 2 shows the modified large-signal transistor model, the port reference planes of which are on the middle of its gate and drain pads to consider practical wire bonding effects effectively.

Parameters
Specifications operating frequency DC − 6 GHz  shunt/series resistors are utilized to achieve the circuit stabilization and flat gain, in addition to its compact size.

Device Description
The GaN HEMT bare die with the 0.4 μm gate length (CGH60030D, Wolfspeed, Inc., Research Triangle Park, NC, USA) that is provided by Wolfspeed has a typical power density of 4.5 W/mm and a maximum output power of 30 W at the drain pad and is applicable up to 6 GHz. Considering the loss of the matching circuit itself and the impedance mismatch loss, CGH60030D is a proper choice for the output power of more than 20 W from 2.5 to 6 GHz. Figure 1 and Table 1 show the photograph and device parameters of CGH60030D [13]. The transistor bare die consists of two 10 × 360 μm cells and has four pads on the gate and drain sides. Because the large-signal model provided by the manufacturer has only two ports for the gate and drain pads, it is difficult to fully include the bonding wire effect and the phase balance on each pad. In our work, we use a modified large-signal model combining the transistor unit cell model, which is based on the manufacturer's foundry process, with three-dimensional electromagnetic simulation models of the gate/drain pads and bonding wires [14,15]. Figure 2 shows the modified large-signal transistor model, the port reference planes of which are on the middle of its gate and drain pads to consider practical wire bonding effects effectively.

Parameters
Specifications operating frequency DC − 6 GHz

Input and Output Matching Circuit Design
We simulated the GaN HEMT under the bias conditions of V DS = 28 V and I DS = 250 mA, and predicted small-signal input impedances at 2.5 GHz and 6 GHz as Z S,2.5 GHz = 1.39 + j2.11 Ω and Z S,6 GHz = 0.89 + j0.11 Ω. Because the transistor was unstable below 7.9 GHz, we performed source-pull and load-pull simulations after stabilizing the transistor with shunt and series resistors. With the drain pad effect eliminated, the transistor was simulated up to the third harmonic by a load-pull tuner [16,17]. The simulation results showed that the optimum load impedances at 2.5 GHz and 6 GHz were Z L,2.5 GHz = 8.00 + j4.91 Ω and Z L,6 GHz = 5.41 + j3.86 Ω, respectively. Figure 3 shows a schematic circuit diagram of the GaN HEMT with the stabilization circuit. To secure the low-frequency stability of the transistor and apply the gate bias voltage through the resistor, the shunt circuit of the resistor R BIAS and the capacitor C Bypass was inserted between the transistor and the input matching circuit. The element values of the shunt circuit were determined to be C Bypass = 39 pF and R BIAS = 36 Ω to simultaneously achieve stability and low loss.
We simulated the GaN HEMT under the bias conditions of VDS = 28 V and IDS = 250 mA, and predicted small-signal input impedances at 2.5 GHz and 6 GHz as ZS,2.5 GHz = 1.39 + j2.11 Ω and ZS,6 GHz = 0.89 + j0.11 Ω. Because the transistor was unstable below 7.9 GHz, we performed source-pull and load-pull simulations after stabilizing the transistor with shunt and series resistors. With the drain pad effect eliminated, the transistor was simulated up to the third harmonic by a load-pull tuner [16,17]. The simulation results showed that the optimum load impedances at 2.5 GHz and 6 GHz were ZL,2.5 GHz = 8.00 + j4.91 Ω and ZL,6 GHz = 5.41 + j3.86 Ω, respectively. Figure 3 shows a schematic circuit diagram of the GaN HEMT with the stabilization circuit. To secure the low-frequency stability of the transistor and apply the gate bias voltage through the resistor, the shunt circuit of the resistor RBIAS and the capacitor CBypass was inserted between the transistor and the input matching circuit. The element values of the shunt circuit were determined to be CBypass = 39 pF and RBIAS = 36 Ω to simultaneously achieve stability and low loss.
Because the high-frequency gain of the transistor is typically lower than its low-frequency gain, the high-frequency loss of the stabilization circuit should be lower than the circuit's low-frequency loss. However, because the input impedance of the transistor is very low, low-loss impedance matching is very difficult in a wide frequency range only with the simple matching circuit of a few LC elements. To compromise the low loss and compact size, we used a titanate substrate with the high relative dielectric constant of 40, and applied a series resistor of RS = 2.1 Ω which made the stability factor k more than 1 and a flat gain in the interested bandwidth by increasing the lowfrequency loss and reducing the high-frequency loss.  Figure 4 shows the variation of the stability factor k, maximum available gain (Gmax), and input impedance before and after the insertion of the series resistor RS. As the dotted impedance trace on the Smith chart in Figure 4 implies, the titanate substrate and bonding wires spread the input impedance trace of the transistor greatly in both of the low-frequency region and the high-frequency region, which maintains the low-frequency impedance as very low, and moves the high-frequency impedance to a high-value region. Therefore, a small series resistor greatly reduces the low-frequency gain, and, by contrast, does not affect the high-frequency gain because of the frequency-dependent voltage-dividing ratio. Because the high-frequency gain of the transistor is typically lower than its low-frequency gain, the high-frequency loss of the stabilization circuit should be lower than the circuit's low-frequency loss. However, because the input impedance of the transistor is very low, low-loss impedance matching is very difficult in a wide frequency range only with the simple matching circuit of a few LC elements. To compromise the low loss and compact size, we used a titanate substrate with the high relative dielectric constant of 40, and applied a series resistor of R S = 2.1 Ω which made the stability factor k more than 1 and a flat gain in the interested bandwidth by increasing the low-frequency loss and reducing the high-frequency loss. Figure 4 shows the variation of the stability factor k, maximum available gain (G max ), and input impedance before and after the insertion of the series resistor R S . As the dotted impedance trace on the Smith chart in Figure 4 implies, the titanate substrate and bonding wires spread the input impedance trace of the transistor greatly in both of the low-frequency region and the high-frequency region, which maintains the low-frequency impedance as very low, and moves the high-frequency impedance to a high-value region. Therefore, a small series resistor greatly reduces the low-frequency gain, and, by contrast, does not affect the high-frequency gain because of the frequency-dependent voltage-dividing ratio. Micromachines 2020, 11, 375 4 of 10  Figure 5 shows the output matching circuit that is tuned to the optimum load impedance. Double λ/4 shorted stubs were used for a DC drain current supply and had an LC-parallel resonator effect at the center frequency, thus reducing the variation of the transistor's output impedance trace and facilitating wideband impedance-matching within a low-Q region on the Smith chart [18,19]. Figure 6 shows the variation of the output impedance trace before and after the insertion of the λ/4 shorted stubs. The output impedance trace was extracted as we saw the drain of the transistor at the bias line position. A single-layer capacitor followed the λ/4 shorted stubs, which resulted in the size reduction of the output matching circuit, although multiple thin-film substrates complicated the assembly process a little. A cascaded low-pass LC network was used for fine tuning of the desired output impedance, and was implemented on an alumina substrate.  Figure 5 shows the output matching circuit that is tuned to the optimum load impedance. Double λ/4 shorted stubs were used for a DC drain current supply and had an LC-parallel resonator effect at the center frequency, thus reducing the variation of the transistor's output impedance trace and facilitating wideband impedance-matching within a low-Q region on the Smith chart [18,19]. Figure 6 shows the variation of the output impedance trace before and after the insertion of the λ/4 shorted stubs. The output impedance trace was extracted as we saw the drain of the transistor at the bias line position. A single-layer capacitor followed the λ/4 shorted stubs, which resulted in the size reduction of the output matching circuit, although multiple thin-film substrates complicated the assembly process a little. A cascaded low-pass LC network was used for fine tuning of the desired output impedance, and was implemented on an alumina substrate. Figure 7 shows a schematic circuit diagram of the designed power amplifier, exemplary input/output impedance matching traces at 4 GHz, and the designed load impedance trace seen from the drain of the transistor. The input impedance was not well matched because of the very low input impedance of the transistor. On the other hand, the output impedance showed a reasonably good matching. To improve the input matching condition, we should use lossy matching or multiple LC matching techniques, but the former degrades the gain performance, and the latter increases the circuit size. An insufficient gain margin makes it difficult to choose lossy matching, and the large circuit size makes compact integration into a small standard metal package infeasible. Therefore, the input matching properly compromised with the size of the input matching circuit because the input mismatch could be improved with the use of the balanced amplifier configuration [20][21][22].  Figure 5 shows the output matching circuit that is tuned to the optimum load impedance. Double λ/4 shorted stubs were used for a DC drain current supply and had an LC-parallel resonator effect at the center frequency, thus reducing the variation of the transistor's output impedance trace and facilitating wideband impedance-matching within a low-Q region on the Smith chart [18,19]. Figure 6 shows the variation of the output impedance trace before and after the insertion of the λ/4 shorted stubs. The output impedance trace was extracted as we saw the drain of the transistor at the bias line position. A single-layer capacitor followed the λ/4 shorted stubs, which resulted in the size reduction of the output matching circuit, although multiple thin-film substrates complicated the assembly process a little. A cascaded low-pass LC network was used for fine tuning of the desired output impedance, and was implemented on an alumina substrate.   Figure 7 shows a schematic circuit diagram of the designed power amplifier, exemplary input/output impedance matching traces at 4 GHz, and the designed load impedance trace seen from the drain of the transistor. The input impedance was not well matched because of the very low input impedance of the transistor. On the other hand, the output impedance showed a reasonably good matching. To improve the input matching condition, we should use lossy matching or multiple LC matching techniques, but the former degrades the gain performance, and the latter increases the circuit size. An insufficient gain margin makes it difficult to choose lossy matching, and the large circuit size makes compact integration into a small standard metal package infeasible. Therefore, the input matching properly compromised with the size of the input matching circuit because the input mismatch could be improved with the use of the balanced amplifier configuration [20][21][22].   Figure 7 shows a schematic circuit diagram of the designed power amplifier, exemplary input/output impedance matching traces at 4 GHz, and the designed load impedance trace seen from the drain of the transistor. The input impedance was not well matched because of the very low input impedance of the transistor. On the other hand, the output impedance showed a reasonably good matching. To improve the input matching condition, we should use lossy matching or multiple LC matching techniques, but the former degrades the gain performance, and the latter increases the circuit size. An insufficient gain margin makes it difficult to choose lossy matching, and the large circuit size makes compact integration into a small standard metal package infeasible. Therefore, the input matching properly compromised with the size of the input matching circuit because the input mismatch could be improved with the use of the balanced amplifier configuration [20][21][22].   Figure 8 shows a fabricated internally matched power amplifier. Input and output matching circuits were implemented on alumina substrates and a titanate substrate using a thin-film process [23]. The GaN HEMT bare die was attached onto a CPC (Cu/Mo70Cu/Cu) carrier with high thermal conductivity using an AuSn (80/20) eutectic process. The complete circuit occupied 9.9 mm × 6.8 mm on the carrier. The GaN HEMT bare die, single-layer capacitors, input/output matching circuits, and microstrip feed lines on RO4003C (Rogers Corporation, Chandler, AZ, USA) for microwave testing were interconnected by 1 mil Au wedge bonding wires. Figure 8. Fabricated internally matched power amplifier using a GaN HEMT bare die, input/output thin-film matching substrates, and single-layer capacitors (circuit area = 9.9 mm × 6.8 mm).

Power Amplifier Measurement
The fabricated power amplifier was measured on a heat-sinking jig under the bias conditions of VDS = 28 V and IDS = 250 mA. The measured S-parameter data were compared with the simulated data in Figure 9. The measured results showed a linear gain of more than 10.2 dB and a return loss of more than 2.3 dB from 2.5 to 6 GHz. The low-frequency gain decreased slightly, and the roll-off of the high-  Figure 8 shows a fabricated internally matched power amplifier. Input and output matching circuits were implemented on alumina substrates and a titanate substrate using a thin-film process [23]. The GaN HEMT bare die was attached onto a CPC (Cu/Mo70Cu/Cu) carrier with high thermal conductivity using an AuSn (80/20) eutectic process. The complete circuit occupied 9.9 mm × 6.8 mm on the carrier. The GaN HEMT bare die, single-layer capacitors, input/output matching circuits, and microstrip feed lines on RO4003C (Rogers Corporation, Chandler, AZ, USA) for microwave testing were interconnected by 1 mil Au wedge bonding wires.  Figure 8 shows a fabricated internally matched power amplifier. Input and output matching circuits were implemented on alumina substrates and a titanate substrate using a thin-film process [23]. The GaN HEMT bare die was attached onto a CPC (Cu/Mo70Cu/Cu) carrier with high thermal conductivity using an AuSn (80/20) eutectic process. The complete circuit occupied 9.9 mm × 6.8 mm on the carrier. The GaN HEMT bare die, single-layer capacitors, input/output matching circuits, and microstrip feed lines on RO4003C (Rogers Corporation, Chandler, AZ, USA) for microwave testing were interconnected by 1 mil Au wedge bonding wires. Figure 8. Fabricated internally matched power amplifier using a GaN HEMT bare die, input/output thin-film matching substrates, and single-layer capacitors (circuit area = 9.9 mm × 6.8 mm).

Power Amplifier Measurement
The fabricated power amplifier was measured on a heat-sinking jig under the bias conditions of VDS = 28 V and IDS = 250 mA. The measured S-parameter data were compared with the simulated data in Figure 9. The measured results showed a linear gain of more than 10.2 dB and a return loss of more than 2.3 dB from 2.5 to 6 GHz. The low-frequency gain decreased slightly, and the roll-off of the high- Figure 8. Fabricated internally matched power amplifier using a GaN HEMT bare die, input/output thin-film matching substrates, and single-layer capacitors (circuit area = 9.9 mm × 6.8 mm).

Power Amplifier Measurement
The fabricated power amplifier was measured on a heat-sinking jig under the bias conditions of V DS = 28 V and I DS = 250 mA. The measured S-parameter data were compared with the simulated data in Figure 9. The measured results showed a linear gain of more than 10.2 dB and a return loss of more than 2.3 dB from 2.5 to 6 GHz. The low-frequency gain decreased slightly, and the roll-off of the high-frequency gain moved to about 6.5 GHz due to the minute change of the implemented load impedance after the device assembly.
Micromachines 2020, 11, 375 7 of 10 frequency gain moved to about 6.5 GHz due to the minute change of the implemented load impedance after the device assembly.  Figure 10 shows the designed load impedance trace and implemented load impedance trace estimated after the device assembly on Smith charts, together with the power gain contours and the output power contours at 2.5 GHz and 6 GHz. As shown in Figure 10, the small shift of the implemented load impedance from the designed load impedance slightly increased the highfrequency gain.  Figure 11 shows the output power, power gain, and power-added efficiency (PAE) of the fabricated power amplifier across the input power at 5 GHz where the maximum PAE was measured. The power gain was decreased from 11.1 to 7.6 dB with the varying input power, which corresponded to 3.5 dB power compression. The saturated output power was 43.9 dBm, and the power-added efficiency was 49.7% at the power saturation condition.  Figure 10 shows the designed load impedance trace and implemented load impedance trace estimated after the device assembly on Smith charts, together with the power gain contours and the output power contours at 2.5 GHz and 6 GHz. As shown in Figure 10, the small shift of the implemented load impedance from the designed load impedance slightly increased the high-frequency gain.
Micromachines 2020, 11, 375 7 of 10 frequency gain moved to about 6.5 GHz due to the minute change of the implemented load impedance after the device assembly.  Figure 10 shows the designed load impedance trace and implemented load impedance trace estimated after the device assembly on Smith charts, together with the power gain contours and the output power contours at 2.5 GHz and 6 GHz. As shown in Figure 10, the small shift of the implemented load impedance from the designed load impedance slightly increased the highfrequency gain.  Figure 11 shows the output power, power gain, and power-added efficiency (PAE) of the fabricated power amplifier across the input power at 5 GHz where the maximum PAE was measured. The power gain was decreased from 11.1 to 7.6 dB with the varying input power, which corresponded to 3.5 dB power compression. The saturated output power was 43.9 dBm, and the power-added efficiency was 49.7% at the power saturation condition.  Figure 11 shows the output power, power gain, and power-added efficiency (PAE) of the fabricated power amplifier across the input power at 5 GHz where the maximum PAE was measured. The power gain was decreased from 11.1 to 7.6 dB with the varying input power, which corresponded to 3.5 dB power compression. The saturated output power was 43.9 dBm, and the power-added efficiency was 49.7% at the power saturation condition.  Figure 12 shows the measured continuous-wave output power performance of the power amplifier under the bias conditions of Vds = 28 V and Ids = 250 mA. The measurement was done from 2.5 to 6 GHz with a 0.5 GHz step frequency. The measured results showed that the amplifier had an output power of 43.3-43.9 dBm, a power-added efficiency (PAE) of 33.4%-49.7%, and a power gain of 6.2-8.3 dB. The maximum deviation of the output power was 0.7 dB at 4.5 GHz, and the poweradded efficiency (PAE) was slightly degraded due to some mismatch of the designed load impedance and the implemented load impedance after the device assembly. Our simulations estimated an insertion loss of 0.3-0.52 dB for the output matching circuit itself across 2-6 GHz [24]. The power gain decreased at both ends of the designed bandwidth with the maximum 1.5 dB, which was caused by slightly earlier compression with the increase in the input power, as predicted from the trace comparison of the designed load impedance and the implemented load impedance on the output power contours in Figure 10.    Figure 12 shows the measured continuous-wave output power performance of the power amplifier under the bias conditions of V ds = 28 V and I ds = 250 mA. The measurement was done from 2.5 to 6 GHz with a 0.5 GHz step frequency. The measured results showed that the amplifier had an output power of 43.3-43.9 dBm, a power-added efficiency (PAE) of 33.4-49.7%, and a power gain of 6.2-8.3 dB. The maximum deviation of the output power was 0.7 dB at 4.5 GHz, and the power-added efficiency (PAE) was slightly degraded due to some mismatch of the designed load impedance and the implemented load impedance after the device assembly. Our simulations estimated an insertion loss of 0.3-0.52 dB for the output matching circuit itself across 2-6 GHz [24]. The power gain decreased at both ends of the designed bandwidth with the maximum 1.5 dB, which was caused by slightly earlier compression with the increase in the input power, as predicted from the trace comparison of the designed load impedance and the implemented load impedance on the output power contours in Figure 10.  Figure 12 shows the measured continuous-wave output power performance of the power amplifier under the bias conditions of Vds = 28 V and Ids = 250 mA. The measurement was done from 2.5 to 6 GHz with a 0.5 GHz step frequency. The measured results showed that the amplifier had an output power of 43.3-43.9 dBm, a power-added efficiency (PAE) of 33.4%-49.7%, and a power gain of 6.2-8.3 dB. The maximum deviation of the output power was 0.7 dB at 4.5 GHz, and the poweradded efficiency (PAE) was slightly degraded due to some mismatch of the designed load impedance and the implemented load impedance after the device assembly. Our simulations estimated an insertion loss of 0.3-0.52 dB for the output matching circuit itself across 2-6 GHz [24]. The power gain decreased at both ends of the designed bandwidth with the maximum 1.5 dB, which was caused by slightly earlier compression with the increase in the input power, as predicted from the trace comparison of the designed load impedance and the implemented load impedance on the output power contours in Figure 10.  Table 2 compares our measured power performance with other published results, showing that our work is very competitive in terms of the bandwidth, output power, and power-added efficiency, despite the compact size.  Table 2 compares our measured power performance with other published results, showing that our work is very competitive in terms of the bandwidth, output power, and power-added efficiency, despite the compact size.

Conclusions
We presented the compact 20-W GaN internally matched power amplifier operating from 2.5 to 6 GHz that utilizes a GaN HEMT bare die, single-layer capacitors, and thin-film substrates for input and output matching circuits. The fabricated power amplifier achieved stable operation and flat gain performance by using shunt and series resistors. Under the continuous-wave output power condition, it showed the output power of 43.3-43.9 dBm (21.4-24.5 W), the PAE of 33.4-49.7% and the power gain of 6.2-8.3 dB in the frequency range of 2.5-6 GHz. The developed power amplifier will be effectively used in wireless and military applications that require high output power over a wide frequency range.