Melt Blown Fiber-Assisted Solvent-Free Device Fabrication at Low-Temperature

In this paper, we propose a solvent-free device fabrication method using a melt-blown (MB) fiber to minimize potential chemical and thermal damages to transition-metal-dichalcogenides (TMDCs)-based semiconductor channel. The fabrication process is composed of three steps; (1) MB fibers alignment as a shadow mask, (2) metal deposition, and (3) lifting-up MB fibers. The resulting WSe2-based p-type metal-oxide-semiconductor (PMOS) device shows an ON/OFF current ratio of ~2 × 105 (ON current of ~−40 µA) and a remarkable linear hole mobility of ~205 cm2/V·s at a drain voltage of −0.1 V. These results can be a strong evidence supporting that this MB fiber-assisted device fabrication can effectively suppress materials damage by minimizing chemical and thermal exposures. Followed by an MoS2-based n-type MOS (NMOS) device demonstration, a complementary MOS (CMOS) inverter circuit application was successfully implemented, consisted of an MoS2 NMOS and a WSe2 PMOS as a load and a driver transistor, respectively. This MB fiber-based device fabrication can be a promising method for future electronics based on chemically reactive or thermally vulnerable materials.


Introduction
Microfabrication techniques have been persistently developed as industrial standards increase for high-performance next-generation electronic device applications. Photolithography has been a commonly used method for the spatially precise patterning process in the integrated circuit (IC) technology. Although this conventional photolithography can provide high-resolution patterns, process complexity and high-cost equipment should be involved. Furthermore, several steps incorporated with solvent and thermal exposure, such as photoresist (PR) coating, curing, and developing, can cause detrimental effects to fully exploit intrinsic properties of semiconductors. In order to overcome the limitations, soft lithography has been considered, as promising alternatives have many advantages, such as low-cost, low-temperature processable, and chemical-free methods [1,2]. Although the PR-based patterning steps are not involved during the soft-lithography process, which can avoid chemical and thermal exposure, poor electrical contacts between metal-semiconductor junctions are still remaining as a challenge. Beyond the electronic device fabrications, chemical and thermal exposure-free approaches are desired in the field of display. To handle chemically sensitive organic materials for organic-light-emitting diode fabrication, a chemical-free fabrication process is highly demanded to minimize potential chemical reaction of organic materials. In an effort to find solutions to overcome such limitations, several approaches have been introduced, including inkjet printing [3], fine-metal-shadow masking [4,5], and microcontact-printing [6].
In a decade, two-dimensional (2D) van der Waals semiconductors such as transition-metaldichalcogenides (TMDCs) have been intensively studied to fully exploit their superlative electronic properties [7][8][9][10]. For example, MoS 2 and WSe 2 as semiconducting members of TMDCs have been extensively studied with great possibilities for future electronics within high-speed [11], flexible [12], and immune short channel effects in the device, which scale down [13]. Similar to the other semiconductors, however, the photolithography process also causes electrical property degradations of such semiconductors, due to solvent-induced chemical reactions and/or thermal degradation [14,15]. Furthermore, securing a clean interface between the source/drain (S/D) electrodes and a TMDCs channel layer is another significant issue towards high-performance device demonstrations [16][17][18][19].
Here, we report a melt blown (MB) fiber-assisted solvent-free lithography method for fabrication of field-effect transistors (FETs). The resulting electrical behaviors of TMDCs-based FETs are thoroughly compared with those of devices fabricated using a conventional photolithography process.

Materials and Methods
TMDCs-based FETs were fabricated on a thermally oxidized 285 nm-thick SiO 2 /p + silicon substrate. Silicon substrate was ultrasonically cleaned by sequentially immersing in acetone, methyl alcohol, and isopropyl alcohol each for 15 min. Polydimethylsiloxane (PDMS) stamps were used to exfoliate and transfer 2D semiconductor active channels to a designated place. To fabricate PDMS stamps, base resin and cross-linker (Sylgard 184, Dow Corning) solutions were mixed with a 10:1 volume ratio, and trapped-air bubbles were removed by degassing in a vacuum for 20 min. The solution was then poured onto a cleaned silicon wafer mold and thermally cured on a hot plate in ambient condition at 423 K for 1 h. Figure 1 shows a non-lithographic micro-scaled device fabrication process using an MB fiber-based shadow mask. First of all, 2D TMDC semiconductors were mechanically exfoliated and transferred on a silicon substrate by a PDMS-based direct imprinting method, as shown in Figure 1a. In Figure 1b, an MB fiber-based shadow mask was aligned and subsequently transferred onto a targeted TMDC nanoflake under an optical microscope (OM) to define micropatterned S/D electrodes. The MB fiber-based shadow mask consisted of a punched PDMS frame and a selected MB fiber with an average diameter of~1.5 µm. The suspending MB fiber was attached on the bottom side of the punched PDMS stamp (see Figure S1 with further details of MB fiber-based shadow mask technique in the Supplementary Materials (SM) section). The MB fiber could be efficiently attached at the 2D TMDC semiconductors on a silicon substrate due to its strong electrostatic force. Figure 1c,d shows a metal S/D electrodes patterning using a DC magnetron sputtering system, and we named this process as the "lift-up" method. By lifting-up the MB fiber-based shadow mask, a narrow gap between S/D electrodes (channel length) was formed with a distance corresponding to the diameter of a used MB fiber. This method is a straightforward way to form micro-scaled S/D electrodes without PR-casting and thermal curing process, and it can effectively reduce the whole process steps and the cost compared to the conventional photolithography. Based on this approach, WSe 2 and the MoS 2 -based PMOS and NMOS devices were fabricated with Pt (50 nm) and Ti/Au (25 nm/25 nm) as S/D electrodes, respectively. between S/D electrodes (channel length) was formed with a distance corresponding to the diameter of a used MB fiber. This method is a straightforward way to form micro-scaled S/D electrodes without PR-casting and thermal curing process, and it can effectively reduce the whole process steps and the cost compared to the conventional photolithography. Based on this approach, WSe2 and the MoS2based PMOS and NMOS devices were fabricated with Pt (50 nm) and Ti/Au (25 nm/25 nm) as S/D electrodes, respectively.   , the WSe 2 PMOS shows a strong p-type property, while the n-type characteristic is suppressed (blue line). The thermally annealed WSe 2 PMOS shows excellent I ON,p of~−0.4 mA at V D of −1 V, which is 10 3 times higher I ON,p than the as-fabricated device at the same bias conditions. It implies that the post-annealing process in an ambient condition forms an atomically thin tungsten oxides (WO x ) layer, having a p-type electrical characteristic on the surface of WSe 2 nanoflake, and it can be understood as a p-doping process at the WSe 2 channel surface [20][21][22][23]. Figure 2b shows I D -V G transfer characteristic curves and linear mobility (µ lin ) plot (inset) at V D of −1 mV, −10 mV, and −100 mV. The µ lin was calculated by using the following equation:

Results and Discussion
where, C OX is the capacitance of SiO 2 gate insulator, W and L are the width and the length of the FET channel, respectively. From this equation, the maximum linear mobility (µ lin,max ) of our WSe 2 PMOS was calculated as~205 cm 2 /V·s at V D of −100 mV. Moreover, another WSe 2 PMOS also showed excellent µ lin,max of~244 cm 2 /V·s, as shown in Figure S2 in Supplementary Materials. As shown in Figure 2b, the I D of our WSe 2 PMOS is proportionally increased by the V D variation. This result can be a strong evidence that our non-lithographic fabrication method provides a high-quality Ohmic contact between the WSe 2 and Pt S/D electrodes. As a result, we can successfully achieve the high-performance WSe 2 PMOS device with excellent µ lin,max .  Figure 2 shows drain current-gate voltage (ID-VG) transfer characteristic curves of a WSe2-based PMOS transistor. As shown in Figure 2a, the as-fabricated WSe2 PMOS shows an ambipolar behavior, and both drain ON current (ION) levels in p-type and n-type regions (ION,p and ION,n) were ~0.3 µA at a drain voltage (VD) of −1 V (black line). After a post-annealing process (423 K for 1 h in ambient air), the WSe2 PMOS shows a strong p-type property, while the n-type characteristic is suppressed (blue line). The thermally annealed WSe2 PMOS shows excellent ION,p of ~−0.4 mA at VD of −1 V, which is ~10 3 times higher ION,p than the as-fabricated device at the same bias conditions. It implies that the post-annealing process in an ambient condition forms an atomically thin tungsten oxides (WOx) layer, having a p-type electrical characteristic on the surface of WSe2 nanoflake, and it can be understood as a p-doping process at the WSe2 channel surface [20][21][22][23]. Figure 2b shows ID-VG transfer characteristic curves and linear mobility (µlin) plot (inset) at VD of −1 mV, −10 mV, and −100 mV. The µlin was calculated by using the following equation:

Results and Discussion
where, COX is the capacitance of SiO2 gate insulator, W and L are the width and the length of the FET channel, respectively. From this equation, the maximum linear mobility (µlin,max) of our WSe2 PMOS was calculated as ~205 cm 2 /V·s at VD of −100 mV. Moreover, another WSe2 PMOS also showed excellent µlin,max of ~244 cm 2 /V·s, as shown in Figure S2 in Supplementary Materials. As shown in Figure 2b, the ID of our WSe2 PMOS is proportionally increased by the VD variation. This result can be a strong evidence that our non-lithographic fabrication method provides a high-quality Ohmic contact between the WSe2 and Pt S/D electrodes. As a result, we can successfully achieve the highperformance WSe2 PMOS device with excellent µlin,max. In addition to the WSe2-based PMOS device, an n-type MoS2 nanoflake-based NMOS device was investigated in a similar manner. Figure 3a,b shows schematics of device structures and OM images of an MoS2 NMOS and an annealed WSe2 PMOS on 285 nm-thick SiO2/p + silicon substrate, respectively. Figure 3c,d show ID-VG transfer characteristics of each device. The scattered symbol and In addition to the WSe 2 -based PMOS device, an n-type MoS 2 nanoflake-based NMOS device was investigated in a similar manner. Figure 3a,b shows schematics of device structures and OM images of an MoS 2 NMOS and an annealed WSe 2 PMOS on 285 nm-thick SiO 2 /p + silicon substrate, respectively.  Based on the PMOS and NMOS devices, a CMOS inverter circuit application was implemented, and ID-VD output characteristics curves of PMOS and NMOS FETs are displayed in Figure 4a (see Figure S3 with further details of load-line analysis in the Supplementary Materials section). The MoS2 NMOS and WSe2 PMOS were used as a load and a driver transistor, respectively, because the MoS2 NMOS and WSe2 PMOS showed negative Vth. Moreover, the WSe2 PMOS had better electrical performances, such as higher ID and linear hole mobility, than those of the MoS2 NMOS device. Figure  4b shows the voltage transfer characteristic (VTC) curves of our CMOS inverter circuit device, and the transition voltage is ~−42 V, which is well-matched with Vth of WSe2 PMOS driver transistor. The inset of Figure 4b shows our CMOS inverter circuit diagram by connecting with the MoS2 NMOS and WSe2 PMOS through an Au wire-bonding technique. To the best of our knowledge, this is the first demonstration of a 2D nanomaterial-based CMOS inverter circuit application through fully dried fabrication processes. Based on the PMOS and NMOS devices, a CMOS inverter circuit application was implemented, and I D -V D output characteristics curves of PMOS and NMOS FETs are displayed in Figure 4a (see Figure S3 with further details of load-line analysis in the Supplementary Materials section). The MoS 2 NMOS and WSe 2 PMOS were used as a load and a driver transistor, respectively, because the MoS 2 NMOS and WSe 2 PMOS showed negative V th . Moreover, the WSe 2 PMOS had better electrical performances, such as higher I D and linear hole mobility, than those of the MoS 2 NMOS device. Figure 4b shows the voltage transfer characteristic (VTC) curves of our CMOS inverter circuit device, and the transition voltage is~−42 V, which is well-matched with V th of WSe 2 PMOS driver transistor. The inset of Figure 4b shows our CMOS inverter circuit diagram by connecting with the MoS 2 NMOS and WSe 2 PMOS through an Au wire-bonding technique. To the best of our knowledge, this is the first demonstration of a 2D nanomaterial-based CMOS inverter circuit application through fully dried fabrication processes.
4b shows the voltage transfer characteristic (VTC) curves of our CMOS inverter circuit device, and the transition voltage is ~−42 V, which is well-matched with Vth of WSe2 PMOS driver transistor. The inset of Figure 4b shows our CMOS inverter circuit diagram by connecting with the MoS2 NMOS and WSe2 PMOS through an Au wire-bonding technique. To the best of our knowledge, this is the first demonstration of a 2D nanomaterial-based CMOS inverter circuit application through fully dried fabrication processes.

Conclusions
We demonstrated a solvent-free device fabrication method using an MB fiber-based shadow mask to minimize high-temperature and/or solvent-induced chemical degradation of semiconducting materials. This process effectively reduces the entire process protocols and the cost compared to the conventional photolithography. Moreover, the pattern size is easily tunable based on the diameter of the MB fiber (~1.5 µm). As a result, our WSe 2 PMOS shows excellent electrical performances, such as µ lin,max of 205 cm 2 /V·s, I ON of~−40 µA, and I ON /I OFF ratio of~2 × 10 5 at V D = −0.1 V, because this approach provides a high-quality interface between the semiconductor active channel and the metal S/D electrode. Lastly, we successfully achieved the CMOS inverter circuit demonstrations consisted of a WSe 2 PMOS as a driver and an MoS 2 NMOS as a load transistor. This micro-scaled shadow masking process exhibits a promising key technique to unlock the unlimited potential of materials for future advanced electronics.

Conflicts of Interest:
The authors declare no conflict of interest.