Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.


Introduction
Monolithic 3-dimensional integration (M3DI) refers to a 3D integration scheme of sequentially manufacturing and stacking devices [1][2][3]. M3DI has been studied extensively as an alternative to improve semiconductor performance in a region where the scale-down limit of a semiconductor device is approaching. In memories (e.g., NAND flash and dynamic random-access memory) and sensors (e.g., 3D heterogeneous integration), the sequential stacking M3DI method has already been applied instead of the through-silicon via method [4][5][6][7]. In addition, studies have reported that the performance of electrical coupling improves when the inter-layer dielectric (ILD) thickness of the M3D complementary metal-oxide-semiconductor logic is less than 50 nm [8]. M3DI in terms of logic has the potential to enhance chip performance, interconnect delay, device density, and frequency bandwidth without requiring the further lateral scaling of the device [9]. Owing to the process for device stacking sequentially on a single wafer, the previous and next tiers have significant limitations in the process thermal budget for device quality [10]. Compared to the conventional standard process, low-temperature processes using approximately 650 • C have been developed, improving the performance of M3DI [11][12][13]. Currently, most M3DI devices have been researched based on metal-oxide-semiconductor field-effect transistors (MOSFETs) that use Si, Ge, and III-V materials [14][15][16][17]. For the majority of MOSFETs, a thermal budget is required for dopant activation after the implantation process; however, there are physical limitations for using these as low-power devices. For junctionless field-effect transistors (JLFETs), it is possible to use the MOSFET process as it 2 of 10 has a junctionless structure. This means that dopant activation is not required, unlike in MOSFETs. JLFETs are advantageous for scale-down, surface mobility degradation, and short-channel effects [18].
A new circuit simulation model has been proposed in which the M3DIC composed of MOSFETs (M3DIC-MOSFETs) reflect direct current (DC)/alternating current (AC) and transient inter-layer electrical coupling [19]. However, owing to the absence of a JLFET compact model that considers electrical coupling between the tiers for the circuit simulation of M3DI structures, an accurate circuit simulation for M3DICs is not possible [20][21][22][23].
In this study, to extract the parameters of the model for the circuit simulation of the M3DIC-JLFET, a structure of monolithic 3D inverter (M3DINV) with electrical coupling (thickness of ILD, T ILD = 10 nm) was constructed and simulated using technology computer-aided design (TCAD). To perform circuit simulation considering the electrical coupling of M3DIC-JLFET, we propose the LETI-UTSOI (version 2.1) model [24][25][26] of the fully-depleted silicon-on-insulator (FD-SOI) MOSFET structure as an alternative to the JLFET compact model and extract the model parameters. The extracted model parameters were verified and compared to the TCAD mixed-mode simulation results (Section 3). Based on the model parameters extracted in Section 3, various logics were simulated, and the performance was compared with that of M3DIC-MOSFETs (Section 4) [27]. Section 5 concludes this study. Figure 1 shows the schematics of an M3DINV composed of JLFET (M3DINV-JLFET). As shown in Figure 1a, an M3DINV-JLFET consists of n-type and p-type JLFET transistors in the top and bottom tiers, respectively. The doping of the JLFET's source/drain, lightly-doped drain (LDD), and the channel are 10 20 , 10 20 , and 10 19 cm −3 , respectively. The JLFET was simulated at the gate length (L g ), gate oxide film (T ox ), silicon thickness (T si ), and ILD thickness (T ILD ) at 30, 1, 6 m, and 10 nm, respectively. The gate oxide, ILD, and box were composed of SiO 2 .

Structures
Micromachines 2020, 11, x FOR PEER REVIEW 2 of 10 For junctionless field-effect transistors (JLFETs), it is possible to use the MOSFET process as it has a junctionless structure. This means that dopant activation is not required, unlike in MOSFETs. JLFETs are advantageous for scale-down, surface mobility degradation, and short-channel effects [18]. A new circuit simulation model has been proposed in which the M3DIC composed of MOSFETs (M3DIC-MOSFETs) reflect direct current (DC)/alternating current (AC) and transient inter-layer electrical coupling [19]. However, owing to the absence of a JLFET compact model that considers electrical coupling between the tiers for the circuit simulation of M3DI structures, an accurate circuit simulation for M3DICs is not possible [20][21][22][23].
In this study, to extract the parameters of the model for the circuit simulation of the M3DIC-JLFET, a structure of monolithic 3D inverter (M3DINV) with electrical coupling (thickness of ILD, TILD = 10 nm) was constructed and simulated using technology computer-aided design (TCAD). To perform circuit simulation considering the electrical coupling of M3DIC-JLFET, we propose the LETI-UTSOI (version 2.1) model [24][25][26] of the fully-depleted silicon-on-insulator (FD-SOI) MOSFET structure as an alternative to the JLFET compact model and extract the model parameters. The extracted model parameters were verified and compared to the TCAD mixed-mode simulation results (Section 3). Based on the model parameters extracted in Section 3, various logics were simulated, and the performance was compared with that of M3DIC-MOSFETs (Section 4) [27]. Section 5 concludes this study. Figure 1 shows the schematics of an M3DINV composed of JLFET (M3DINV-JLFET). As shown in Figure 1a, an M3DINV-JLFET consists of n-type and p-type JLFET transistors in the top and bottom tiers, respectively. The doping of the JLFET's source/drain, lightly-doped drain (LDD), and the channel are 10 20 , 10 20 , and 10 19 cm −3 , respectively. The JLFET was simulated at the gate length (Lg), gate oxide film (Tox), silicon thickness (Tsi), and ILD thickness (TILD) at 30, 1, 6m, and 10 nm, respectively. The gate oxide, ILD, and box were composed of SiO2. In reference data simulation, a device simulator, ATLAS [28], by SILVACO was used. Table 1 shows the models, methods, and work functions used in the TCAD simulation. The models used for the device simulation were CVT, SRH, BGN, AUGER, and FERMI. The methods used for device simulation were NEWTON and GUMMEL. The gate work functions of the n-type and p-type JLFETs were 5.06 and 4.41 eV, respectively. In reference data simulation, a device simulator, ATLAS [28], by SILVACO was used. Table 1 shows the models, methods, and work functions used in the TCAD simulation. The models used for the device simulation were CVT, SRH, BGN, AUGER, and FERMI. The methods used for device simulation were NEWTON and GUMMEL. The gate work functions of the n-type and p-type JLFETs were 5.06 and 4.41 eV, respectively.  Figure 2 shows the Simulation Program with Integrated Circuit Emphasis (SPICE) model parameter extraction process used in this study. Through the process flow, model parameters were extracted by comparing them with the reference data. First, parameter initialization was performed, and the threshold voltage (V t ) roll-off and subthreshold swing (SS) degradation parameters were extracted. Next, the mobility and series resistance parameters, velocity saturation, drain-induced barrier lowering (DIBL), and channel length modulation (CLM) parameters were extracted. The process was repeated until the parameters were completely extracted. When the DC parameter extraction was complete, the output conductance parameters were extracted. Finally, the back gate effect parameters were extracted.

Parameter Extraction
Micromachines 2020, 11, x FOR PEER REVIEW 3 of 10  Figure 2 shows the Simulation Program with Integrated Circuit Emphasis (SPICE) model parameter extraction process used in this study. Through the process flow, model parameters were extracted by comparing them with the reference data. First, parameter initialization was performed, and the threshold voltage (Vt) roll-off and subthreshold swing (SS) degradation parameters were extracted. Next, the mobility and series resistance parameters, velocity saturation, drain-induced barrier lowering (DIBL), and channel length modulation (CLM) parameters were extracted. The process was repeated until the parameters were completely extracted. When the DC parameter extraction was complete, the output conductance parameters were extracted. Finally, the back gate effect parameters were extracted.     Figure 3a shows the drain current-gate voltage (I pds −V pgs ) characteristics at V pds (−0.2, −0.6, and −1 V) and V sub = 0 V. Figure 3b shows the I pds −V pds characteristics at V pgs (−0.2, −0.6, and −1 V) and V sub = 0 V. The HSPICE results match the TCAD results within 10% error. Figure 4 shows the current-voltage characteristics with the TCAD and HSPICE simulation results of the top n-type JLFET. Figure 4a shows the drain current-gate voltage (I nds −V ngs ) characteristics at V nds (0.2, 0.6, and 1 V) and V pgs = 0 V. Figure 4b shows the I nds −V nds characteristics at V ngs (0.2, 0.6, and 1 V) and V pgs = 0 V. The HSPICE results match the TCAD results within 10% error. Figure 5a shows the I nds −V ngs characteristics at V pgs (0, 0.5, and 1 V) and V nds = 1 V. Figure 5b shows the I nds −V nds characteristics at V ngs (0.2, 0.6, and 1 V) and V pgs = V ngs . The HSPICE results match the 4 of 10 TCAD results within 10% error. This shows that the top n-type JLFET reflects the dependence on the back-gate (gate of the p-type JLFET) bias well. When a voltage is applied to the gate of the bottom p-type JLFET which can operate as a back-gate in M3DINV with a very thin ILD of T ILD = 10 nm, it affects the current of the top n-type JLFET by the threshold voltage shifts.    Figure 5b shows the Inds−Vnds characteristics at Vngs (0.2, 0.6, and 1 V) and Vpgs = Vngs. The HSPICE results match the TCAD results within 10% error. This shows that the top n-type JLFET reflects the dependence on the back-gate (gate of the p-type JLFET) bias well. When a voltage is applied to the gate of the bottom ptype JLFET which can operate as a back-gate in M3DINV with a very thin ILD of TILD = 10 nm, it affects the current of the top n-type JLFET by the threshold voltage shifts.         Figure 5b shows the Inds−Vnds characteristics at Vngs (0.2, 0.6, and 1 V) and Vpgs = Vngs. The HSPICE results match the TCAD results within 10% error. This shows that the top n-type JLFET reflects the dependence on the back-gate (gate of the p-type JLFET) bias well. When a voltage is applied to the gate of the bottom ptype JLFET which can operate as a back-gate in M3DINV with a very thin ILD of TILD = 10 nm, it affects the current of the top n-type JLFET by the threshold voltage shifts.  Figure 6 shows the transconductance-voltage characteristics of the p-type and n-type JLFET. Figure 6a shows the transconductance-gate voltage (g m −V pgs ) characteristics of the bottom p-type JLFET at V pds (−0.2, −0.6, and −1 V). Figure 6b shows the transconductance-gate voltage (g m −V ngs ) characteristics of the top n-type JLFET at V pds (=0.2, 0.6, and 1 V). We observed a minor mismatch at high gate source voltage values. However, the HSPICE simulation results matched the TCAD results overall within 10% error.  Figure 6 shows the transconductance-voltage characteristics of the p-type and n-type JLFET. Figure 6a shows the transconductance-gate voltage (gm−Vpgs) characteristics of the bottom p-type JLFET at Vpds (−0.2, −0.6, and −1 V). Figure 6b shows the transconductance-gate voltage (gm−Vngs) characteristics of the top n-type JLFET at Vpds (=0.2, 0.6, and 1 V). We observed a minor mismatch at high gate source voltage values. However, the HSPICE simulation results matched the TCAD results overall within 10% error.  Following the model parameter extraction process flow, we extracted the parameters of the bottom p-type and top n-type JLFET using the LETI-UTSOI model, as shown in Table 2. Table 2. Summary of the extracted parameters of the LETI-UTSOI model for the bottom p-type and top n-type JLFET.   Figure 7a shows the gate capacitance-gate voltage (C pgpg −V pgs ) characteristics of the bottom p-type JLFET at V pds (−0.2, −0.6, and −1 V). Figure 6b shows the gate capacitance-gate voltage (C ngng −V ngs ) characteristics of the top n-type JLFET at V pds (0.2, 0.6, and 1 V). The HSPICE simulation results match the TCAD results.  Figure 6 shows the transconductance-voltage characteristics of the p-type and n-type JLFET. Figure 6a shows the transconductance-gate voltage (gm−Vpgs) characteristics of the bottom p-type JLFET at Vpds (−0.2, −0.6, and −1 V). Figure 6b shows the transconductance-gate voltage (gm−Vngs) characteristics of the top n-type JLFET at Vpds (=0.2, 0.6, and 1 V). We observed a minor mismatch at high gate source voltage values. However, the HSPICE simulation results matched the TCAD results overall within 10% error.  Following the model parameter extraction process flow, we extracted the parameters of the bottom p-type and top n-type JLFET using the LETI-UTSOI model, as shown in Table 2. Table 2. Summary of the extracted parameters of the LETI-UTSOI model for the bottom p-type and top n-type JLFET. Following the model parameter extraction process flow, we extracted the parameters of the bottom p-type and top n-type JLFET using the LETI-UTSOI model, as shown in Table 2. Figure 8a shows an equivalent circuit of the M3DINV composed of the top n-type and bottom p-type JLFETs in series. The LETI-UTSOI model was applied to both the JLFETs. The input voltage (V IN = V pg = V ng ) of M3DINV was applied to the gates of the n-type and p-type JLFETs. The driving voltage (V DD ) was applied to the source of the p-type JLFET, and the source of the n-type JLFET was connected to the ground. The output voltage (V OUT = V pd = V nd ) was the drain voltage of the n-type and p-type JLFET. Figure 8b compares the voltage transfer characteristics (VTC) on the M3DINV-JLFET, as shown in Figure 8a. The HSPICE simulation results match the TCAD results overall within 10% error.   Figure 9 shows the transient response of the M3DINV-JLFET. Black squares (and solid lines) and red circles (and dot lines) denote the input voltages V IN and the output voltages V OUT of the M3DINV, respectively. Load capacitance CL = 1 fF was used. The HSPICE simulation results match the TCAD results overall within 10% error.

Parameter Extraction
Micromachines 2020, 11, x FOR PEER REVIEW 7 of 10 Figure 9 shows the transient response of the M3DINV-JLFET. Black squares (and solid lines) and red circles (and dot lines) denote the input voltages VIN and the output voltages VOUT of the M3DINV, respectively. Load capacitance CL = 1 fF was used. The HSPICE simulation results match the TCAD results overall within 10% error.  Table 3 shows the power consumption and performance of a fan-out-3 (FO3) ring oscillator built using M3DINV-JLFETs. The M3DINV-JLFETs were compared with the M3DINV-MOSFETs. The power consumption, frequency, and delay per stage of the ring oscillators with 3, 19, and 101 stages of the M3DINV-JLFETs varied less than 3% from those of the M3DINV-MOSFETs. However, the performances of the M3DINV-MOSFET and M3DINV-JLFET were approximately the same.  Table 4 summarizes the performance comparison of M3DIC-JLFETs and M3DIC-MOSFETs. M3DICs such as the INV, NAND, NOR, 2 × 1 multiplexer (MUX) [29], D flip-flop (D-FF) [30], and 6T SRAM [31] were simulated. Their performances were compared in terms of their average static power, average dynamic power, and average delay. The static power of M3DINV-JLFETs increased approximately 600% more than the power of the M3DIC-MOSFETs. Electrical coupling by the gate of the bottom transistor increases the leakage current of the top transistor, resulting in an increase in static power. M3DIC-JLFETs have more leakage current changes due to electrical coupling than M3DIC-MOSFETs. The dynamic power of M3DINV-JLFETs increased approximately 34.5% more than the power of M3DIC-MOSFETs. The average propagation delay of the M3DINV-JLFETs increased approximately 17.5% compared to that of M3DIC-MOSFETs. Because the load cap of M3DIC-JLFETs is larger than that of the M3DIC-MOSFETs due to the electric coupling, the dynamic power and delay of the M3DIC-JLFETs are larger than those of the M3DIC-MOSFETs.  Table 3 shows the power consumption and performance of a fan-out-3 (FO3) ring oscillator built using M3DINV-JLFETs. The M3DINV-JLFETs were compared with the M3DINV-MOSFETs. The power consumption, frequency, and delay per stage of the ring oscillators with 3, 19, and 101 stages of the M3DINV-JLFETs varied less than 3% from those of the M3DINV-MOSFETs. However, the performances of the M3DINV-MOSFET and M3DINV-JLFET were approximately the same.  Table 4 summarizes the performance comparison of M3DIC-JLFETs and M3DIC-MOSFETs. M3DICs such as the INV, NAND, NOR, 2 × 1 multiplexer (MUX) [29], D flip-flop (D-FF) [30], and 6T SRAM [31] were simulated. Their performances were compared in terms of their average static power, average dynamic power, and average delay. The static power of M3DINV-JLFETs increased approximately 600% more than the power of the M3DIC-MOSFETs. Electrical coupling by the gate of the bottom transistor increases the leakage current of the top transistor, resulting in an increase in static power. M3DIC-JLFETs have more leakage current changes due to electrical coupling than M3DIC-MOSFETs. The dynamic power of M3DINV-JLFETs increased approximately 34.5% more than the power of M3DIC-MOSFETs. The average propagation delay of the M3DINV-JLFETs increased approximately 17.5% compared to that of M3DIC-MOSFETs. Because the load cap of M3DIC-JLFETs is larger than that of the M3DIC-MOSFETs due to the electric coupling, the dynamic power and delay of the M3DIC-JLFETs are larger than those of the M3DIC-MOSFETs.

Conclusions
In this study, we propose to use the LETI-UTSOI (version 2.1) model as an alternative to the JLFET compact model to perform circuit simulation considering the electrical coupling of M3DIC-JLFET. Comparing the simulation results of TCAD and HSPICE, the parameters of the proposed model were extracted and the DC, AC, and transient response characteristics were verified. Although the LETI-UTSOI model of the FD-SOI MOSFET structure is used as an alternative to the JLFET compact model, it was confirmed that circuit simulation considering electrical coupling between vertically stacked JLFETs is possible. Because of the various circuit simulations, the overall performance of the M3DIC-MOSFETs was slightly higher than that of the M3DIC-JLFETs. However, considering the ease of processing, miniaturization, and advantages of M3DI, the applicability of M3DIC-JLFET is higher.