Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET)

Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (IAMB). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (ION), IAMB, and gate-to-drain capacitance (CGD). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot.


Introduction
Over the past several decades, complementary metal-oxide-semi-conductor (CMOS) technologies have been scaled down to improve integration densities and performance [1][2][3]. As the integration density increases, however, the increase of power consumption becomes an emerging main concern. Since the power dissipation is proportional to the square of supply voltage (V DD ), future CMOS devices should be operating with low V DD . However, MOS field-effect transistors (MOSFETs) have a limit of 60 mV/dec subthreshold swing (S) at room temperature because they are based on a thermionic carrier injection. As a result, it is fundamentally impossible to lower V DD maintaining a high on-off current ratio (I ON /I OFF ) [4]. Therefore, a sharp-switching device, based on a novel operating mechanism, is needed to achieve sub-60 mV/dec-S, and hence ultra-low power operation. Recently, tunnel FETs (TFETs) have been extensively investigated as one of the promising candidates for a next-generation low-power logic element [5][6][7][8][9][10][11]. Because TFETs inject charges through a band-to-band tunneling (BTBT) mechanism from a source to a channel, abrupt switching is possible compared to conventional MOSFETs with drastically reduced I OFF [12][13][14]. In addition, they are able to inherit MOSFETs technologies with minimum cost and maximum efficiency with the help of similar structure and process to MOSFETs used in current CMOS technologies [15].
However, TFETs have some technical challenges to be solved for succeeding or alternating MOSFETs. First, they suffer from a low-level I ON and a worse S than expectation due to a high tunnel resistance [16]. A multi-gate structure and a narrow bandgap material (e.g., SiGe or Ge) are regarded as promising strategies to address the above-mentioned issues by improving gate controllability and BTBT efficiency [16][17][18]. In addition, heterojunction is preferred to suppress the I OFF caused by Shockley-Read-Hole (SRH) recombination, which is exponentially increased in narrow band-gap Figure 1 shows a structure of double-gate isosceles trapezoid TFET (DGIT-TFET) studied in this work. It adopts a double-gate (DG) structure to enhance gate controllability over the channel. It features a vertical channel structure, in which the source and drain are located at a narrow top, and relatively thick bottom regions, respectively. The vertical structure is advantageous, not only for increasing the integration density without any areal penalty, but also for adopting a selective epitaxial layer growth (SEG) technique to improve I ON /I OFF with the help of heterojunction [26]. In this study, the Si 1-x Ge x -channel is overlapped with the gate by 15 nm considering the process margin in SEG process ( Figure 1). It is also helpful to improve the I ON further by using pseudo-direct BTBT when the Ge mole fraction is increased [16,18,27]. The channel length (L CH ) is set by 30 nm to exclude short-channel effects and equivalent gate oxide thickness (T OX ) is set by 0.5 nm assuming high-k dielectric. The other important design parameters are summarized in Table 1, unless otherwise noted [28]. The electrical characteristics of DGIT-TFET, depending on the design parameters are investigated, and analyzed using Synopsys Sentaurus TM (Synopsys, Mountain View, CA, USA) [25]. For a rigorous examination, Shockley-Read-Hall (SRH) and dynamic non-local BTBT models are used after calibration. In detail, A and B parameters in Kane's model is changed as in [18], to consider both indirect and direct BTBT components, simultaneously. The modified local density approximation (MLDA) model is also used for the consideration of quantum effect.  Table 1. The n-channel DGIT-TFET can be fabricated by the process flow, shown in Figure 2. Starting with a silicon-on-insulator (SOI) wafer (a) drain region is formed by arsenic (As) ion implantation (b). A bulk-Si substrate can alternate the SOI with the help of vertical structure of DGIT-TFET. The sequential in-situ, doped epitaxial growths are performed for channel (i.e., lightly doped p -Si and Ge layers) and source (i.e., highly doped p + Ge layer) (c). After patterning tapered structure, conventional shallow trench isolation (STI) process is performed by oxide gap-fill, chemical mechanical polishing (CMP), and STI wet-etching processes in sequence (d). The length of DU can simply be adjusted by changing STI-oxide wet-etching time. After dopant activation, atomic layer deposition (ALD) for high-k gate oxide is followed by metal gate deposition (e). Finally, double-gates are formed by sidewall spacer technique, with an appropriate over-etching, to avoid gate-to-source overlap (f). The back-end-of-line (BEOL) processes are not shown here, since the conventional techniques are applicable.  Table 1. The n-channel DGIT-TFET can be fabricated by the process flow, shown in Figure 2. Starting with a silicon-on-insulator (SOI) wafer (a) drain region is formed by arsenic (As) ion implantation (b). A bulk-Si substrate can alternate the SOI with the help of vertical structure of DGIT-TFET. The sequential in-situ, doped epitaxial growths are performed for channel (i.e., lightly doped p − Si and Ge layers) and source (i.e., highly doped p + Ge layer) (c). After patterning tapered structure, conventional shallow trench isolation (STI) process is performed by oxide gap-fill, chemical mechanical polishing (CMP), and STI wet-etching processes in sequence (d). The length of DU can simply be adjusted by changing STI-oxide wet-etching time. After dopant activation, atomic layer deposition (ALD) for high-k gate oxide is followed by metal gate deposition (e). Finally, double-gates are formed by side-wall spacer technique, with an appropriate over-etching, to avoid gate-to-source overlap (f). The back-end-of-line (BEOL) processes are not shown here, since the conventional techniques are applicable. In order to estimate the effect of asymmetric body thickness (TB) in DGIT-TFET (i.e., thin source and thick drain) on its electrical characteristics, drain current (ID) as a function of VGS with different TB are examined in the conventional DG-TFET structure ( Figure 3a). The simulation results show that the ION and S are improved as TB becomes thinner ( Figure 3b). It is attributed to the improved gate controllability over the channel, which is confirmed by the increase in electric field at source-tochannel junction as TB decreases ( Figure 3c). Unfortunately, there is a drawback that the IAMB is also increased with the thinner TB since tunnel barrier width (WTUN) at channel-to-drain junction is decreased as well ( Figure 3d). On the other hand, it is expected that the DGIT-TFET's asymmetric source/drain thicknesses will allow it to achieve high ION and low IOFF, simultaneously.   In order to estimate the effect of asymmetric body thickness (T B ) in DGIT-TFET (i.e., thin source and thick drain) on its electrical characteristics, drain current (I D ) as a function of V GS with different T B are examined in the conventional DG-TFET structure (Figure 3a). The simulation results show that the I ON and S are improved as T B becomes thinner (Figure 3b). It is attributed to the improved gate controllability over the channel, which is confirmed by the increase in electric field at source-to-channel junction as T B decreases ( Figure 3c). Unfortunately, there is a drawback that the I AMB is also increased with the thinner T B since tunnel barrier width (W TUN ) at channel-to-drain junction is decreased as well (Figure 3d). On the other hand, it is expected that the DGIT-TFET's asymmetric source/drain thicknesses will allow it to achieve high I ON and low I OFF , simultaneously.  Figure 4a shows the transfer characteristics of DGIT-TFET by changing the drain thickness (TD) from 5 to 50 nm, while the source thickness (TS) is fixed at 5 nm considering process capability and compatibility with sub-7 nm technology node [29]. In case of 5 nm-thick TD, DGIT-TFET is identical to the conventional DG-TFET in Figure 3a,b which shows improved ION but suffers from IAMB. On the other hand, it is clear that DGIT-TFET can suppress IAMB, without any ION and S degradation, by increasing TD (Figure 4a). The simulation result shows that IAMB is reduced approximated 2 orders of  Figure 4a shows the transfer characteristics of DGIT-TFET by changing the drain thickness (T D ) from 5 to 50 nm, while the source thickness (T S ) is fixed at 5 nm considering process capability and compatibility with sub-7 nm technology node [29]. In case of 5 nm-thick T D , DGIT-TFET is identical to the conventional DG-TFET in Figure 3a,b which shows improved I ON but suffers from I AMB .

Design Optimization of DGIT-TFET
On the other hand, it is clear that DGIT-TFET can suppress I AMB , without any I ON and S degradation, by increasing T D (Figure 4a). The simulation result shows that I AMB is reduced approximated 2 orders of magnitude as T D increases from 5 nm to 20 nm, since the electric field at the channel-to-drain junction is decreased efficiently.
(CGD) dominates entire gate capacitance (CGG) while gate-to-source capacitance (CGS) is negligible [30]. Therefore, CGD as a function of VGS, is examined with the various TD from 5 to 50 nm-thick. Figure 4b shows that CGD is increased proportionally to the TD, due to the increase of drain area. It is problematic for high-speed and low-power CMOS logic applications, since the CGD is directly related to the Miller capacitance, which increases voltage over/under-shoots and delay time [31]. In other words, there is a trade-off between IAMB and CGD in terms of TD. As shown in Figure 5, the CGD remarkably increases when TD ≥ 20 nm while the amount of decreasing IAMB is negligible. Therefore, the optimum TD is determined as 20 nm.  In addition to the effects of T D on the DC characteristics, the influences of T D on the AC performances are examined as well. In case of TFET, unlike to the MOSFET, gate-to-drain capacitance (C GD ) dominates entire gate capacitance (C GG ) while gate-to-source capacitance (C GS ) is negligible [30]. Therefore, C GD as a function of V GS , is examined with the various T D from 5 to 50 nm-thick. Figure 4b shows that C GD is increased proportionally to the T D , due to the increase of drain area. It is problematic for high-speed and low-power CMOS logic applications, since the C GD is directly related to the Miller capacitance, which increases voltage over/under-shoots and delay time [31]. In other words, there is a trade-off between I AMB and C GD in terms of T D . As shown in Figure 5, the C GD remarkably increases when T D ≥ 20 nm while the amount of decreasing I AMB is negligible. Therefore, the optimum T D is determined as 20 nm.
In addition to the increase in T D , another strategy is required to suppress I AMB and C GD , simultaneously. As shown in Figure 6a, if the DU (i.e., the length of drain underlap region) is increased, the I AMB is further decreased. This result is obvious based on the previous studies [32,33]. However, DGIT-TFET can minimize the DU because I AMB is already restrained by large T D . It is beneficial, not only for the small parasitic resistance, but for the high integration density. Moreover, Figure 6a clearly shows that if the DU increases more than 10 nm, the I OFF becomes worse in spite of the longer DU due to the significant SRH leakage. The DGIT-TFET with 10 nm-DU shows smaller I AMB and C GD than that for 0 nm-DU with the amount of about 2.1, and 3.5 orders of magnitudes, respectively (Figure 6a,b). Considering these results, the optimum DU can be determined as~10 nm. The adoption of drain underlap region can be realized easily without any aggressive process capability issue by changing the height of STI oxide. The detail about the influence of C GD on voltage overshoot during CMOS operation will be discussed at the end of this section. In addition to the increase in TD, another strategy is required to suppress IAMB and CGD, simultaneously. As shown in Figure 6a, if the DU (i.e., the length of drain underlap region) is increased, the IAMB is further decreased. This result is obvious based on the previous studies [32,33]. However, DGIT-TFET can minimize the DU because IAMB is already restrained by large TD. It is beneficial, not only for the small parasitic resistance, but for the high integration density. Moreover, Figure 6a clearly shows that if the DU increases more than 10 nm, the IOFF becomes worse in spite of the longer DU due to the significant SRH leakage. The DGIT-TFET with 10 nm-DU shows smaller IAMB and CGD than that for 0 nm-DU with the amount of about 2.1, and 3.5 orders of magnitudes, respectively (Figure 6a,b). Considering these results, the optimum DU can be determined as ~10 nm. The adoption of drain underlap region can be realized easily without any aggressive process capability issue by changing the height of STI oxide. The detail about the influence of CGD on voltage overshoot during CMOS operation will be discussed at the end of this section.  In addition to the increase in TD, another strategy is required to suppress IAMB and CGD, simultaneously. As shown in Figure 6a, if the DU (i.e., the length of drain underlap region) is increased, the IAMB is further decreased. This result is obvious based on the previous studies [32,33]. However, DGIT-TFET can minimize the DU because IAMB is already restrained by large TD. It is beneficial, not only for the small parasitic resistance, but for the high integration density. Moreover, Figure 6a clearly shows that if the DU increases more than 10 nm, the IOFF becomes worse in spite of the longer DU due to the significant SRH leakage. The DGIT-TFET with 10 nm-DU shows smaller IAMB and CGD than that for 0 nm-DU with the amount of about 2.1, and 3.5 orders of magnitudes, respectively (Figure 6a,b). Considering these results, the optimum DU can be determined as ~10 nm. The adoption of drain underlap region can be realized easily without any aggressive process capability issue by changing the height of STI oxide. The detail about the influence of CGD on voltage overshoot during CMOS operation will be discussed at the end of this section. As above-mentioned, the vertical-structured DGIT-TFET is compatible to the SEG process for Si1-xGex/Si heterojunction formation. It is worthwhile to study the effects of heterojunction on DGIT-TFET's driving current, since the use of a narrow bandgap material can reduce the tunnel resistance drastically. Figure 7b shows transfer characteristics of DGIT-TFET according to the Ge mole fraction (xM) at source-channel junction (Figure 7a). If xM increases, ION is effectively improved, without increasing IAMB, due to the decrease of BTBT resistance. In case of 100%-xM, ION is increased more than two-orders of magnitude from that for sub-70%-xM cases because direct band-to-band tunneling (BTBT) can be utilized [16,18,27]. As above-mentioned, the vertical-structured DGIT-TFET is compatible to the SEG process for Si 1−x Ge x /Si heterojunction formation. It is worthwhile to study the effects of heterojunction on DGIT-TFET's driving current, since the use of a narrow bandgap material can reduce the tunnel resistance drastically. Figure 7b shows transfer characteristics of DGIT-TFET according to the Ge mole fraction (xM) at source-channel junction (Figure 7a). If xM increases, I ON is effectively improved, without increasing I AMB , due to the decrease of BTBT resistance. In case of 100%-xM, I ON is increased more than two-orders of magnitude from that for sub-70%-xM cases because direct band-to-band tunneling (BTBT) can be utilized [16,18,27].
Last of all, the transient characteristics of CMOS inverter composed of n-channel DGIT-TFET and p-channel DGIT-MOSFET are investigated by changing DU. In this case, 100%-xM is used as a source-channel junction for best performance. As shown in Figure 8, it is clear that DGIT-TFET inverter can be operated with less than 1 ns intrinsic delay time. There is a considerable voltage overshoot for the 0 nm-DU due to the large Miller capacitance; C GD . It is necessary to address this issue since it is problematic in terms of power consumption, reliability, and so on. As shown in the inset of Figure 8, the overshoot phenomenon is significantly suppressed as DU increases with the help of decreased C GD (Figure 6b). If 10 nm-DU (the optimized length considering I OFF and C GD ) is adopted in DGIT-TFET, overshoot voltage becomes~30 % of that for 0 nm-DU. As above-mentioned, the vertical-structured DGIT-TFET is compatible to the SEG process for Si1-xGex/Si heterojunction formation. It is worthwhile to study the effects of heterojunction on DGIT-TFET's driving current, since the use of a narrow bandgap material can reduce the tunnel resistance drastically. Figure 7b shows transfer characteristics of DGIT-TFET according to the Ge mole fraction (xM) at source-channel junction (Figure 7a). If xM increases, ION is effectively improved, without increasing IAMB, due to the decrease of BTBT resistance. In case of 100%-xM, ION is increased more than two-orders of magnitude from that for sub-70%-xM cases because direct band-to-band tunneling (BTBT) can be utilized [16,18,27]. Last of all, the transient characteristics of CMOS inverter composed of n-channel DGIT-TFET and p-channel DGIT-MOSFET are investigated by changing DU. In this case, 100%-xM is used as a source-channel junction for best performance. As shown in Figure 8, it is clear that DGIT-TFET inverter can be operated with less than 1 ns intrinsic delay time. There is a considerable voltage overshoot for the 0 nm-DU due to the large Miller capacitance; CGD. It is necessary to address this issue since it is problematic in terms of power consumption, reliability, and so on. As shown in the inset of Figure 8, the overshoot phenomenon is significantly suppressed as DU increases with the help of decreased CGD (Figure 6b). If 10 nm-DU (the optimized length considering IOFF and CGD) is adopted in DGIT-TFET, overshoot voltage becomes ~30 % of that for 0 nm-DU. Last of all, the transient characteristics of CMOS inverter composed of n-channel DGIT-TFET and p-channel DGIT-MOSFET are investigated by changing DU. In this case, 100%-xM is used as a source-channel junction for best performance. As shown in Figure 8, it is clear that DGIT-TFET inverter can be operated with less than 1 ns intrinsic delay time. There is a considerable voltage overshoot for the 0 nm-DU due to the large Miller capacitance; CGD. It is necessary to address this issue since it is problematic in terms of power consumption, reliability, and so on. As shown in the inset of Figure 8, the overshoot phenomenon is significantly suppressed as DU increases with the help of decreased CGD (Figure 6b). If 10 nm-DU (the optimized length considering IOFF and CGD) is adopted in DGIT-TFET, overshoot voltage becomes ~30 % of that for 0 nm-DU.  Figures 4b and 6b.