Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core–shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 μA/μm, off-state current (Ioff) of 1.09 × 10−12 A/μm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications.


Introduction
The power consumption of future transistors has become one of the most important problems in the semiconductor industry. As the device dimensions, such as the minimum feature size, are scaled down, the importance of the off-state power as well as the active power becomes significant. Particularly, low standby power and low supply voltage (V DD ) operation are necessary in various electronics applications, such as mobile devices, wearable devices, and internet-of-things (IoT) systems [1][2][3]. Considering these aspects, the tunnel field-effect transistor (TFET) is one of the most promising logic devices. TFETs have advantages such as low off-state current (I off ), low subthreshold swing (SS), and low power consumption compared with the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, TFETs can have an SS lower than 60 mV/dec, which cannot be achieved by the conventional MOSFETs at room temperature because of their operation mechanism [4][5][6][7]. However, the conventional silicon-based TFETs exhibit several critical problems, in particular, low on-state current (I on ). Due to the large bandgap (E g ) of Si, the amount of electron band-to-band tunneling (BTBT) is insufficient, thus resulting in a small I on [8][9][10][11]. Therefore, various studies have been conducted to improve these problems in material or structural approaches. TFETs using small E g materials, such as Ge, at the source region exhibit an improvement in the amount of source-to-channel BTBT [12]. Furthermore, III-V heterojunction TFETs have been investigated for enhancing the electrical properties [13][14][15]. In addition to those experiments, many attempts have been performed in structural approaches to overcome the drawbacks, such as line TFET, U-gate TFET, T-shaped TFET, L-shaped TFET, and vertical nanowire TFET (VNWTFET) [15][16][17][18][19][20][21][22][23][24]. However, it is still necessary to study TFETs having superior performances and a small size.
In this work, a Ge-based gate-metal-core VNWTFET has been optimally designed and analyzed using the technology computer-aided design (TCAD) simulations. By using the gate-metal-core structure, the proposed device has a wider BTBT junction and, thus, higher current drivability can be obtained at the same size as that of the conventional VNWTFETs. Direct current (DC) characteristics such as I on , I off , the on-off current ratio (I on /I off ), threshold voltage (V t ), and SS are investigated to evaluate the device performance. Moreover, several device parameters were modulated to obtain the optimized design values. Figure 1 shows the cross-sectional view of the proposed Ge-based gate-metal-core VNWTFET with a gate radius (R g ) of 10 nm and a gate dielectric thickness (T ox ) of 2 nm. The gate dielectric material is hafnium oxide (HfO 2 ), which enhances the current performances because of a higher gate controllability. The lower E g and lower electron effective mass (m e * ) of Ge can increase the BTBT rate [12]. The work function of the gate metal is 4.27 eV. The doping concentrations of the source, channel, and drain are p-type 1 × 10 20 cm −3 , p-type 1 × 10 16 cm −3 , and n-type 5 × 10 18 cm −3 , respectively. I on is defined as the drain current (I DS ) at the gate voltage (V GS ) = the drain voltage (V DS ) = 0.55 V, for low-power applications. Further, the threshold voltage (V t ) is extracted using a constant-current method [25].

Device Structure and Description
obtained at the same size as that of the conventional VNWTFETs. Direct current (DC) characteristics such as Ion, Ioff, the on-off current ratio (Ion/Ioff), threshold voltage (Vt), and SS are investigated to evaluate the device performance. Moreover, several device parameters were modulated to obtain the optimized design values. Figure 1 shows the cross-sectional view of the proposed Ge-based gate-metal-core VNWTFET with a gate radius (Rg) of 10 nm and a gate dielectric thickness (Tox) of 2 nm. The gate dielectric material is hafnium oxide (HfO2), which enhances the current performances because of a higher gate controllability. The lower Eg and lower electron effective mass (me * ) of Ge can increase the BTBT rate [12]. The work function of the gate metal is 4.27 eV. The doping concentrations of the source, channel, and drain are p-type 1 × 10 20 cm −3 , p-type 1 × 10 16 cm −3 , and n-type 5 × 10 18 cm −3 , respectively. Ion is defined as the drain current (IDS) at the gate voltage (VGS) = the drain voltage (VDS) = 0.55 V, for lowpower applications. Further, the threshold voltage (Vt) is extracted using a constant-current method [25]. Figure 2 shows the mechanism of the current flow in the proposed device. As indicated in Figure  2a, the electrons are tunneled mainly from the source to the channel regions in the lateral path and the tunneled electrons drift toward the drain region by VDS. When the positive VGS is applied, the energy bands in the channel region are lowered and BTBT occurs at the channel-source interfaces as shown in Figure 2b. Therefore, the channel thickness (Tch) and the gate-metal height (Hg) were considered as design variables for optimization processes because Tch and Hg determine the tunneling probability and current drivability. Furthermore, the proposed gate-metal-core structure has the advantage that it proposes a wider source-channel junction area (A = 2π × (Rg + Tox + Tch) × Hg) than the conventional core-shell structure (A = 2π × Tch × Hg) in the same dimensions. Additionally, in the case of TFETs, a short source-to-drain distance causes the leakage current at the off-state and the ambipolar behavior when the negative VGS is applied. Thus, the channel height (Hch) was also considered as a design paramet   Figure 2 shows the mechanism of the current flow in the proposed device. As indicated in Figure 2a, the electrons are tunneled mainly from the source to the channel regions in the lateral path and the tunneled electrons drift toward the drain region by V DS . When the positive V GS is applied, the energy bands in the channel region are lowered and BTBT occurs at the channel-source interfaces as shown in Figure 2b. Therefore, the channel thickness (T ch ) and the gate-metal height (H g ) were considered as design variables for optimization processes because T ch and H g determine the tunneling probability and current drivability. Furthermore, the proposed gate-metal-core structure has the advantage that it proposes a wider source-channel junction area (A = 2π × (R g + T ox + T ch ) × H g ) than the conventional core-shell structure (A = 2π × T ch × H g ) in the same dimensions. Additionally, in the case of TFETs, a short source-to-drain distance causes the leakage current at the off-state and the ambipolar behavior when the negative V GS is applied. Thus, the channel height (H ch ) was also considered as a design parameter. The silicon dioxide (SiO 2 ) is placed between the source and drain regions to suppress the leakage current. The device design and analysis are performed with the Sentaurus TCAD simulation. During the simulation process, various physical models were included for the higher accuracy. A nonlocal BTBT model was applied because the drive current of the proposed device is totally affected by the amount of tunneled electrons. The generation rate (Rnet) by the nonlocal BTBT mechanism can be obtained by the follow equation:

exp
(1) where F0 = 1 V/cm, P = 2.5 for the phonon-assisted tunneling process. At T = 300 K, the prefactor, A, and the exponential factor, B, for the phonon-assisted tunneling process can be expressed by the follow equations: where g is a degeneracy factor, h is Plank's constant, and Dop, εop, and Nop are the deformation potential, energy, and number of optical phonons, respectively. ρ is the mass density. mC and mV are the effective mass in the conduction band and the valance band, respectively, with the relationship of . According to the Equations (1)-(3), the proposed Ge-based TFET can achieve the higher Rnet due to the low me * and the low Eg. The Fermi-Dirac statistical model was applied because the electrons in thermal equilibrium with a semiconductor lattice obey Fermi-Dirac statistics. In addition, the Shockley-Read-Hall (SRH) recombination model, auger recombination model, and trap-assisted-tunneling (TAT) model were involved because the recombination/generation, which influences the leakage current in the device, is greatly affected by the SRH and TAT mechanism. Moreover, the bandgap narrowing model, doping dependent mobility model, and quantum confinement effect were considered to estimate the device performances more accurately [26]. Figure 3a shows the IDS-VGS transfer characteristics of the proposed gate-metal-core VNWTFETs that vary with different Tch. As Tch gets thinner, Ion increases since the effective tunneling barrier width decreases. Figure 3b depicts the energy band diagrams of the proposed devices with different Tch. The electric field across the channel region also gets stronger as Tch decreases, resulting in the enhancement of the gate controllability. Thus, the thinner Tch, having an energy band with a sharp slope, results in an increase of the electron tunneling rate. Moreover, Ioff also increases as Tch becomes The device design and analysis are performed with the Sentaurus TCAD simulation. During the simulation process, various physical models were included for the higher accuracy. A nonlocal BTBT model was applied because the drive current of the proposed device is totally affected by the amount of tunneled electrons. The generation rate (R net ) by the nonlocal BTBT mechanism can be obtained by the follow equation:

Results and Discussion
where F 0 = 1 V/cm, P = 2.5 for the phonon-assisted tunneling process. At T = 300 K, the prefactor, A, and the exponential factor, B, for the phonon-assisted tunneling process can be expressed by the follow equations: where g is a degeneracy factor, h is Plank's constant, and D op , ε op , and N op are the deformation potential, energy, and number of optical phonons, respectively. ρ is the mass density. m C and m V are the effective mass in the conduction band and the valance band, respectively, with the relationship of 1 According to the Equations (1)-(3), the proposed Ge-based TFET can achieve the higher R net due to the low m e * and the low E g . The Fermi-Dirac statistical model was applied because the electrons in thermal equilibrium with a semiconductor lattice obey Fermi-Dirac statistics. In addition, the Shockley-Read-Hall (SRH) recombination model, auger recombination model, and trap-assisted-tunneling (TAT) model were involved because the recombination/generation, which influences the leakage current in the device, is greatly affected by the SRH and TAT mechanism. Moreover, the bandgap narrowing model, doping dependent mobility model, and quantum confinement effect were considered to estimate the device performances more accurately [26]. Figure 3a shows the I DS -V GS transfer characteristics of the proposed gate-metal-core VNWTFETs that vary with different T ch . As T ch gets thinner, I on increases since the effective tunneling barrier width decreases. Figure 3b depicts the energy band diagrams of the proposed devices with different T ch . The electric field across the channel region also gets stronger as T ch decreases, resulting in the enhancement of the gate controllability. Thus, the thinner T ch , having an energy band with a sharp slope, results in an increase of the electron tunneling rate. Moreover, I off also increases as T ch becomes thinner. When T ch is 6 nm, however, I off decreases because of the increment of the resistance of the channel (R ch ), and then I off increases again as T ch further decreases. Figure 4 indicates the I on and SS characteristics of the proposed devices with the different T ch . As described earlier, it is shown that I on increases as T ch reduces. Unlike I on , however, SS improved until T ch becomes 5 nm, having the minimum value of 57.5 mV/dec, and thereafter increases because of the increment of I off . On the other hand, the ambipolar behavior was scarcely affected by T ch , since H ch , which contributes to the leakage current when the negative V GS being applied is constant. Since SS is as crucial as I on in the performance of the logic devices, it is desirable that T ch is adjusted to be 5 nm. Consequently, I on = 4.46 × 10 −5 A/µm, I off = 1.35 × 10 −11 A/µm, V t = 0.24 V, I on /I off = 3.3 × 10 6 , and SS = 57.5 mV/dec are obtained at T ch = 5 nm.   Figure 5a shows the IDS-VGS transfer characteristics of the proposed devices according to variation in Hg. Each curve was extracted from the devices with the different Hg varying from 10 to 80 nm at Tch = 5 nm. The higher Hg widens the tunneling area, resulting in the enhancement of Ion because the IDS of TFETs is totally affected by the amount of the tunneled electrons. Meanwhile, Ioff also tends to increase slightly with the higher Hg for the same reason mentioned above. However, when Hg = 30 nm and Hg = 70 nm, Ioff decreased because the increment of Rch, which resulted from the   Figure 5a shows the IDS-VGS transfer characteristics of the proposed devices according to variation in Hg. Each curve was extracted from the devices with the different Hg varying from 10 to 80 nm at Tch = 5 nm. The higher Hg widens the tunneling area, resulting in the enhancement of Ion because the IDS of TFETs is totally affected by the amount of the tunneled electrons. Meanwhile, Ioff also tends to increase slightly with the higher Hg for the same reason mentioned above. However, when Hg = 30 nm and Hg = 70 nm, Ioff decreased because the increment of Rch, which resulted from the  Figure 5a shows the I DS -V GS transfer characteristics of the proposed devices according to variation in H g . Each curve was extracted from the devices with the different H g varying from 10 to 80 nm at T ch = 5 nm. The higher H g widens the tunneling area, resulting in the enhancement of I on because the I DS of TFETs is totally affected by the amount of the tunneled electrons. Meanwhile, I off also tends to increase slightly with the higher H g for the same reason mentioned above. However, when H g = 30 nm and H g = 70 nm, I off decreased because the increment of R ch , which resulted from the longer current path, dominates over the increase of the amount of the electron tunneling at the off-state. Furthermore, the increase of R ch deteriorates the rate of the I on increment, thus, I on is gradually saturated. For these reasons, I on /I off and SS have the largest value and the lowest value at H g = 70 nm, respectively, as indicated in Figure 5b. Therefore, optimized values were obtained with I on = 8.22 × 10 −5 A/µm, I off = 1.45 × 10 −11 A/µm, V t = 0.21 V, I on /I off = 5.67 × 10 6 , and SS = 54.7 mV/dec at T ch = 5 nm and H g = 70 nm.  Figure 6a shows the IDS-VGS transfer characteristics of the proposed devices that vary with Hch. In the proposed device, the ambipolar behavior, when the negative VGS is applied, is mainly affected by the amount of the electron tunneling from the source and channel region to the drain region. Figure 6b depicts the energy band diagrams of the proposed devices that vary with Hch at VGS = −0.55 V and VDS = 0.55 V. With the lower Hch, the energy band of the channel is lowered by VDS, as in the conventional short channel TFETs [27]. Therefore, the longer Hch where VDS has less effect on the channel has the thicker tunneling barrier width at the channel-drain junction and, thus, suppresses the electron tunneling from the channel to the drain. In addition to the foregoing, as Hch increases, Rch increases because the current path also becomes longer. As a result, Ioff decreases gradually with the Hch increasing. The increase in Rch also deteriorates Ion for the same reason. Figure 7 indicates Ion/Ioff and SS characteristics of the proposed devices with the different Hch varying from 20 to 90 nm. Ion/Ioff is gradually improved as Hch increases, and is then almost saturated when Hch = 80 nm. Moreover, SS has minimum values at Hch = 80 nm and then increases at Hch = 90 nm. As mentioned above, because of the effect of Rch, Ion and Ioff decrease constantly with increasing Hch, and the decrease in Ion dominates over Ioff when Hch = 80 nm. Finally, the optimized device is achieved with Ion = 8.09 × 10 −5 A/μm, Ioff = 1.09 × 10 −12 A/μm, Vt = 0.21 V, Ion/Ioff = 7.45 × 10 7 , and SS = 42.8 mV/dec at Tch = 5 nm, Hg = 70 nm, and Hch = 80 nm.  Figure 6a shows the I DS -V GS transfer characteristics of the proposed devices that vary with H ch . In the proposed device, the ambipolar behavior, when the negative V GS is applied, is mainly affected by the amount of the electron tunneling from the source and channel region to the drain region. Figure 6b depicts the energy band diagrams of the proposed devices that vary with H ch at V GS = −0.55 V and V DS = 0.55 V. With the lower H ch , the energy band of the channel is lowered by V DS , as in the conventional short channel TFETs [27]. Therefore, the longer H ch where V DS has less effect on the channel has the thicker tunneling barrier width at the channel-drain junction and, thus, suppresses the electron tunneling from the channel to the drain. In addition to the foregoing, as H ch increases, R ch increases because the current path also becomes longer. As a result, I off decreases gradually with the H ch increasing. The increase in R ch also deteriorates I on for the same reason. Figure 7 indicates I on /I off and SS characteristics of the proposed devices with the different H ch varying from 20 to 90 nm. I on /I off is gradually improved as H ch increases, and is then almost saturated when H ch = 80 nm. Moreover, SS has minimum values at H ch = 80 nm and then increases at H ch = 90 nm. As mentioned above, because of the effect of R ch , I on and I off decrease constantly with increasing H ch , and the decrease in I on dominates over I off when H ch = 80 nm. Finally, the optimized device is achieved with I on = 8.09 × 10 −5 A/µm, I off = 1.09 × 10 −12 A/µm, V t = 0.21 V, I on /I off = 7.45 × 10 7 , and SS = 42.8 mV/dec at T ch = 5 nm, H g = 70 nm, and H ch = 80 nm. and SS characteristics of the proposed devices with the different Hch varying from 20 to 90 nm. Ion/Ioff is gradually improved as Hch increases, and is then almost saturated when Hch = 80 nm. Moreover, SS has minimum values at Hch = 80 nm and then increases at Hch = 90 nm. As mentioned above, because of the effect of Rch, Ion and      Figure 8 indicates the output characteristics of the proposed devices with different V GS . When a small V GS of 0.3 V or less is applied, I DS is almost constant and has a low value. I DS has a low value even though V DS increases because the amount of the electrons tunneled from the source to the channel region is small for a low V GS . When V GS is greater than 0.4 V, the tunneled electrons in the channel region drift toward the drain region by the positive V DS . I DS increases as a function of V DS for small V DS , then gets saturated and becomes less dependent on V DS when V DS is approximately 0.5 V, showing the proper output characteristics for circuit applications. Figure 8 indicates the output characteristics of the proposed devices with different VGS. When a small VGS of 0.3 V or less is applied, IDS is almost constant and has a low value. IDS has a low value even though VDS increases because the amount of the electrons tunneled from the source to the channel region is small for a low VGS. When The comparison of the proposed device with the different works in terms of Ion, Vt, VDD, and SS is presented in Table 1. This proposed device has the highest Ion value with the low Vt and the low VDD value. Thus, the proposed Ge-based gate-metal-core VNWTFET is a suitable candidate for the logic devices with the low power consumption.

Parameter This Work SiGe-S-NW-TFET [28]
Si-Based Nanotube TFET [29] Si/SiGe HTG-TFET [30] Ge-Source vTFET [31] Ion (μA/μm) 80.9 (at VGS = 0.55 V) 11.66 (at VGS = 1. The comparison of the proposed device with the different works in terms of I on , V t , V DD , and SS is presented in Table 1. This proposed device has the highest I on value with the low V t and the low V DD value. Thus, the proposed Ge-based gate-metal-core VNWTFET is a suitable candidate for the logic devices with the low power consumption.

Conclusions
In this work, a Ge-based gate-metal-core VNWTFET was optimally designed and analyzed based on TCAD simulations. With wider BTBT junctions, a higher current drivability can be realized compared to the conventional TFETs. The proposed device demonstrated superior DC performances with I on = 8.09 × 10 −5 A/µm, I off = 1.09 × 10 −12 A/µm, V t = 0.21 V, I on /I off = 7.45 × 10 7 , and SS = 42.8 mV/dec at H g = 70 nm, T ch = 5 nm, and H ch = 80 nm. It is ensured that the proposed device would be a promising logic device for the low-power applications.