Analysis and Design of Series-LC-Switch Capacitor Multistage High Gain DC-DC Boost Converter for Electric Vehicle Applications

Research into modern transportation systems is currently in progress in order to fully replace the traditional inter-combustible engine with a noiseless, fast, energy-efficient, and environmentally friendly electric vehicle. Electric vehicles depend on an electric motor and require highly efficient converter drive circuits. Among these converters, DC-DC boost converters play a major role in charging not only the battery banks but also in providing the DC-link excitation voltage in transformerless applications. However, the development of these converters, which have higher voltage and current gain with minimum components, minimum voltage, and current stress, is quite challenging. Therefore, this research work aims to address these issues and also to improve overall system performance. These aims are achieved by developing a series LC-based single-stage boost converter, and extending its gain through a multi-stage boost converter using switch capacitor phenomena. This article also presents a complete operating model in continuous conduction mode. The proposed converter is tested under various testing conditions, such as output loading, input voltage levels, and duty cycle ratio for a 50 W resistive load. The results are compared with existing models. The proposed converter is stated to have achieved the highest efficiency, i.e., 96.5%, along with extendable voltage gain with reduced voltage and current stresses, which is a major contribution to this research field.


Introduction
The report "Riding the Energy Transition: Oil Beyond 2040", regarding energy transition for the oil market, was published by the International Monetary Fund (IMF) in May 2017, and showed their concern for adopting electric vehicles in the upcoming future. The discussion concluded that the future of transportation will see around 290 million people (93% of the population) travel via electric vehicles (EV) in the USA [1]. However, EV performance as compared to the conventional engine is a real concern. The ideal development of the electric vehicle was compared with the outperformance of combustible cars, which would create a Kodak moment for combustion-based automakers who fail to transition to EVs.
The adoption of EV as an emerging technology solely depends on how fast EV can outperform the inter-combustible engine (ICE). Travel does not always require a top speed This worked on the principle of single inductor stored cell-based SC (SIESC-SC), with only two operating modes. However, this converter, as compared to other converters, was not suitable for lighter loads, and its efficiency was less than 90% [22]. Behdad Faridpak in [14] and Javed Ahmad et al. in [23] developed a high gain DC-DC converter using a switch inductor/capacitor mode and operated them as voltage multiplier cells (VMC). However, the developed model used multiple inductors, capacitors, and switches to form VMCs in a single-stage boost converter and still requires additional elements in boost stages. This not only increases the cost, but it also means that the offered stress is still higher than the proposed model. A similar effort with a reduced number of components, but using coupled inductors, was presented in [19]. However, calculating turn ratios is yet another job which must be performed. The obtained output voltage gain was similar to that obtained from the active network converter (SC-ANC) [24]. However, the desired number of reactive and active switches was very high. Similarly, Z-source and quasi-Z-source (QZS) in [25] serves the same purpose, although it is limited by the duty cycle (D ≤ 0.5), and the voltage gain is also slightly less than presented in [23]. The active switch along with the switch inductor and capacitor proposed in [26] and [27] offered a high gain with an extendable option, but nonetheless, it required multiple inductors and switches to operate.
It is desirable to have a maximum converter gain at around 50% of duty cycle, a fast converter response, minimum number of converter boost side elements, a minimum voltage and current stress, maximum efficiency, minimum losses, fewest operating modes, zero current switching (ZCS), and ease of control. These types of DC-DC boost converters often have limited duty cycle variations. Some converters are limited to 30%, while the rest can be adjusted between 50 and 90%.
In this paper, an easily-adjustable voltage gain non-isolated DC-DC boost converter is proposed using an LC series single stage with switch capacitors (SC). The proposed converter is capable of handling all the stated problems in [14,19,26]. This converter has only one auxiliary switch connected in series to the capacitor and inductor. The proposed converter operates using the minimum number of elements needed to produce a very high voltage gain DC-DC converter. The normalized voltage stress concerning output across the auxiliary switch linearly rises as the duty cycle approached unity, instead of rising or staying constant, such as in all existing non-isolated boost converters. The operating principle and steady-state analysis at multiple varying loads is presented in detail in the following sections. These facts are verified by using both simulation and experimental setup analysis.
The paper is organized as follows: Section 2 presents the modelling and operation of the proposed converter, Section 3 presents the analysis of the proposed converter, and Section 4 presents the results along with a discussion. Section 5 concludes the discussion.

•
The overall number of inductors, capacitors, and switches have been largely reduced. Now, only one inductor, capacitor, and switch are required for use in the single-stage boost converter. This reduces the overall size and cost of the system. • The multiple-stage boost converters are easily extendable and gain can be easily adjusted according to requirements. The PWM signal is used to control only one switch, which controls the single-stage overall gain. • The proposed design aims to reduce both device voltage and current stress in order to reduce device size. In this way, device power capacity is utilized to its maximum.

•
The proposed DC-DC converter serves as a good option for use in both EV driving and battery charging systems. Figure 1 shows the basic structure of an active network derived from the concept of capacitor (C A ) and connected inductor (L 1 ). It is switched by using an auxiliary switch. When the switch (S 1 ) is ON, the inductor is charged through the source, and when the  Figure 1 shows the basic structure of an active network derived from the concept of capacitor and connected inductor . It is switched by using an auxiliary switch. When the switch is ON, the inductor is charged through the source, and when the switch turns OFF, the voltage across the switch becomes twice the input. Both and share the same amount of voltage from the input source. Multiple capacitors and diodes on the output of the auxiliary switch form the switched-capacitor three-stage boost converter, with a series or parallel combination of capacitors as shown in Figure 2. The diodes , , , , , and capacitors , , , ,

Modelling and Operation of the Proposed Converter
, and , form the complete unit of the three-stage switched capacitor boost converter. Figure 3 shows the typical waveforms obtained during continuous conduction mode (CCM). In CCM operation, the current through the inductor never falls to zero. The operating modes of the proposed converter in the steady-state are presented in detail as follows.

CCM Operation
There are only two further operating modes in the CCM condition. These are mode 1, when the auxiliary switch is turned ON, and mode 2, when the switch turns OFF. The timing diagram for the two-stage boost converter is as in Figure 3. We will be using the timing diagram to understand the operation of this converter circuit by dividing it into intervals. Multiple capacitors and diodes on the output of the auxiliary switch form the switchedcapacitor three-stage boost converter, with a series or parallel combination of capacitors as shown in Figure 2. The diodes D 1 , D 2 , D 3 , D 4 , D 5 , and capacitors C 1 , C 2 , C 3 , C 4 , C 5 , and C 6 , form the complete unit of the three-stage switched capacitor boost converter. Figure 3 shows the typical waveforms obtained during continuous conduction mode (CCM). In CCM operation, the current through the inductor never falls to zero. The operating modes of the proposed converter in the steady-state are presented in detail as follows. Figure 1 shows the basic structure of an active network derived from the concept of capacitor and connected inductor . It is switched by using an auxiliary switch. When the switch is ON, the inductor is charged through the source, and when the switch turns OFF, the voltage across the switch becomes twice the input. Both and share the same amount of voltage from the input source. Multiple capacitors and diodes on the output of the auxiliary switch form the switched-capacitor three-stage boost converter, with a series or parallel combination of capacitors as shown in Figure 2. The diodes , , , , , and capacitors , , , ,

Modelling and Operation of the Proposed Converter
, and , form the complete unit of the three-stage switched capacitor boost converter. Figure 3 shows the typical waveforms obtained during continuous conduction mode (CCM). In CCM operation, the current through the inductor never falls to zero. The operating modes of the proposed converter in the steady-state are presented in detail as follows.

CCM Operation
There are only two further operating modes in the CCM condition. These are mode 1, when the auxiliary switch is turned ON, and mode 2, when the switch turns OFF. The timing diagram for the two-stage boost converter is as in Figure 3. We will be using the timing diagram to understand the operation of this converter circuit by dividing it into intervals.

CCM Operation
There are only two further operating modes in the CCM condition. These are mode 1, when the auxiliary switch (S 1 ) is turned ON, and mode 2, when the switch (S 2 ) turns OFF. The timing diagram for the two-stage boost converter is as in Figure 3. We will be using the timing diagram to understand the operation of this converter circuit by dividing it into intervals.

Mode 1 , :
During this time interval, a positive signal is applied at the gate of and it turns ON. The capacitor , and inductor , start to store the energy. The equivalent circuit is shown in Figure 4a. Since all the components are assumed as an ideal, their internal parasitic resistances are, therefore, ignored for the sake of simplicity. Initially, at this stage, it is also assumed that the circuit initial conditions are set to zero. Thus, the voltage induced by the inductor and the voltage stored by the capacitor is given by Equation (1). It can be seen that the DC source, , and are parallel to each other. The inductor charging current in this mode is given by Equation (2).
(1)  During this time interval, a positive signal is applied at the gate of S 1 and it turns ON. The capacitor (C A ), and inductor (L 1 ), start to store the energy. The equivalent circuit is shown in Figure 4a. Since all the components are assumed as an ideal, their internal parasitic resistances are, therefore, ignored for the sake of simplicity. Initially, at this stage, it is also assumed that the circuit initial conditions are set to zero. Thus, the voltage induced by the inductor and the voltage stored by the capacitor is given by Equation (1). It can be seen that the DC source, C A , and L 1 are parallel to each other. The inductor charging current in this mode is given by Equation (2).
During this time interval, the configuration as shown in Figure 4b, the switch turns off. The capacitor (C A ) maintains its constant voltage level, and the inductor discharges its energy. The voltage across the switch V SW can be easily evaluated by applying KVL in this loop. Therefore, the loop equation is given by Equation (3). From Equation (1) as a result of the initial condition, the voltage across the switch is given by Equation (4).
During the inductor discharging state i.e., within the same interval, the current will flow through the diode (D 1 ) and make it forward-biased, while the diode (D 2 ) becomes reverse-biased. This capacitor (C 2 ) becomes parallel to the switch and attains the voltage level using KVL is given by Equation (5). The equivalent circuit is shown in Figure 4c. Thus, the connection formed is a series, and its current in this mode is given by Equation (6).
During this time interval, a positive signal is applied at the gate of and it turns ON. The capacitor , and inductor , start to store the energy. The equivalent circuit is shown in Figure 4a. Since all the components are assumed as an ideal, their internal parasitic resistances are, therefore, ignored for the sake of simplicity. Initially, at this stage, it is also assumed that the circuit initial conditions are set to zero. Thus, the voltage induced by the inductor and the voltage stored by the capacitor is given by Equation (1). It can be seen that the DC source, , and are parallel to each other. The inductor charging current in this mode is given by Equation (2). (1) Sustainability 2022, 14, x FOR PEER REVIEW 6 of 24

Mode 2 , :
During this time interval, the configuration as shown in Figure 4b, the switch turns off. The capacitor maintains its constant voltage level, and the inductor discharges its energy. The voltage across the switch can be easily evaluated by applying KVL in this loop. Therefore, the loop equation is given by Equation (3). From Equation (1) as a result of the initial condition, the voltage across the switch is given by Equation (4).
During the inductor discharging state i.e., within the same interval, the current will flow through the diode and make it forward-biased, while the diode becomes reverse-biased. This capacitor becomes parallel to the switch and attains the voltage level using KVL is given by Equation (5). The equivalent circuit is shown in Figure 4c. Thus, the connection formed is a series, and its current in this mode is given by Equation (6).

2
(5) During this interval, the converter again enters mode 1, when the turns ON. However, this time the inductor and capacitors hold the previous states and become  During this interval, the converter again enters mode 1, when the (S 1 ) turns ON. However, this time the inductor and capacitors hold the previous states and become charged again as well, while C 2 maintain its charge. At this position, the voltage across the switch sets to zero, and the diode D 1 becomes reverse-biased. At this stage, the capacitor C 2 that was previously charged to the switch voltage level will now start to discharge through diode (D 2 ) to charge capacitor (C 1 ) at the same potential level. Using KVL, the steady-state voltage across C 1 is given by Equation (7), and the equivalent circuit is shown in Figure 4d.
Each capacitor in this three-stage boost converter follows the same charging principle, and shares the equivalent switch voltage. In each operating mode, if C 2 , C 4 , C 6 . . . are charging then C 1 , C 3 , C 5 . . . will be discharging to charge the other side, and vice versa.

Converter Gain
For the sake of simplicity, it is assumed that the output load is connected across C 2 . The voltage across the inductor is given by Equation (8). In CCM the inductor current is evaluated by considering both modes, i.e., one complete cycle. During the ON state i.e mode 1, the inductor current, given that all initial conditions are zero and using the inductor voltage from Equation (1) in mode 1, is given by Equation (9), respectively. Similarly, during mode 2 which is the OFF stage, the inductor current is computed by Equation (10). In If the converter is operating in a steady-state condition, the average current through the inductor will remain the same in both on and off conditions. Therefore, from Equations (9) and (10) we can determine the gain of the converter when the load is connected at the first stage i.e., across C 2 as in Equation (12).
If the load is connected to C 4 , then the gain of the converter at the second stage is given by Equation (13). The equivalent circuit for this type of configuration is shown in Figure 5. For the j th stage of the boost converter, the converter gain is given by Equation (12), and the output voltage (V o ) for the extendable converter is given by Equation (15).
where, j is any stage from 1, 2, 3, . . . n (14)  Figure 5. Equivalent circuit in mode 2 when the load is connected to .

Voltage Stress
The switches in the proposed converter undergo stress when they are in the off state. For the converter shown in Figure 2, the switch voltage stress is three lower than the output voltage. The net conclusion is that in this proposed converter, the switch stress across MOSFET, diodes and, capacitor will be . This is a major contribution of this research, as the element voltage stress within this converter will not be affected by converter gain extension. Additionally, as in Equation (20), it is the contribution of this research that the switch stress from sources other than conventional converters is significantly reduced by increasing the duty cycle ratio.
The normalized voltage stress across the power switch or in terms of … Figure 5. Equivalent circuit in mode 2 when the load is connected to C 4 .
According to KCL, the average input current and the average inductor currents for this converter are given by Equations (16) and (17) respectively. Based on the input to output power balance. We can write inductor current from Equation (17) in terms of gain for any (j) stage and the input to output current gain is mentioned by Equation (19).
The proposed converter works on the principle of zero switch current (ZSC). If the converter fails to follow the current, the diodes D 1 , D 2 , D 3 , D 4 , and D 5 will undergo the reverse recovery problem during the OFF condition.

Voltage Stress
The switches in the proposed converter undergo stress when they are in the off state. For the converter shown in Figure 2, the switch voltage stress is three lower than the output voltage. The net conclusion is that in this proposed converter, the switch stress across MOSFET, diodes and, capacitor will be j −1 V o . This is a major contribution of this research, as the element voltage stress within this converter will not be affected by converter gain extension. Additionally, as in Equation (20), it is the contribution of this research that the switch stress from sources other than conventional converters is significantly reduced by increasing the duty cycle ratio.
The normalized voltage stress across the power switch in terms of CCM gain and that of the diodes is given by Equation (21).

Current Stress
The normalized inductor current stress ( I L I in ) can be obtained by modifying Equations (16) and (18) to obtain Equation (22).

Analysis of the Proposed Converter
In this section, we have analyzed our proposed converter in terms of current and voltage gain, and have compared the results with the existing boost as shown in Figures 6-12. The proposed converter is also analyzed by relating the impacts of extending boosting stages and output voltage as a function of duty cycle variation. This section will also relate voltage and current stress levels by comparing the proposed converter with existing models. The steady-state analysis and loss analysis model for the proposed converter is also presented in its sub-section. At the end of this section, a complete design method based on the required inductor and capacitor selection is presented in detail.
Additionally, these converters do not offer a high degree of freedom to adjust a smooth output voltage. Their system also becomes unstable/discontinued above this limit. However, switch capacitor active switch LC network (SC-AS-LC) [26], coupled inductor switch capacitor (CL-SC) [19], switch capacitor active network converter (SC-ANC) [24], and the proposed converter not only provide high voltage gains, but are also controllable for the entire range of varying 0.9. However, these converters are not preferred due to the high current stress level.   Additionally, these converters do not offer a high degree of freedom to adjust a smooth output voltage. Their system also becomes unstable/discontinued above this limit. However, switch capacitor active switch LC network (SC-AS-LC) [26], coupled inductor switch capacitor (CL-SC) [19], switch capacitor active network converter (SC-ANC) [24], and the proposed converter not only provide high voltage gains, but are also controllable for the entire range of varying 0.9. However, these converters are not preferred due to the high current stress level.   According to the input-output power balance, the current gain of the proposed converter significantly decreases as the duty cycle ratio is increased, as in Figure 9. This also justifies that, as the number of stages increases, the current gain for the same connected load will decrease, while the output voltage will increase. Hence, the results obtained from Equation (19) are justifiable, and the voltage gain will rise significantly. This causes a considerably higher inductor current to pass through it, which is why the inductor current to the output current ratio for each stage will be raised, as in Figure 10. Therefore, the proposed converter requires a high current inductor and MOSFET to support such a value of inrush current. However, if the input voltage level is enhanced for the same output side load, the requirement of inductor current will gradually decrease. Based on the inductor to output current gain analysis as shown in Figure 10, to support a large number of stages an inductor current support and input voltage rating must be specified first. The number of the boost stage depends on the amount of gain demanded, as in Equation (14) and Equation (19). The second factor is the selection of LC and switch parameters, as demonstrated in the next sections. The number of boost stages for the same input voltage can be theoretically extended up to the jth level for higher voltage gain and, for the fixed duty cycle, as shown in Figure 10. However, as demonstrated practically in the next section, the gain starts to saturate for each jth stage as the D approaches unity. This is mainly because at a higher value of D, the input switch side current becomes high, which causes conduction losses and, secondly, at each higher stage of j the inductor current becomes very high which causes significant inductor power loss. Therefore, the best way for the proposed design to overcome this issue is to raise the level of input voltage level to extend the gain stages. The inductor current to the output current gain for the five stages of the proposed converter is also compared with the normalized inductor current gain of the existing topologies [14,19,24,26,27] in Figure 11. It can be seen that the proposed converter inductor current gain is very high among all the other types of converters. This is mainly because when the switch is opened, the capacitor, together with the input source currents, becomes higher in magnitude in order to charge the capacitors in the boost stage. This is shown by Equation (22). Its higher current is the main thrust to support a large number of finite multiple boost stage capacitor charges. The inductor current gain for the SL-SC and SL-DS-DC converter is the same, and also offers limited gain. However, the SL-SC type converter is among the lowest to offer inductor current gain and, thus, offers the limited extending option. This comparison also suggests that the proposed converter can step up a very low voltage i. e., 1 V to around several times higher than its input voltage.
In this regard, the proposed converter requires a high current rating inductor to handle this gain. The comparison analysis also reveals that the proposed converter is also well suited for high power applications, especially in DWPT battery charging systems. best way for the proposed design to overcome this issue is to raise the level of input voltage level to extend the gain stages. The inductor current to the output current gain for the five stages of the proposed converter is also compared with the normalized inductor current gain of the existing topologies [14,19,24,26,27] in Figure 11. It can be seen that the proposed converter inductor current gain is very high among all the other types of converters. This is mainly because when the switch is opened, the capacitor, together with the input source currents, becomes higher in magnitude in order to charge the capacitors in the boost stage. This is shown by Equation (22). Its higher current is the main thrust to support a large number of finite multiple boost stage capacitor charges. The inductor current gain for the SL-SC and SL-DS-DC converter is the same, and also offers limited gain. However, the SL-SC type converter is among the lowest to offer inductor current gain and, thus, offers the limited extending option. This comparison also suggests that the proposed converter can step up a very low voltage i. e., 1 V to around several times higher than its input voltage.
In this regard, the proposed converter requires a high current rating inductor to handle this gain. The comparison analysis also reveals that the proposed converter is also well suited for high power applications, especially in DWPT battery charging systems.  stress of the existing models, when compared to the proposed design, is still higher. On the other hand, the proposed converter model and CL-SC converter diode voltage stress is the same, and is, in fact, quite low at almost 1: 8 times that of SC-ANC, SC-AS-LC, and SL-DS-DC. The proposed designed converter is almost 1/75 part of the NVS level of the existing models i.e., SC-ANC, SC-AS-LC, and SL-DS-DC, which is the major contribution of the proposed design. Similarly, Figure 13 relates the normalized switch voltage stress with the voltage gain of the converters. Here, for most of the schemes, the stress level for the switch is different as compared to diodes. The switch voltage stress / for the proposed and CL-SC converter is the same i.e., 1: 5 . The SC-ANC and SL-SC, on the other hands, are the same but higher than our proposed converter i.e., (7: 30 . However, among all of these, SL-DS-DC appears to undergo the highest / stress ratio i.e., 7: 15 . It is to be noted that all the results obtained and compared are valid for CCM, and are justifiable for mathematical forms obtained from Equations (19)- (22).

Voltage and Current Gain Analysis
The proposed converter is analyzed for five stages as in Figure 6, and its voltage gain as a function of the duty cycle corresponding to Equation (14) is shown in Figure 7. Each stage of the converter has a maximum limit for attaining voltage gain as the D approach the unity. For each stage of the converter, when increasing the duty cycle of the converter, its gain linearly increases. As the D approaches unity, the system gain suddenly begins to rise in a nonlinear way. The proposed converter is also compared with the existing voltage gain models as in Figure 8. The switched inductor double switch DC converter (SL-DS-DC) [27] and switch inductor switch capacitor (SL-SC) [14] in Figure 8 have a good range of voltage gain but, nonetheless, are limited by voltage gain adjustment i.e., (D =≤ 0.4). Additionally, these converters do not offer a high degree of freedom to adjust a smooth output voltage. Their system also becomes unstable/discontinued above this limit. However, switch capacitor active switch LC network (SC-AS-LC) [26], coupled inductor switch capacitor (CL-SC) [19], switch capacitor active network converter (SC-ANC) [24], and the proposed converter not only provide high voltage gains, but are also controllable for the entire range of varying D ≤ 0.9. However, these converters are not preferred due to the high current stress level.
According to the input-output power balance, the current gain of the proposed converter significantly decreases as the duty cycle ratio is increased, as in Figure 9. This also justifies that, as the number of stages increases, the current gain for the same connected load will decrease, while the output voltage will increase. Hence, the results obtained from Equation (19) are justifiable, and the voltage gain will rise significantly. This causes a considerably higher inductor current to pass through it, which is why the inductor current to the output current ratio for each stage will be raised, as in Figure 10. Therefore, the proposed converter requires a high current inductor and MOSFET to support such a value of inrush current. However, if the input voltage level is enhanced for the same output side load, the requirement of inductor current will gradually decrease. Based on the inductor to output current gain analysis as shown in Figure 10, to support a large number of stages an inductor current support and input voltage rating must be specified first.
The number of the boost stage (j) depends on the amount of gain demanded, as in Equations (14) and (19). The second factor is the selection of LC and switch parameters, as demonstrated in the next sections. The number of boost stages for the same input voltage can be theoretically extended up to the jth level for higher voltage gain and, for the fixed duty cycle, as shown in Figure 10. However, as demonstrated practically in the next section, the gain starts to saturate for each jth stage as the D approaches unity. This is mainly because at a higher value of D, the input switch side current becomes high, which causes conduction losses and, secondly, at each higher stage of j the inductor current becomes very high which causes significant inductor power loss. Therefore, the best way for the proposed design to overcome this issue is to raise the level of input voltage level to extend the gain stages.
The inductor current to the output current gain for the five stages of the proposed converter is also compared with the normalized inductor current gain of the existing topologies [14,19,24,26,27] in Figure 11. It can be seen that the proposed converter inductor current gain is very high among all the other types of converters. This is mainly because when the switch is opened, the capacitor, together with the input source currents, becomes higher in magnitude in order to charge the capacitors in the boost stage. This is shown by Equation (22). Its higher current is the main thrust to support a large number of finite multiple boost stage capacitor charges. The inductor current gain for the SL-SC and SL-DS-DC converter is the same, and also offers limited gain. However, the SL-SC type converter is among the lowest to offer inductor current gain and, thus, offers the limited extending option. This comparison also suggests that the proposed converter can step up a very low voltage (i.e., V in = 1 V) to around several times higher than its input voltage. In this regard, the proposed converter requires a high current rating inductor to handle this gain. The comparison analysis also reveals that the proposed converter is also well suited for high power applications, especially in DWPT battery charging systems. Similarly, Figure 13 relates the normalized switch voltage stress with the voltage gain of the converters. Here, for most of the schemes, the stress level for the switch is different as compared to diodes. The switch voltage stress (NVS/G v ) for the proposed and CL-SC converter is the same i.e., (1:5). The SC-ANC and SL-SC, on the other hands, are the same but higher than our proposed converter i.e., (7:30) . However, among all of these, SL-DS-DC appears to undergo the highest NVS/G v stress ratio i.e., (7:15). It is to be noted that all the results obtained and compared are valid for CCM, and are justifiable for mathematical forms obtained from Equations (19)- (22).  Similarly, Figure 13 relates the normalized switch voltage stress with the voltage gain of the converters. Here, for most of the schemes, the stress level for the switch is different as compared to diodes. The switch voltage stress / for the proposed and CL-SC converter is the same i.e., 1: 5 . The SC-ANC and SL-SC, on the other hands, are the same but higher than our proposed converter i.e., (7: 30 . However, among all of these, SL-DS-DC appears to undergo the highest / stress ratio i.e., 7: 15 . It is to be noted that all the results obtained and compared are valid for CCM, and are justifiable for mathematical forms obtained from Equations (19)- (22).  The comparison of the proposed design in terms of minimum component requirement with common gain, switch voltage and current stress, and maximum achieved efficiency is presented in the next section.

Steady-State Analysis
By fixing the duty cycle at around 50% and setting input voltage to 7 volts, the circuit as shown in Figure 9 achieves the steady-state in almost 200 ms. The steady-state output voltage and current waveform of the 5th stage DC-DC boost converter is shown in Figure 14. The system rise time is 23 ms, while the system percentage overshoot is 34.9%. Since the response of the system is underdamped, the oscillations completely die out around 180 ms. The comparison of the proposed design in terms of minimum component requirement with common gain, switch voltage and current stress, and maximum achieved efficiency is presented in the next section.

Steady-State Analysis
By fixing the duty cycle at around 50 % and setting input voltage to 7 volts, the circuit as shown in Figure 9 achieves the steady-state in almost 200 ms. The steady-state output voltage and current waveform of the 5th stage DC-DC boost converter is shown in Figure 14. The system rise time is 23 ms, while the system percentage overshoot is 34.9%. Since the response of the system is underdamped, the oscillations completely die out around 180 ms.

Loss Analysis
Various types of losses are affiliated with the DC-DC converter. The majority of the commonly associated losses are with diodes, the MOSFETs/IGBTS capacitor, and inductor losses. In Equations (23)-(31), the efficiency of the proposed converter is calculated for the fifth stage boost converter. It is assumed that the converter is ripple-free in current and voltage.
The losses affiliated with any IGBT or MOSFET include conduction losses, switching power losses and, if the output side capacitance is considered linear, side capacitance loss. The conduction loss for MOSFET and IGBT is given by Equations (23) and (24), while the output side capacitance loss is given by Equations (25) and (26).
The power loss associated with diodes in any converter during conduction is related by Equations (27)

Loss Analysis
Various types of losses are affiliated with the DC-DC converter. The majority of the commonly associated losses are with diodes, the MOSFETs/IGBTS capacitor, and inductor losses. In Equations (23)-(31), the efficiency of the proposed converter is calculated for the fifth stage boost converter. It is assumed that the converter is ripple-free in current and voltage.
The losses affiliated with any IGBT or MOSFET include conduction losses, switching power losses and, if the output side capacitance is considered linear, side capacitance loss. The conduction loss for MOSFET and IGBT is given by Equations (23) and (24), while the output side capacitance loss is given by Equations (25) and (26).
The power loss associated with diodes in any converter during conduction is related by Equations (27)-(29). The inductor loss due to ESR is given by Equation (30). The efficiency of the system is given by Equation (31), where, P loss is the sum of power loss across MOSFET/IGBT, diodes, and the inductor from Equations (23)-(30).

Design Analysis
In this section, we will analyze the minimum size requirement of the inductor, capacitor, and diodes based on their voltage stress, current stress, and ripple factors. For this purpose, it is necessary to have information regarding average current in case of inductance selection and voltage rating while selecting the capacitor size. This is because the capacitance and switching frequency play a major role in reducing the ripples in output voltage. Indeed, frequency and inductance selection reduce the ripples in current.
The capacity of a plate to store a charge on any plate is given by Equation (32), and the current through any conductor is given by Equation (34). After substituting Equation (32) in Equation (33), the minimum capacitance to reduce the ripple in output voltage for the proposed converter is given by Equation (34).

∆Q = C∆V
(32) The average current passing through the inductor when the switch is turned on is equivalent to the input current, and the voltage induced around it is given by Equation (35). When we substitute Equation (14) in Equation (34), we can obtain the minimum inductance requirement for the proposed converter in Equation (36). From Equation (36), we can design an inductor for any stage output voltage and with the desired ripple current ∆i.
The selection of MOSFET and switches can be easily carried out based on the required gain from Table 1. The proposed converter is designed to step up a minimum of five volts input to 50 volts output by using only the 5th stage boost converter. It can be easily extended up to the 10th stage but, due to input current limitations, the prototype is designed for only the 50 W test.

Experimental Results and Discussion
This section discusses the performance of the proposed converter. The following experiments are conducted to test the voltage regulation, system gain, output power delivered, inductor current to output current, and system efficiency by changing the duty cycle ratio. The proposed system can take any value of input voltage between 1-11 V. The maximum boosted voltage achieved at 10 V input is approximately 70 volts, and the maximum achieved power from this system is 50 W at a 100 Ω resistive load. A 50 kHz and a 15 V peak pulse voltage is applied to the gate of the Infineon IPW60R045CP. The experimental results are summarized from Figures 15-24. The required set of equipment and components used during the experiment is summarized in Table 1. For comparison, the different levels between 5-10 V are applied at the input side of the converter. delivered, inductor current to output current, and system efficiency by changing the duty cycle ratio. The proposed system can take any value of input voltage between 1 11 V. The maximum boosted voltage achieved at 10 V input is approximately 70 volts, and the maximum achieved power from this system is 50 W at a 100 Ω resistive load. A 50 kHz and a 15 V peak pulse voltage is applied to the gate of the Infineon IPW60R045CP. The experimental results are summarized from Figures 15-24. The required set of equipment and components used during the experiment is summarized in Table 1. For comparison, the different levels between 5 10 V are applied at the input side of the converter.
In Figure 15, the voltage gain analysis for varying duty cycles at three different input voltage levels 5 V, 7 V & 10 V is summarized. The system voltage gain for any input voltage is the same but, it must be noted that it linearly rises as increases. These results align to Equation (14), and the system gain remains almost linear till it crosses 50%. Following this, the system tends to become nonlinear, and practically no further gain enhancement is achieved typically after 60%. The inductor current to output current ratio as a function of the duty cycle at three input voltage levels is presented in Figure 16.
As the duty cycle increases, the / ratio gradually tends to decrease. The decrement in inductor current gain is more pronounced at higher voltage levels. This is because of the input to output power balance, as discussed in the previous section. In Figure 17, power regulation at different input voltage levels as a function of is presented. As the input voltage level is increased, the output power also shows a significant increase. This demonstrates that, for a large duty cycle ratio or turn-on time, both output voltage and current increase the higher the power level goes. The output power level difference also shows that for high input voltage levels, the output power rise will be significantly higher. This means that for a low voltage, such as a 5 V input, there is a slight power loss across semiconducting devices. ower (W) Figure 16. Inductor to output current gain analysis for different voltages.
In Figure 17, power regulation at different input voltage levels as a function of is presented. As the input voltage level is increased, the output power also shows a significant increase. This demonstrates that, for a large duty cycle ratio or turn-on time, both output voltage and current increase the higher the power level goes. The output power level difference also shows that for high input voltage levels, the output power rise will be significantly higher. This means that for a low voltage, such as a 5 V input, there is a slight power loss across semiconducting devices. We also tested the system against load variation. Since the proposed system is designed for a minimum of 100 Ω (section 3D), it is not recommended to use it with resistances lower than the designed value, otherwise the system gain will drastically drop. However, for any value of load the design procedure, as discussed in the previous section, must be considered. The experimental results to validate this fact are performed for the 7 volt input, as shown in Figure 18. In this experiment, the duty cycle is fixed at 50%, while the resistive load is decreased in steps from 40 Ω to 100 Ω. The output current increases with it, while the power drops from 15 W to 10 W, respectively. The overall gain decreases by 33%. This means that the voltage gain is dependent over load resistance.
Output Power (W) To justify the proposed design, overall performance analysis is justified based on the power transfer efficiency from input to the output side of the system. The system input voltage is fixed at 10 volts while the duty cycle ratio is changed between 10 70 %, and is calculated based on the calculations presented in Section (3D). However, the overall result is presented in Figure 19 against various levels of output power, and is completely tabulated in Table 2. To justify the proposed design, overall performance analysis is justified based on the power transfer efficiency from input to the output side of the system. The system input voltage is fixed at 10 volts while the duty cycle ratio is changed between 10 70 %, and is calculated based on the calculations presented in Section (3D). However, the overall result is presented in Figure 19 against various levels of output power, and is completely tabulated in Table 2.  Figure 20. It can be seen that as the switch turns off, boost voltage appears across its drain terminal, while the inductor current begins to fall to zero at the same time. The inverse happens when the switch turns on. The switching current and output (voltage, current) waveforms are presented in Figure 21. The ripples in the output current and voltage are measured to be less than 5% of the rated values. The average current flowing through boost stage one diode as a demo, as a function of          In Figure 15, the voltage gain analysis for varying duty cycles at three different input voltage levels (5 V, 7 V & 10 V) is summarized. The system voltage gain for any input voltage is the same but, it must be noted that it linearly rises as D increases. These results align to Equation (14), and the system gain remains almost linear till it crosses 50%. Following this, the system tends to become nonlinear, and practically no further gain enhancement is achieved typically after D = 60%. The inductor current to output current ratio as a function of the duty cycle at three input voltage levels is presented in Figure 16. As the duty cycle increases, the I L /I o ratio gradually tends to decrease. The decrement in inductor current gain is more pronounced at higher voltage levels. This is because of the input to output power balance, as discussed in the previous section.
In Figure 17, power regulation at different input voltage levels as a function of D is presented. As the input voltage level is increased, the output power also shows a significant increase. This demonstrates that, for a large duty cycle ratio or turn-on time, both output voltage and current increase the higher the power level goes. The output power level difference also shows that for high input voltage levels, the output power rise will be significantly higher. This means that for a low voltage, such as a 5 V input, there is a slight power loss across semiconducting devices.
We also tested the system against load variation. Since the proposed system is designed for a minimum of 100 Ω (section 3D), it is not recommended to use it with resistances lower than the designed value, otherwise the system gain will drastically drop. However, for any value of load the design procedure, as discussed in the previous section, must be considered. The experimental results to validate this fact are performed for the 7 volt input, as shown in Figure 18. In this experiment, the duty cycle is fixed at D = 50%, while the resistive load is decreased in steps from 40 Ω to 100 Ω. The output current increases with it, while the power drops from 15 W to 10 W, respectively. The overall gain decreases by 33%. This means that the voltage gain is dependent over load resistance.
To justify the proposed design, overall performance analysis is justified based on the power transfer efficiency from input to the output side of the system. The system input voltage is fixed at 10 volts while the duty cycle ratio is changed between 10-70 %, and is calculated based on the calculations presented in section (3D). However, the overall result is presented in Figure 19 against various levels of output power, and is completely tabulated in Table 2. The experimental result of our proposed converter is presented for voltages and current in Figures 20-23. The control signal, which ensures zero switching currents (ZSC) for the proposed converter, is presented in Figure 20. It can be seen that as the switch turns off, boost voltage appears across its drain terminal, while the inductor current begins to fall to zero at the same time. The inverse happens when the switch turns on. The switching current and output (voltage, current) waveforms are presented in Figure 21. The ripples in the output current and voltage are measured to be less than 5% of the rated values. The average current flowing through boost stage one diode as a demo, as a function of switching voltage, is shown in Figure 23. The current switching is all according to the phenomena already explained in Section 2.1.
The experimental gate voltage, drain to source voltage, and current waveforms for 5 V input voltage and at D = 50% is shown in Figure 20. It shows that as the gate voltage transit to zero, the V DS peaks and, at the same instant, the drain current switches to zero, which ensures the zero current switchings (ZCS) condition. The output current and voltage waveforms at this condition are presented in Figure 21. Additionally, the zoomed-in version for this value of current and voltage waveforms is also shown in the lower side window of Figure 23. The ripples in current and voltage are very low, i.e., 4 mA and 1 V respectively. These values make around a 0.7% and 2% ripple factor of the output levels. This output voltage is also compared with the waveforms of switching voltage and current in Figure 23. The average diode current waveform connected to the load side is a current waveform in comparison to gate switching voltage is shown in Figure 22.
The performance analysis of the proposed converter in terms of voltage gain and current gain, along with maximum achieved efficiency and a minimum number of elements required in a single-stage boost converter, is presented in Table 3. Among these converters, SC-ANC, SC-AS-LC, and SL-DS-DC require at least two MOSFET switches to perform the analysis, while our proposed converter performs its work using only one MOSFET. Similarly, SC-AN, CL-SC and, SC-AS-LC-based topology require two minimum inductors to perform the single-stage boost converter. However, our converter performs its operation with only one inductor. The other components, such as diodes and capacitors, are variable, as they can be adjusted to achieve desired boost voltage level. The proposed converter not only reduces the overall size, but it also improves efficiency. Additionally, it also reduces control complexity and the number of single-stage boosting elements, which is the major contribution of the proposed work. The output voltage is almost smooth, and contains almost negligible ripples in current and voltage. The overall lab prototype of the proposed system is demonstrated in Figure 24.