A High Step-up DC-DC Converter Based on the Voltage Lift Technique for Renewable Energy Applications

: High gain DC-DC converters are getting popular due to the increased use of renewable energy sources (RESs). Common ground between the input and output, low voltage stress across power switches and high voltage gain at lower duty ratios are desirable features required in any high gain DC-DC converter. DC-DC converters are widely used in DC microgrids to supply power to meet local demands. In this work, a high step-up DC-DC converter is proposed based on the voltage lift (VL) technique using a single power switch. The proposed converter has a voltage gain greater than a traditional boost converter (TBC) and Traditional quadratic boost converter (TQBC). The effect of inductor parasitic resistances on the voltage gain of the converter is discussed. The losses occurring in various components are calculated using PLECS software. To confirm the performance of the converter, a hardware prototype of 200 W is developed in the laboratory. The simulation and hardware results are presented to determine the performance of the converter in both open-loop and closed-loop conditions. In closed-loop operation, a PI controller is used to maintain a constant output voltage when the load or input voltage is changed.


Introduction
The present alarming situation of depletion of non-renewable energy sources presents an opportunity to look for alternative energy sources. RESs are a good option to replace fossil fuel energy and nuclear energy for electrical power generation. In recent years, the share of RESs in power generation has increased significantly. Distributed generation (DG) technologies utilize RESs in the form of solar cells, fuel cells and wind turbines etc. [1,2]. To tackle the problem of environmental pollution and global warming caused by fossil fuels, sustainable energy production can be achieved by renewable [3,4] energy sources. Renewable energy systems and energy storage systems are going to play an important role in the future of low-carbon energy emission systems [5].
RESs are integrated with battery energy storage systems (BESSs), are not only environmentally friendly but also result in the wide use of DC (Direct Current) systems, i.e., DC generation and DC storage units. To inject this power into the alternating current (AC) Distribution Grid, DC-AC power electronic converters are used. Similarly, AC-DC and DC-AC conversion are used in AC drives. Moreover, the DC loads such as electric vehicles (EVs), light-Emitting Diode systems (LED), DC motors, data centres, and other bat- DC-DC converters act as a medium between the load and the source. They are broadly classified into two types in the literature: isolated and non-isolated. Traditional boost converters (TBC), as shown in Figure 2a, if deployed in microgrids, would have to be operated at high values of the duty ratio which causes high current and voltage stress on the power devices of the converter. The voltage drop across the parasitic resistance (ESR) of capacitors and inductors increases substantially at higher duty ratios, leading to the decrease in voltage gain and efficiency of the conventional boost converter [9][10][11]. To address these problems, several DC-DC converters topologies have been proposed. In [10] a review of o various boosting techniques such as the use of voltage multipliers to multiply the boost factor, and switched inductor, switched capacitor, magnetic coupling, and multistage techniques. Several high-gain DC-DC converters are proposed using these techniques. In [11] the converter uses a voltages doubler to increase the voltage gain. Several converters use isolated high-frequency transformers to obtain voltage gain by increasing the turns ratio of the transformer. However, such circuits are bulky, costly, and more complex., Moreover, the leakage inductance of the transformer would interfere with switch operation [10,11].
Non-isolated converters are further classified into two types, namely, coupled inductor and non-coupled [12]. In the coupled-inductor-based converters, the output can be boosted by selecting a suitable turn ratio of the inductor coil. The leakage inductance of the coupled inductor is inexorable, which generates a spike in switch current and demands clamping [13]. Several applications do not require an isolated converter; in such cases, non-isolated DC-DC converters are preferred to achieve high voltage gains [14][15][16]. A modified structure of the quadratic boost converter is obtained by using a switched inductor module in place of the inductor to obtain the voltage gain twice the TQBC [17,18]. Additionally, the combination of different converters can give rise to new converters. A modified SEPIC converter is used to achieve higher gain by amalgamating the conventional SEPIC with the boosting module [19]. A novel buck-boost topology is derived in [20] by combining one traditional boost converter, one traditional buck converter, and one traditional buck-boost converter using only one power switch to obtain quadratic voltage gain. Another buck-boost topology is presented in [21]. Hybrid switched-capacitor quadratic boost converters with very high DC gain and low voltage stress on power devices are presented in [22]. A larger gain is obtained by a hybrid switched-capacitor technique in [23]. The low voltage stress on power semiconductor devices allows using lower-rated MOSFET with low on-resistance to obtain better efficiency by reducing conduction and switching loss [23].
The voltage lift (VL) technique is a well-known method widely used in electronic circuit design. In recent years, it has been successfully used in DC-DC converter applications and paved the way for the design of high voltage gain converters. The use of the VL technique was confirmed by Luo by developing DC-DC converters [24]. It uses extra energy storage elements inductors and capacitors to enhance the voltage gain of the circuit. Luo proposed a series of positive output Luo converters, such as a self-lift circuit, re-lift circuit, triple-lift, and quadruple-lift boost converters. This technique was used to overcome the effects of the parasitic elements and to boost the voltage at the output. In [25] a high-gain converter using the VL technique to achieve gain equal to twice the traditional boost converter using two inductors, but this converter has switch stress equal to the output voltage. A voltage doubler circuit such as Cockroft-Walton can be used to increase the output voltage [26], and it reduces the voltage stress across the switch. Additionally, the VL technique is used in [25][26][27][28] with a voltage doubler. A non-isolated DC-DC converter based on the VL technique was used to obtain a negative voltage concerning the ground [29]. The isolated category of converter bases on interleaving technique is proposed in ref. [30] In this paper, the proposed non-isolated quadratic boost converter utilizes the dual voltage lift (VL) technique to increase the gain of the converter. The proposed topology has the following advantages.
1. The voltage gain is greater than TBC and QBC. 2. The voltage stress on the power switch is lower than the output voltage. 3. The voltage doubler is avoided to increase the voltage gain. 4. A single power switch that makes control easy reduces gate drive requirements. 5. The low voltage stress on power devices reduces the power losses, hence the converter efficiency is increased. 6. A common ground connection is available between the source and load.

Operating Principle of the D-VL Converter
The proposed schematic illuminated in Figure 2c uses two voltage lift cells. The combination of L1, C1, and D1 is the first voltage lift cell (VL-1), whereas the similar combination of L2, C2, and D2 is (VL-2). The proposed converter has two inductors, four capacitors, and five diodes. The converter utilizes a single power switch, so the control is very easy. Taking a single voltage lift cell (VL-1), when Switch S is ON, the additional capacitor C1 is connected in parallel with Inductor L1 and charged by an input DC source. When the switch is OFF, the energy storage capacitor C1 is connected in series with DC input, and Inductor L1 discharges energy to pure resistive load R. Same situation occurs in VL-2. This way, voltage gain improvement is achieved and reduced switch stress over a traditional quadratic boost converter (TQBC), as depicted in Figure 2b.

Continuous Conduction Mode (CCM) of the D-VL Converter
The continuous conduction mode of the D-VL converter can be analyzed in two modes of operation.
Mode 1 (t1 < t < t0): The equivalent circuit related to this mode is shown in Figure 3a. inductor L1 is charged by input source Uin through D3 and S. Moreover, inductor L2 is charge by capacitors C1 and C2 through S. In this interval, inductor currents have a positive slope and store energy. The output DC load is fed by output capacitor voltage UC0. Waveform's profile of the proposed converter is shown in Figure 4. The governing voltage equations are as follows where represents the voltage across the corresponding components. Mode 2(t1 < t < S): Switch S is turned off in this mode. The equivalent circuit of this mode is shown in Figure 3b. Inductors L1 and L2 discharge through D2, C2, and D0, C0, respectively. Waveform's profile of the proposed converter is shown in Figure 4. The governing voltage equations are as follows:

Voltage Gain Calculation
During steady-state conditions, the average voltage across an inductor is zero, i.e., = 0 Using the derived voltage Equations (1) and (2), we can extract the volt-second balance equations as where α is the duty ratio. Using Equations (1)-(3), the following results are obtained: Using (4) voltage gain K for the proposed converter, the results are:

Mismatch Operating Modes of the Inductors of the proposed D VL Converter
The converter enters the DCM mode of operation when the inductor current goes to zero at any time of interval. Consider two cases of operation: 2.2.1. Case I: Inductor L1 operating in DCM and L2 into CCM Inductor L1 is sufficiently high so that ripple is neglected. A low value of inductance of L2 makes the ripple high in inductor current L2, and the current goes to zero before the time interval TS. The waveform of the considered operation is shown in Figure 5a.

Mode 1(t0 < t < t1):
The power switch is ON for this duration. Inductor L1 starts to magnetize from zero and reaches the maximum at the end at time DTS. This mode is the same as CCM Mode I. The governing relations in this mode is given by Equation (1) Mode 2(t1 < t < t2): The power switch is OFF in this time interval. Inductor L1 starts to demagnetize, and the current falls to null at the end of the interval α1Ts. The governing relations in this interval are given by (2).

Mode 3(t2 < t < TS):
The power switch is OFF. In this interval, the Inductor L1 current is zero. The voltage across Inductor L1 is zero. The equivalent circuit diagram is shown in Figure 6. The average voltage across an inductor is zero, i.e., u dt = 0 in equilibrium. Therefore, Using Equations (4) and (6), the voltage gain can be derived as Additionally, the value of α1 can be calculated as below: From (7), (8), and (9), the resulting quadratic equation has roots that give a voltage gain relation in the DCM mode of operation.
where β = 2L RT ⁄ is defined as a normalized inductor time constant. The positive solution gives the required solution, i.e.,

Boundary Condition Mode:
In Mode 2, the inductor current of L1 becomes zero at the end of αTS. This mode is termed a boundary condition mode (BCM). In this mode, the voltage gain of CCM mode and DCM mode are equal, i.e., The following relation is yielded from (12): The derived β is defined as the normalized boundary inductor time constant for Inductor L1. If β > β , the converter operates in CCM mode; otherwise, the converter operates in DCM mode, as shown in Figure 8a.

Case II: Inductor L2 operating in DCM and L1 into CCM
Inductor L2 is sufficiently high so that ripple is neglected. A low value of inductance of L1 makes ripple high in inductor current L1, and the current goes to zero before the time interval TS. The waveform of the considered operation is shown in Figure 5b.

Mode 1(t0 < t < t1):
The power switch is ON for this duration. Inductor L1 starts to magnetize from zero value and reach the maximum at the end at time DTS. This mode is the same as CCM Mode I. The governing relations in this mode are given by Equation (1): The power switch is OFF in this time interval. Inductor L2 starts to demagnetize, and the current falls to zero at the end of the interval α1Ts. The governing relations in this interval are given by Equation (2)

Mode 3(t2 < t < TS):
The power switch is OFF. In this interval, the Inductor L2 current is zero. The voltage across Inductor L2 is zero. The equivalent circuit diagram is shown in Figure 7: The average voltage across an inductor is zero, i.e., u dt = 0 in equilibrium. Therefore, Using Equations (4) and (14), the voltage gain can be derived as Additionally, the value of α1 can be calculated as below: From (7), (8), and (9), the resulting quadratic equation has roots that give a voltage gain relation in the DCM mode of operation.
where β = 2L RT ⁄ is defined as a normalized inductor time constant. The positive solution gives the required solution, i.e.,

Boundary Condition Mode:
In Mode 2, the inductor current of L2 becomes zero at the end of αTS. This mode is termed a boundary condition mode (BCM). In this mode, the voltage gains of the CCM mode and DCM mode are equal, i.e., The following relation is yielded from (20): The derived β is defined as the normalized boundary inductor time constant for Inductor L2. If β > β , the converter operates in the CCM mode; otherwise, the converter operates in the DCM mode, as shown in Figure 8b.

Effect of ESR of Inductor on Voltage Gain
Parasitic resistance ESR r is considered. Inductor L in Figure 2 is replaced by this arrangement, as shown in Figure 9. The voltage across Inductor L can be determined in both modes as follows: Switch-OFF mode⇒ u = u + u − u − i r u = u + u − u − i r The average value of voltage across the inductor is zero. Therefore, the following expressions are derived: Therefore, the effect of ESR on voltage gain can be calculated using (24): If r = r = r , then The effect of ESR of inductors on voltage is shown in Figure 10.

Current Stress of Components
If the converter is assumed loss-free, then where 〈i 〉 is the average current of any element of the proposed converter. According to the modes of operation of the proposed converter, i , i are the capacitor currents when S is turned ON and i , i are the capacitor currents when S is turned OFF. The current expressions are shown in (28).
Applying current-second balance on capacitor C1 and C0: Using Equations (28)-(30), the average inductor currents 〈i 〉 and 〈i 〉 can be drawn out as Likewise, applying current-second balance on capacitor C2 and C3, the average current through power diodes (D0 to D4) and power Switch (S) can be obtained as

Design of Circuit Components
Inductors are designed based on current ripple, and capacitors are designed based on voltage ripple.
(A) Inductor Design: Using Equation (1), the value of inductors L1 and L2 can be extracted as follows: where ∆i and ∆i are the ripples in inductor currents L1 and L2, and fs is the switching frequency.
(B) Capacitor Design: The capacitor value depends upon its charging current, the voltage ripple ∆u across it, duty ratio, and switching frequency f .
Using Equation (7), we can obtain the value of C0 and C1 as follows: Likewise, the rest capacitor value can be drawn out as where ∆u is the voltage ripple in capacitor voltage.
(C) Selection of Diodes and Switch: The voltage across power diodes (D0 to D4) and the power Switch (S) are as follows: where Ts is the switching period.

Power Loss Calculation in the proposed Dual VL Converter
The equivalent circuit, including parasitic resistors, is also considered to analyze the proposed converter circuit. In a non-ideal equivalent circuit, all components are replaced with their parasitic resistances, as shown in Figure 11, where rS is the switch on-resistance, rD is the diode on-resistance, and uF is the diode's threshold voltage. The ESR of the inductor is taken as rL. The ESR of the capacitor is taken as rC. Assuming that the inductor current has no ripple. The power output is given as (a) Switch Losses The root mean square value of the current passing through the switch is i , and P and P are the switching loss and conduction loss of switch S.
where the rising and falling times of S are given by t and t , respectively. Total loss by the switch is calculated as

(b) Power losses in diodes
The root mean square current of the diode is notified by i . The power loss due to ON resistance of diodes is P and P is the loss due to forward voltage drop u of the diodes. Diode loss is calculated as Total diode loss can be drawn out as follows:

c) Power loss in inductors due to ESRs
The root mean square current of the diode is notified by i . The power loss due to ESRs and the r of the inductor is P .
Total loss due to ESR of inductors can be obtained as

) Power losses in capacitors
The root mean square current of the diode is denoted by i . The power loss due to the ESRs and r of the inductor is P .
For all capacitors, the loss can be calculated as The expression for the efficiency of the proposed converter circuit can be obtained from Equations (43), (46), (48) and (50) as η = P P + P + P + P + P (51)

Comparative Study
A detailed analysis of the proposed converter with similar non-isolated structures is carried out in this section. The comparison is based on voltage gain, voltage stress, and the number of components in the converters, as listed in Table 1. Voltage gain is an important index to determine the performance of the converter. The voltage gain curve is shown in Figure 12. The proposed converter can achieve the highest voltage gain till duty ratio (α) of 0.6 after α > 0.6; topologies two and eight are greater than the proposed converter. Topology nine uses coupled inductors to boost the voltage gain up to eight times (not shown in Figures 12 and 13) because of the isolated category of DC-DC converters but has the maximum number of components compared to other converters listed in Table 1.
The component counts of the proposed converter are less than topologies 1, 2, 5, and 8. Another important criterion is the voltage stress on the semiconductor devices. For this, a plot of normalized switch voltage stresses against the voltage gain of the proposed converter is shown in Figure 13. The proposed converter has the least voltage stress on the switch, which is less than the output voltage. Topologies two and eight have higher voltage gain, but they have greater voltage stress than the proposed converter. Moreover, topologies two and eight both have a greater number of components than the proposed converter. Topologies 2, 3, 6, and 8 have voltage stress equal to the output voltage. The high voltage stress on the devices increases the chance of the failure of the devices, so devices with a higher rating will be required. The components with the higher rating will have increased costs and will deteriorate the efficiency of the converter due to high power loss. Topology 1 and topology 9 have a non-common ground structure, while other topologies, including the proposed converter, have a common ground structure.
Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes The proposed topology can achieve higher gain with low stress on the components. The components with lower ratings will have low ON resistance, which will improve the overall efficiency of the converter. Moreover, the converter utilizes a single switch, so control is easy. The interleaved converter, presented in topology 9, utilizes two switches with a 180-degree phase difference. Further, the use of the coupled inductor makes the circuit complex. The proposed converter also provides a common ground structure between input and output, which mitigates electromagnetic interference problems. The volume of components is mainly decided by the magnetic components in the converter; the proposed converter uses only two inductors such as TQBC, so volume is low as compared to topologies 2, 3, 5, and 8 which utilizes three inductors. The use of more inductors makes the circuit bulkier.   Table 1.

Simulation Results at α = 0.4
In this section, simulation results of the proposed converter are discussed. The parameter values taken for simulation are presented in Table 2. The simulation is carried out at an input voltage of 36 volts at a frequency of 50 kHz. Equivalent series resistance (ESR) of inductors and capacitors is also considered for the simulation on Piecewise Linear Electrical Circuit Simulation (PLECS) software. The duty cycle is maintained at 0.4. Figure 14 shows the output voltage results of the proposed converter. The output voltage is obtained is 256 V, which is more than seven times the input voltage. The deviation obtained is due to a parasitic resistance drop in the proposed converter. The average current of inductors of L1 and L2 are 3.7 Ampere and 1.4 Ampere, as shown in Figure 15. In the same figure, the ripple observed in the inductor current is very low, with a fixed duty ratio of 0.4. When the switch is OFF, it blocks the positive voltage equal to 159 V which is 62% of the Vo in Figure 16. In the same figure, the average capacitor voltage VC3 is 96 V. Figure 17  Proposed Converter presents the capacitor voltages of C1 and C2, equal to 36 V and 96 V, respectively. The simulation results obtained by using parameters mentioned in Table 2 are in agreement with the theoretical results. It is to be mentioned that the converter is operated in the CCM mode.

Experimental Verification at α = 0.4
To verify the operating principles and boost the capability of the proposed converter, a hardware prototype of 200 W is developed and tested under laboratory conditions. The hardware prototype is shown in Figure 18a and the hardware setup in Figure 18b. The experimental waveforms are presented and demonstrated in this section. The hardware parameters are the same as the simulation parameters given in Table 3. The DC input supply is taken to be 10 V for the CCM mode operation of the proposed hardware prototype. The experimental gate pulse for the power MOSFET (SPW52N50C3) is 40 per cent. Figure 19 captures the input (Vin) and output voltages (Vo) of the experimental prototype. The output voltage (VO) obtained is 70 volts, where Vgs is the gate drive signal. When the MOSFET is ON, inductors L1 and L2 magnetize and the current through the inductors (IL1 and IL2) increases linearly. IL1 increases from 0.15 Ampere to a peak value of 0.7 Ampere, whereas IL2 increases from 1.0 Ampere to a peak value of 1.2 Ampere. The average current of inductors of L1 and L2 are 1.04 Ampere and 0.4 Ampere, as shown in Figure 20. During the OFF state, the voltage across the switch is 40 V, which is less than VO, as shown in Figure 21. The capacitor voltages VC1, VC2, and VC3 are 10 V, 26 V, and 26 V, respectively, captured in Figures 20 and 21 with very low voltage ripple.    The closed-loop performance of the converter is illustrated in Figures 22 and 23. The output voltage Vo is regulated at 45 V when the input voltage is varied from 10 volts to 14 V to 8 V. Similarly, when the load resistance is changed the output voltage should be held constant by the PI controller. As the load is changed from 300 Ω to 800 Ω, the output voltage is held constant at the set reference value of 60 V, as shown in Figure 24. It shows that the PI controller is working satisfactorily. The values of proportional constant (Kp) and integral constant (Ki) for the PI controller are set to be 0.05 and 0.01 respectively. TMS320F28335 controller is used for implementation of closed-loop control.
The efficiency at different power levels is shown in Figure 24. It can be seen from the plot that for a constant output power as the voltage increased from 10 V to 20 V, the efficiency of the converter increased. This is because to achieve the same power level, the current decreases with the increase in output voltage. As a result, the conduction losses in the converter decreases and efficiency increases. The percentage losses in the components as calculated from the PLECS software by incorporating the real loss values from the datasheet of different component. 47% of the total loss, occurs in diodes, as shown in Figure 25. The switch losses are around 19%. Losses in the inductors and capacitors are found to be 20% and 14% respectively. The diode losses can be reduced by the selection of diodes with a low value of parasitic resistances. The capacitor ESR depends on the frequency and hence capacitor losses increase with an increase in frequency.

Discussion and Conclusions
The proposed converter can achieve a voltage gain of more than 10 times at a duty ratio of 0.6. The topology has a common ground structure with a single switch, so control is very easy with a reduced number of components. Due to parasitic resistances of components, the voltage gain of the proposed converter is severely affected at higher duty ratios. The total number of the elements in the proposed converter is less than the other converters for the same value of voltage gain. The maximum efficiency obtained was 94% at an input voltage of 20 V. The converter performance is found to be good in a closedloop situation also with the PI controller. The PI controller is tuned to maintain a constant output voltage when the load or the input voltage changes. The converter is suitable for renewable energy applications for medium power applications due to the presence of continuous input current and common ground between the input and the output sides.