Improved Predictive Control for an Asymmetric Multilevel Converter for Photovoltaic Energy

This article proposes a 27-level asymmetric cascade H-bridge multilevel topology for photovoltaic applications, which considers a predictive control strategy that allows minimization of the commutations of the converter. This proposal ensures a highly sinusoidal and stable photovoltaic injection when there are solar irradiance disturbances, generating a low distortion in the current waveform and low switching losses. To validate the performance of the control and the proposed topology, the dynamic model of the alternating current (AC) and direct current (DC) side system is first obtained, which is checked by computational simulations. Subsequently, the implementation of a master–slave control is carried out, focused on the control of DC voltage and AC current. The proposal is simulated, and the total harmonic distortion (THD) is obtained in the voltage and current waveforms. Undesired commutations, typical of the predictive control, are eliminated in the AC voltage waveform, and a proper DC voltage tracking is achieved for the high-power cell. In order to demonstrate the performance of the proposed control strategy, a low-power proof-of-concept prototype is implemented, in which the energy is injected to the grid, under the event of solar irradiance disturbances (with DC control).Then, the undesired switching in the main cell is eliminated, generating THDs in the voltage and current signal of 7.76% and 2.65%, respectively.


Introduction
In the global context at the end of 2019, global generation capacity from renewable sources increased by 176 GW and reached 2537 GW worldwide, which represents an annual growth of 7.4%, the average of seven consecutive years [1].
Moreover, it is expected that wind and solar power will account for 96% of the total power supply of renewable energy sources by 2050 [2]. This opens up great opportunities for power electronics, which have to efficiently integrate renewable energy into the different electricity networks and also to guarantee the quality and stability of them, especially in energies as vulnerable to disturbances as photovoltaic technology, the operation of which may require monitoring [3] and adaptive control to deal with the radiation intermittency.
Power electronics is a multidisciplinary area that plays a fundamental and mandatory role in the incorporation of photovoltaic energy technology into electrical systems. In this scenario, the neutral point clamped (NPC) converters, cascade H-bridge (CHB), and modular multilevel converters (MMC) stand out for their wide range of applications at the industry level [4][5][6][7]; they are very attractive due to the high quality of their output signals, as well as their low number of components and high voltage under the ratio 9:3:1. It is possible to find in the literature other asymmetry proportions for this converter [29,30]; however, it has been shown that the used relation minimizes the redundant states [8,9] and, therefore, generates less harmonic content in the resulting waveforms of the converter. Due to the asymmetric distribution of the voltages, HPC handles, at most, one of the total power of the converter, while the rest is distributed between the MPC and LPC modules. These last two cells have to ensure the proportion in terms of the DC voltage of the HPC cell despite the changes in solar irradiance upon the photovoltaic panels. It is important to mention that the voltage ratio for the MPC and the LPC must be ensured by external control loops and additional hardware (DC/DC converters), as deeply explained in [31,32]. It is important to consider that non-compliance with asymmetry implies a harmonic distortion in the output signal of the converter, which means losses attributed to the generation of harmonics in the AC current.

Converter Modulation
To understand the modulation of the converter, it is necessary to identify its valid states. For a three-cell topology of a CHB converter, there are 64 valid states, and 37 of these are redundant 'zero' states. It is not possible to use these redundant states for a purpose other than the equitable alternation of losses between the semiconductors of the converter cells, since these do not influence the output signal of the converter. Thus, only two matrices of 27 valid states will be used, where the first matrix will consider the zero states '11' and the second matrix will consider the zero states '00'. In Section 2.5, this topic will be addressed in greater detail, which has as its main objective the equitable distribution of the zero states in each cell in order to distribute the conduction losses of the semiconductors of the three equitable cells. The generalized valid states for this converter are shown in Table 1, where the marked framed states are those that present undesired commutation generated by the standard predictive control. This issue is widely developed in later sections.

AC Link Dynamic Model
To formalize the behavior of the converter, it is necessary to obtain the dynamic model of the system. For this, the following equations are defined as follows: where V dc is the virtual DC voltage of the converter that is composed by V 9 (DC voltage of the HPC), V 3 = V 9 3 (DC voltage of the MPC), and V 1 = V 9 9 (DC voltage of the LPC). The converter voltage can be expressed as where v c represents the AC voltage of the converter and s c is the switching function that represents the 27 valid non-redundant states of the converter. Similarly, v c can be represented by the sum of the AC signals of each cell.
where v HPC , v MPC , and v LPC correspond to the AC voltage of the HPC, MPC, and LPC, respectively. The following dynamic equation of the converter is obtained with the help of the simplified circuit of Figure 2.
Once the dynamic model of the converter is obtained, it is necessary to find its discrete equivalent [33]. This is required to program the predictive algorithm and to be able to evaluate each valid state of the converter discretely. For this, a first-order Euler approximation is applied in the derivative of the dynamic Equation (4).
where T s corresponds to sampling time.
Reordering the Equation (5), predicted current i c (k + 1) can be obtained.
Finally, Equation (6) predicts the future state of the converter current.

DC Link Dynamic Model
Additionally, it is necessary to formalize the DC link behavior of the HPC in order to apply the master control loop. For this, a power balance between the converter and the HPC capacitor is considered.
Equation (7) represents the power balance between the AC side of the converter and the DC side capacitor, where V pv represents the capacitor voltage, which is also represented by v 9 . Applying the Laplace transform to Equation (7) and considering the term −V pv i pv as a disturbance: where s represents the Laplace term. From Equation (8), the system transfer function is obtained, which is represented by Equation (9).
From the G(s) function, the calculation of parameters of the corresponding PI control loop was performed. Using classic control tools, such as Root Locus, a settling time of 2 s, with no overshoot in the step response, was established; it resulted in kp = 0.00040292 and ki = 0.0001477.

Predictive Algorithm
The diagram in Figure 3 shows each of the steps to implementing the predictive control. First, a measurement stage is observed, in which the converter current i c (k) and the grid voltage v s (k) are obtained. Then, in the second stage, the optimal switching state s c (k) that was obtained in the previous prediction cycle is applied. After this, the equation evaluation process (6) is initialized. This process is repeated 27 times, which corresponds to the number of valid states considered in the converter. Once i c (k + 1) is obtained, the cost function g j is calculated, whose value depends on the absolute difference between i re f c (k + 1) and i c (k + 1). The value of this cost function g j is then optimized, considering the valid state that generates its minimum value. Finally, the optimal valid state is stored to be applied in the next control cycle.

Stability and Robustness Assessment
To demonstrate the robustness of the proposed predictive control, the simulation is carried out, considering the AMC converter and the control strategy under study (see Figure 3). Within the simulation, changes were made in the system parameters: The inductance L c and resistance R c of the converter were varied in a certain range in order to analyze the behavior of the control. The parameters considered in the simulation are shown in Table 2. On the other hand, the Figure 4a,b represents the response of the closed-loop system to the variation of inductance and resistance of the converter, respectively. For both figures, the left and right axes represent the converter current and the total harmonic distortion (THD) of the voltage, respectively. It is also possible to observe a segmented line, which represents the current reference of the converter.   Initially, the nominal values of resistance and inductance of the converter are 5 Ω and 20 mH, respectively. It is observed that when applying an inductive change (see Figure 4a), the system does not present big variations in the current signal of the converter (compared to its reference). Indeed, the current is kept constant with the change of this parameter, and the THD remains low. However, if the value of the inductance continues to increase, a significant distortion in the dynamics of the current of the converter is naturally expected.
In Figure 4b, it can be seen that when there is a resistive change, the precision of the predictive control is reduced. Indeed, when increasing or decreasing the resistive load, the control gradually moves away from its reference. However, within a range of ±25% of the load, the control loop still can achieve an acceptable behavior because the converter voltage keeps its sinusoidal shape.
On the other hand, in the predictive control, it is not possible to carry out a stability analysis using conventional methods. However, there are studies that establish some methods to guarantee asymptotic stability in a closed loop. Those methods are "Continuity of system and cost", "Uniform weak controllability", and "Properties of constraint set", among others [34].

Mitigation of Undesired Commutations
Following the steps in the diagram of Figure 3, a correct control of the converter current was achieved. Nevertheless, several commutations were observed in the changes of states of the cells. According to the nature of the converter, it was determined that such commutations have a negative effect, particularly on the HPC (Figure 5a), since it manipulates the highest amount of power (maximum 70%), whereby additional switching losses would be generated in terms of the expected signal (see Figure 5b). Although the same effect also occurs in the MPC and LPC, they handle much lower power than the HPC, so they are not considered in the present study. The effect produced by additional commutations is normal in predictive loops, especially if it does not have a penalization element of commutations in its cost function. Given the latter and to overcome this problem for the HPC, it is proposed to establish a matrix of penalties (based on a method addressed in article [35]) that limits the additional commutations produced in the changes of state of the HPC. Therefore, a new term is applied in the cost function, which serves as a restriction that acts to eliminate these undesired commutations. This term is a matrix whose values are based on the present state k and the future state k + 1. After applying this matrix of restrictions in the cost function of the predictive control, it is expected to obtain a signal similar to Figure 5b.  To perform the constraint matrix, it is necessary to consider the valid states of the Table 1. There, it can be seen that the framed states are those that generate the commutations in the HPC. Considering the latter, the constraint matrix described in Table 3 is generated, which is applied as a new component in the cost function M(k)(k + 1).  Table 3 is obtained from Table 1 and consists of 27 rows and 27 columns, whose rows represent the current valid state s c (k) and whose columns represent the future valid state s c (k + 1). Table 3 shows the commutation regions based on the present and future states previously mentioned, where '1' represents commutation between the states and '0' the non-commutation between them. The logic of Table 3 is to position itself in the current state and determine if the future state commutates the HPC. It is expected that, at the time that an undesired commutation happens, the cost function will increase its value, preventing the application of the respective future state unless there is really a change in the HPC and the converter enters within the non-commutation region. This method ensures the reduction of commutation efficiently in the HPC. Considering the above, the new cost function is as follows: where g j corresponds to the cost function and M(k)(k + 1) is the constraint matrix shown in Table 3, k is the present time, k + 1 is the state to be evaluated, and λ corresponds to the weighting factor that is calculated based on the maximum permissible error in the cost function to be obtained.

Zero State Equalization
In order to get the most out of the proposed topology, it is necessary to strategically use the zero states of the converter in order to distribute the load equally in the semiconductors and avoid their partial use. A basic scheme of the H-bridge cell is shown in Figure 6, where the zero state '11' is observed, which implies that both s 11 and s 12 are closed. This indicates that the cell does not deliver voltage. However, it allows the current to pass through an eventual load at terminals T 1 and T 2 . It is worth mentioning that the switches s * 11 and s * 12 have a phase shift of 180 • with respect to s 11 and s 12 . If only the zero state '11' is used, the semiconductors s 11 and s 12 would suffer a greater loading as compared to the semiconductors s * 11 and s * 12 , which would produce an imbalance in their lifetimes. It is important to clarify that when considering two zero states per cell, and not only one, there is a total of 4 3 valid states in the topology. However, the existing redundant states are only zero states, which do not contribute in the amplitude of the signal at the output of the converter. The proposed technique will take advantage of all the zero states in order to distribute them, i.e., each of the switches is used equally when a zero state occurs. Subsequently, a suitable way to distribute the semiconductor load equally is to alternate two state tables (created from the table with 64 valid states) in each wave cycle. In this way, this guarantees equal usage and heat distribution throughout all four switches of each cell.

Control Strategy
The diagram in Figure 7 shows the control proposal, which considers a master-slave approach. The master-loop corresponds to the DC control of the HPC, while the slave-loop corresponds to the current control of the AC side of the converter. The master-block is implemented through a proportional-integrative loop (PI), while the slave-block is controlled through a predictive loop. ( 1) q is set to zero. This block aims to provide the set of valid states for the future state of the converter s c (k + 1). Subsequently, an inverse Park-transform block is observed, which transforms the references from the dq plane to the abc plane, giving the future current reference i re f c (k + 1). This signal reaches the predictive control block (described in Figure 3) in the same way as the converter current and the grid voltage.
On the other hand, a PI block is responsible for controlling the voltage in the HPC of the converter, which is fed with the difference between the signals (v re f 9 ) 2 and v 2 9 , taking into account the transfer function described in Equation (9). The output of this PI block provides the direct current reference to maintain the voltage of the HPC in the reference (v re f 9 ) 2 .

Simulation Results
This section shows and discusses the main waveforms obtained with the methods presented in this proposal. This work was simulated in the PSIM and MATLAB softwares; solar irradiance disturbances in the photovoltaic array connected to the HPC were considered. The considered parameters are shown in Table 2.

Transient State Analysis
In this section, a dynamic analysis of the signals obtained by simulation is developed with the purpose of demonstrating the proper tracking of the current reference through the master-slave approach.
To evaluate the performance of the control strategy, an initial solar irradiance value of 1000 W/m 2 is imposed for the photovoltaic array of the HPC. Starting at 0.5 s, the solar irradiance is reduced to 500 W/m 2 , emulating an eventual loss of generation in the photovoltaic panels due to the shading effect (see Figure 8a). Once this change in the photovoltaic generation is imposed, it can be seen in Figure 8b that the converter current at t < 0.5 s is in a steady state at the value of 3 A. At t > 0.5 s, the dynamic change in the photovoltaic generation takes place, and there is a drop in the current signal i c and the reference current i re f d (generated by the master-loop). The latter gradually descends to a final value of 1.5 A. This reduction occurs because the photovoltaic generation decreases and, therefore, so does the current injected into the grid. It is observed that, given the dynamic change, the current is adjusted to the new generation condition in order to ensure that the capacitor of the HPC is kept in the reference v re f 9 (see Figure 8c). Although the dynamics of the predictive control in open loop are quite fast (in the order of ms), in a master-slave scheme, this dynamic is governed by the slower system, which, in this case, corresponds to the voltage control of the HPC, which is carried out by a proportional-integrative control (PI) with a settlement time of 2 ms and no overshoot. For this reason, the current i c takes 2 s to reach its reference value.
For both the DC current and the voltage, there is a higher ripple at t < 0.5 s compared to t > 0.5 s, which is due to the fact that this loop corresponds to a PI (linear control) block, which is designed for a specific operating point. Therefore, when the operating conditions change (solar irradiance disturbance), a decrease in the ripple in the response of both variables can be seen. This effect is also attributed to the fact that the new generation conditions involve manipulating a smaller amount of current.
On the other hand, Figure 8d shows the AC voltage of the HPC, which has a switched amplitude between 0 and ±39 V. At t > 0.5 s, it is observed that the voltage of this cell takes about 2 s to stabilize. Figure 8e shows the instantaneous power injected into the grid, where it can be seen that, at t < 0.5 s, this has a steady state value of 80 W. However, that value drops to 40 W due to the decrease in the generation of the photovoltaic panels.

Steady State Analysis
In this section, the results obtained in simulation are discussed; mainly, it is intended to confirm the correct response of the system in the steady state and also to demonstrate the effective elimination of undesired commutations, which are included in the objectives of this work.
In Figure 9a, the signal obtained in the HPC is shown by applying the constraint matrix M(k)(k + 1), while in Figure 9b, the signal obtained in the HPC is shown without applying the constraint matrix. It is worth mentioning that, for each wave cycle, the HPC should commutate only four times and not 16 times, as shown in Figure 9b. It is observed that with the restriction of commutations in the cost function, the commutations produced in the HPC state changes are completely eliminated. Therefore, and considering the previous figures, the commutations in the HPC are eliminated to 25% with the help of the constraint matrix in the cost function. The MPC and LPC in Figure 9c,d do not show changes in the event of disturbances because, for simulation purposes, the cells are fed with external DC sources in order to follow the 9:3:1 ratio. It can be seen that there are additional commutations in the changes of state of the MPC and LPC. The latter is due to the nature of the predictive control and the absence of restrictions in the cost function to mitigate them. In fact, it is established that the commutations of the smaller cells generate a negligible impact (with respect to the commutations in the HPC) on the output signal of the converter. Figure 9e shows the converter voltage signal, where the stepped shape is observed due to the nature of the asymmetric multilevel topology 9:3:1, obtaining a maximum of 27 levels. Figure 9f shows the converter's current signal, where THD is obtained in the current and voltage signals of 1.53% and 7.07%, respectively. These values are positioned within the standards recommended by the Institute of Electrical and Electronics Engineers (IEEE) [36]. Finally, in Figure 9g, the commutation of the status tables is shown, where an equitable distribution of the zero states is ensured, which prevents unequal loading of the semiconductors of the converter. Figures 10a,b shows the harmonic spectrum of the voltage and current of the converter using predictive control, where a logarithmic scale is used on the y-axis, in order to show more clearly all the components of the spectrum. On the other hand, the x-axis represents the harmonics of the signal, which is normalized with regard to the fundamental frequency (50 Hz). Therefore, the first harmonic corresponds to the fundamental frequency; the other harmonics (from 2 to 50) are multiples of the fundamental. It is important to mention that the harmonic voltage spectrum concentrates its greatest amplitude on the fundamental frequency. The amplitude of the rest of the harmonic components is very far from the fundamental amplitude, and can be easily eliminated with a passive filter. Figure 9a,b demonstrates the low harmonic component of this converter compared to other topologies, which is one of the main features of the asymmetric multilevel converter presented in this work.

Experimental Implementation
The general connection scheme is the same as that presented in Figure 1, where the asymmetric multilevel converter (AMC) is connected to the power grid in order to inject the power generated in the PV modules. The same values of the simulation are considered for the parameters in the proof-of-concept prototype.

Commutation Elimination in the HPC
In this subsection, an experimental comparison is made between the application and the absence of the restriction table within the cost function of the predictive control applied to the AMC. The latter is to check if undesired commutations are actually being eliminated in the HPC, and to experimentally validate the results obtained in the simulation. Thus, initially, the predictive control is implemented in the converter without the incorporation of the M matrix (see Figure 11a). As a result, a voltage signal is obtained in the HPC with undesired commutations in the state changes of the cell. This result normally describes the typical behavior of a predictive control strategy where there is a change in the selection of valid states mainly reflected in the changes in the state of the HPC. On the other hand, the matrix of switching restrictions is incorporated in order to validate the results obtained in the simulation. In Figure 11b, the results obtained by applying the M restriction matrix in the cost function of the predictive control are shown, as is the total mitigation of undesired commutations in the changes of state of the HPC. Therefore, the results obtained in the simulation can be validated.

Discrete Master Control
In order to introduce a linear controller, it is very important to establish the expected dynamic behavior. Figure 12 represents the master control scheme based on the power balance model shown in Equation (8), which was described in the previous sections. It has to be considered that the implementation of the control algorithm is discrete. Therefore, the control loop must be expressed in the Z plane, as shown in Figure 12. The same parameters of the simulation are used for the experimental tests.

Result Analysis
In this section, the tests and analyses of the master-slave control are carried out, where disturbances are applied in the power generation of the photovoltaic panels connected to the HPC of the converter.
For these tests, the parameters of Table 2 are considered. In Figure 13a, two signals can be seen; v 9 (channel 1) corresponds to the DC control of the HPC, which was previously tuned, establishing a settling time of 2 s without overshoot. It is possible to observe in Figure 13a that the dynamic response complies with the times established in the tuning of the controller, as previously established. In addition, the signal i c (channel 2) represents the behavior of the converter current, where it is observed that prior to the disturbance in the solar irradiance of the photovoltaic panels, the injection current to the grid is 1.7 A. After the disturbance, the current decreases to 0.8 A, since the power generation decreases under this scenario. The current is regulated (because of the master control), such that the voltage of the HPC is kept at the established reference of 39 V. It is possible to confirm that both the settling time and the overshoot in the DC voltage of the HPC behave according to the design parameters.
Additionally, two graphs are shown in Figure 13b,c. The first image represents the behavior of the currents i c , i s , and i L in the steady state prior to the solar irradiance disturbance. The second image represents the behavior of the same currents in the steady state after the solar irradiance disturbance. In the latter, it can be seen that the quality of the current signal injected by the converter in both operating conditions is highly sinusoidal with low THD. Current signals appear with evident noise on the experimental prototype. This is due to several factors, such as sensing errors, electromagnetic noise, losses due to length of wiring, parasitic capacitances, voltage drop in the semiconductors, and passive elements, among others. In particular, in this implementation, losses are attributed to the magnetic field generated by the inductor of the converter, some inevitable long tracks at the gate of the MOSFETs (metal oxide semiconductor field-effect transistor) of the H-bridges, the wiring between the digital signal processing (DSP) and the field-programmable gate array (FPGA), and the calibration of the sensors. Then, the harmonic spectra obtained for the current and voltage signals of the experimental setup in the steady state are shown. The harmonic spectrum of the voltage signal of the AMC prototype is shown in Figure 14a, and indicates a similar distribution to the one obtained in the simulation, where there is the highest amplitude concentrated in the fundamental frequency. From the second harmonic onwards, the lower-order components of high frequencies (up to 2.5 kHz) are distributed, where the second harmonic has an amplitude of the order of mV.
In Figure 14b, the harmonic distribution of the converter's current signal is shown, which is a consequence of the harmonic voltage distribution and subsequent attenuation due to the inductive component of the filter L c . To obtain the value of the inductor capable of generating a THD lower than 2%, the Equation (11) is considered, which was obtained following the procedure developed in [37].
where f c refers to the maximum switching frequency and δ to the maximum permissible current error. In order to obtain the maximum switching frequency, an analysis is performed in the LPC because it switches at a higher frequency than the rest of the cells of the topology. In this analysis, a total of 50 commutations per cycle were obtained, of which 10 commutations were attributed for each edge due to the predictive control action, obtaining a total of commutations (T c ) of: where s cycle c is the total number of commutations per cycle of the LPC and s pred c corresponds to the commutations, in the LPC, provided by the nature of the predictive control. Considering that the voltages used in the low-power prototype are 56.4 V for the converter and 20 V for the AC source, and establishing an allowable error of 0.02 A for the converter current, it can be said that: For practical reasons, there were only off-the-shelf inductors of 20 mH for the prototype implementation. It should be mentioned that in the prototype, there are conditions that increase the value of THD in the current, despite the calculation made in the simulated tests, which is reflected in the value of THD of the obtained current from the prototype and shown in Table 4. The quality of the current obtained in the simulation is compared (Figure 10b) with the current signal obtained in the experimental test. It is observed that the harmonic distortion of the prototype is higher than the one obtained from the simulation, which is absolutely logical, considering the already explained causes in the analysis from Figure 13. Thus, the harmonic distortion of the current and voltage signals of the converter is analyzed, obtaining a THD of 2.65% and 7.76%, respectively. These magnitudes meet the quality standards recommended by the IEEE [36].
Additionally, in Table 4, a comparison of the harmonic distortion of the signals i c and v c obtained in simulation and in the prototype is made.

Discussion
In this section, a comparison is made between the proposal and other works that address asymmetric multilevel topologies with different asymmetries on their DC side.
There is a great variety of works where asymmetric multilevel topologies are addressed, whose applications are mainly photovoltaic energy injection. These works mainly deal with variations in asymmetric topologies (asymmetries), commutation techniques, and control strategies. For comparison purposes, the THD values for both voltage and current of each surveyed work will mainly be taken in order to position this proposal as a feasible alternative for photovoltaic applications.
The survey revealed several commutation techniques applied to asymmetric multilevel topologies (see Table 5), in which it is observed that the POD-PWM and POD-PWM techniques present a significant harmonic distortion in the voltage signal of the converter [38], obtaining 14.83% and 15.2%, respectively. Furthermore, it is found that the most promising modulation techniques are Space Vector Modulation, Level-Shifted Pulse-Width Modulation, and Staircase Modulation [39][40][41] with voltage THDs of 3.71%, 3.84%, and 3.85%, respectively. These solutions were presented in an open loop, considering only the performance of the modulation in their respective topologies. Although the work presented in this article does not have a modulation technique because a predictive control strategy is applied, the obtained current and voltage THDs of the proposed converter are 1.53% and 7.07%, respectively. These values are acceptable and place the proposal as a feasible solution, bearing in mind that this proposed scheme also considers a master-slave closed-loop control (PI-Predictive), and there are other factors that contribute various harmonic components that were not considered in the previously named articles.
Finally, two articles [10,42] that validate their studies through an experimental prototype are presented. The article [42] presents a seven-level cascade asymmetric multilevel converter, which uses an LS-PWM modulation technique and closed-loop control with a PI controller, and also has maximum power point tracker (MPPT) functionality for its two independent DC sources. The results of this work are validated through an experimental prototype, obtaining a THD of 2.2% and 13.3% for the current and voltage signals, respectively. The voltage THD is higher than the THD obtained for this work. However, it is observed that the current THD is lower than the THD of the proposed topology. This can be attributed to the use of a second inductor on the negative terminal of the AC source, which acts as a low-pass filter. The article [10] presents an asymmetric 16:4:1 multilevel topology, which is validated through an experimental prototype. Although only the open-loop performance of the SVM technique combined with a staircase technique is evaluated, an interesting result is observed in the harmonic content of the voltage, which is lower than 4%. However, when contrasted with a closed-loop control for some photovoltaic applications, this THD would undoubtedly increase, approaching the value obtained in the proposal of this paper.
The latter makes clear that the proposed converter has interesting results compared to different asymmetries, delivering signals with a fairly low THD.

Conclusions
This paper presents a study about a predictive control strategy for a 27-level asymmetric multilevel converter for PV solar applications, whose main contribution is to locate the proposed system as a good alternative for photovoltaic applications. Among the features that stand out can be mentioned a highly sinusoidal signal, with low harmonic content, commutating most of the power to the fundamental frequency to reduce commutation losses and also taking advantage of the flexibility provided by photovoltaic systems to compose (through different arrangements) isolated DC inputs required by the HPC, MPC, and LPC.
The generalized model of the single-phase converter was proposed and a predictive control strategy was applied to achieve a proper current tracking. A master-slave scheme was applied in a simulation and a prototype in order to control both the DC link and the converter current. The strategy incorporates a PI outer controller as well as a predictive scheme in the inner loop, which demonstrated the correct reference tracking under solar irradiance disturbances. Indeed, its convergence was within the design parameters, showing satisfactory dynamic and stationary response. A restriction table was incorporated into the cost function in order to limit the commutations in the HPC, which was properly achieved in the prototype and simulation, where 12 commutations were eliminated from a total of 16, representing a 75% decrease of commutations in the HPC. Thus, a simple but effective strategy was implemented in order to ensure the equitable power distribution among the semiconductor devices, which is based on the alternation of the zero states of the converter. Finally, the THD of the experimental results for the current and voltage waveforms was 2.65% and 7.76%, respectively. These quantities contrasted with those obtained in the simulation, which were 1.53% and 7.07% for current and voltage, respectively. This increase in the THD is attributed to the intrinsic undesired phenomena involved in the implementation of a physical prototype.

Acknowledgments:
The authors thank the support of the CONICYT PFCHA/Doctorado Becas Chile/2019-21190255 and the ANID/FONDECYT Programme through Regular 1191028.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations are used in this manuscript: