Theoretical Analysis on the Short-Circuit Current of Inverter-Interfaced Renewable Energy Generators with Fault-Ride-Through Capability

Renewable energy generators (REGs) usually employ power electronic devices for connecting with the grid, which makes their fault characteristics completely different from those of conventional synchronous generators. In the existing studies, the simulation methods are mainly adopted to analyze fault current contribution from REG. As a result, the explanations on the fault current show diversity and cannot reach a recognized standard. The REGs’ mathematical model in relay-setting calculations is unknown. Thus, this paper theoretically analyses the fault current characteristics of inverter-interfaced REGs (IIREGs) with fault-ride-through (FRT) ability. In order to understand the fault current characteristics, the FRT control strategy for IIREGs is firstly studied. Then the characteristics of high-frequency and fundamental-frequency fault currents from IIREGs are theoretically analyzed after and during the faults. The affecting factors and duration time of different frequency fault currents are, respectively, revealed. Further, the mathematical expression of fundamental fault currents from IIREGs are derived and verified based on the experimental test bench. The results can be used in estimating the IIREGs’ fault contributions and developing the fault calculation model.


Introduction
With the worldwide concern on environment pollution and the crisis on traditional fossil energy, renewable-energy penetration in power grids is expected to grow spectacularly [1].In China, the government has launched eight 10-GW-level wind-power bases with an accumulated installed capacity of over 150 million kW and several large-scale solar energy power stations with a total installed capacity of 5 million kW during 2011-2015 [2].These wind-power bases and solar power stations are located in the Chinese northern regions and coastal areas.They are connected to the transmission grid in a concentrated mode.As a result, the share of the renewable-energy generators (REGs) is increasing in the connected regional grids [3].The REGs become indispensable in maintaining the stable and reliable operation of the grid.
In many countries, the newly devised grid code demands that the REGs must have the fault-ride-through (FRT) ability.As a result, the fault current contribution from REGs cannot be neglected.However, the fault characteristics of REGs are different from those of conventional synchronous generators (CSGs).Due to the REGs' special electricity-generating principles and the integration of power electronic converters, the analysis on the fault characteristics of REGs becomes difficult.The existing study adopts the simulation methods [4,5].The results depend on the simulation tests, so it is diversified.Thus, the universal equivalent model of REGs is unknown for fault analysis and relay setting calculations of power grids with high REG penetration.
As a result, Chinese regional power utilities generally adopt two protection solutions.One method considers the REGs as loads; thus, protection relay is not installed (or enabled).The other method considers the REGs as the CSGs; thus, the protection relays configured for both the REGs and grid sides at the outgoing lines are the same.This configuration may lead to protection malfunction at the wind-farm side of the outgoing lines [6].To solve the problems, the fault contribution of different REGs must be theoretically analyzed.
REGs are classified into two types in terms of the integration mode of power electronic converters: partial-and fully-rated converter-interfaced REGs [7,8].The former generally refers to wind turbines with doubly-fed induction generators, whereas the latter is referred to as inverter-interfaced REGs (IIREGs), including wind turbines with permanent magnet synchronous generators and photovoltaic panels and so on.This paper mainly concerns with the IIREGs' fault characteristics.
The IIREGs are connected to the grids only through a full-scale inverter, so their generating units are completely decoupled from the grid.The IIREGs' fault characteristics are affected mainly by the inverters' control mode, the inverters' integration circuits, and so on.With the FRT requirements [9,10], the IIREG fault characteristics are closely associated with the grid-tie inverters' FRT strategy.However, the FRT strategies are diverse from manufacturer to manufacturer and unknown to the public.
To clearly reveal the fault characteristics of IIREGs, the basic action is to study on the FRT control strategy.Many advanced control techniques have been developed for grid-tie inverters, including deadbeat controllers [11], predictive techniques [12,13], controllers based on artificial intelligence tools [14], and multi-loop feedback controllers [15][16][17][18][19], and so on.Due to its good performance and simplicity, multi-loop feedback control appears as an attractive way for the inverter control.In achieving FRT ability, the widely used control strategies are the vector-oriented current feedback control [15].They are suitable only for symmetrical faults and cannot improve the FRT ability under the asymmetrical faults.
In order to enhance the asymmetrical FRT ability, some control strategies have also been proposed, such as the single vector current controller with feed forward negative-sequence grid-side voltage [16], dual vector current controller (DVCC) in a positive and negative synchronously rotating frame [17], and proportional-resonant controllers in a two-phase stationary frame [18,19].However, their main concerns are how to eliminate the DC-link fluctuation or to decrease the negative fault current.The inverters' maximum current limit, which inevitably exists under severe faults [20], is not still considered in these strategies.
In revealing the IIREG fault characteristic, most studies adopt the simulation methods.Ref. [21,22] analyzes the fault current contribution based on the IIREG' simulation models.In the simulation test, the IIREG adopts the normal grid-connected control strategies.The research result cannot accord with the FRT requirement.Further, Ref. [23][24][25] studies the fault current characteristics of IIREGs by considering the FRT control strategy.However, this FRT control strategy is not available under the asymmetrical grid faults.The mentioned above research results depend on the designated control strategy and show diversity due to different control strategies.
At the same time, in some references the IIREGs' fault current is also derived based on the designated control strategies.Consequently, the fault current expressions are not universal and cannot been applied for relay setting calculation.Ref. [26,27] proposes a controlled current source model for the IIREG system.In the model, its current magnitude depends on the terminal voltage and the DC-side active power.It is assumed that the reactive power supply is equal to zero after a grid-side fault [28,29].The assumption does not accord with the reactive power requirement of FRT codes.Ref. [30,31] deduce the fault current expression with the effect of the FRT control strategy.However, the inverters' current limit is not considered in the FRT control strategy and the fault current expression is suitable only for the assigned FRT control.
In this paper, in order to derive a consolidated expression of the fault current, the fault characteristics of IIREGs are theoretically analyzed.Since the fault characteristics are related to the FRT control strategy, the improved FRT strategy is developed to solve the problems in the existing literature.The remaining paper is organized as follows: Section 2 discusses the improved FRT control strategy under a severe fault.In Section 3, the characteristics of different frequency fault current from IIREGs are theoretically analyzed.In Section 4 the mathematical expression of the fundamental fault current is derived and verified based on the experimental test bench.Conclusions are drawn in Section 5.

Main Circuit Model
This section presents the main circuit model of IIREGs, which serve as the basis for both the design of the FRT strategy and the analysis on the fault current contribution.The integration topology of an IIREG is shown in Figure 1.Under the faults, the mathematical model on the AC-side of the grid-connected inverter can be expressed as Equation (1).
where the subscripts p and n indicate the positive-and negative-sequence components, respectively.E k dq , I k dq and V k dq (k = p, n) denote the space vectors of the grid-side voltage, output current, and AC-side voltage of the inverter, respectively.Here, R = R 1 + R 2 , and L = L 1 + L 2 .R 1 and L 1 are the inverter-side resistance and inductance of the inductor-capacitor-inductor (LCL) filter, respectively, and R 2 and L 2 denote the grid-side ones of the LCL filter.ω is the grid frequency.In this paper, in order to derive a consolidated expression of the fault current, the fault characteristics of IIREGs are theoretically analyzed.Since the fault characteristics are related to the FRT control strategy, the improved FRT strategy is developed to solve the problems in the existing literature.The remaining paper is organized as follows: Section 2 discusses the improved FRT control strategy under a severe fault.In Section 3, the characteristics of different frequency fault current from IIREGs are theoretically analyzed.In Section 4 the mathematical expression of the fundamental fault current is derived and verified based on the experimental test bench.Conclusions are drawn in Section 5.

Main Circuit Model
This section presents the main circuit model of IIREGs, which serve as the basis for both the design of the FRT strategy and the analysis on the fault current contribution.The integration topology of an IIREG is shown in Figure 1.Under the faults, the mathematical model on the AC-side of the grid-connected inverter can be expressed as Equation ( 1 where the subscripts p and n indicate the positive-and negative-sequence components, respectively.E k dq , I k dq and V k dq (k = p, n) denote the space vectors of the grid-side voltage, output current, and AC-side voltage of the inverter, respectively.Here, R = R1 + R2, and L = L1 + L2.R1 and L1 are the inverter-side resistance and inductance of the inductor-capacitor-inductor (LCL) filter, respectively, and R2 and L2 denote the grid-side ones of the LCL filter.ω is the grid frequency.The instantaneous active and reactive output power of the IIREGs during severe faults can be described as Equation (2).Here, we note that reactive power Qout is different from that defined in classical steady-state circuit theory [32] where the superscript c, s and o denote the cosine, sine and average components.P c out , P s out , Q c out , and Q s out are not equal to zero after asymmetrical faults.They can be represented in terms of the grid-side voltage and output current as: The instantaneous active and reactive output power of the IIREGs during severe faults can be described as Equation (2).Here, we note that reactive power Q out is different from that defined in classical steady-state circuit theory [32], i.e., where the superscript c, s and o denote the cosine, sine and average components.P c out , P s out , Q c out , and Q s out are not equal to zero after asymmetrical faults.They can be represented in terms of the grid-side voltage and output current as: Equation (3) shows that P c out has the same absolute value as Q s out , as well as P s out and Q c out .Therefore, by nullifying the oscillating components of the instantaneous active power, the instantaneous reactive power is also flattened.
Similarly, the instantaneous active power P 1 out and reactive power Q where C and U dc stand for the DC-link capacitance and voltage, respectively.During asymmetrical faults, the two-times frequency component of active power P 1 out yields a 100-Hz DC-link voltage ripple.Such a pulsating voltage causes detrimental effects on the control system of the grid-tied inverter and even leads to tripping off of the IIREG from the grid.

Improved FRT Control Strategy
To ensure that the IIREGs ride through the asymmetrical faults, the control strategy based on DVCC for the grid-tie inverter has been widely used.The strategy uses two control loops: four faster inner parallel current loops and a slower outer DC-link voltage control loop.The inner loops regulate the positive and negative output currents of the IIREG injected to the grid, whereas the outer loop acts as a supervisory controller and determines the average active power reference P o in the inner controller.The control structure enables flexible control of the output current of the IIREGs.Generally, any of the two control targets expressed in Equation ( 5) can be achieved: where the superscript * denotes the reference value.In Equation ( 5), the average reactive power Q 0 can be set to meet the FRT requirement.According to Equations ( 5) and (3), current references i p d * , i p q * , i n d * , and i n q * can be calculated.In Equation ( 5), the first sub-expression is to suppress the oscillation of the DC-link voltage by setting P s out * = 0 and Q s out * = 0 (Control Goal 1), whereas the second one is to eliminate the negative-sequence current through the inverter (i Control Goal 1 easily leads to dangerous high current through grid-tie inverter under the severe faults.Control Goal 2 may cause the oscillations in the DC-link voltage.Control Goal 1 and Control Goal 2 are suitable only for distant asymmetrical faults.
To enhance the FRT ability of IIREGs, an improved control strategy is studied in this section, as shown in Figure 2. Compared with the conventional control strategy based on DVCC, the developed FRT strategy can take care of both the inverters' allowable current limit and DC-link voltage fluctuation.A novel current limiter is designed to deal with the inverter over-current problem, and a controller for the DC chopper is improved to insure the DC-link voltage within its acceptable value.The corresponding details are explained next.
The key idea of the novel current limiter is to fully utilize the control ability of the grid-tie inverter within its allowable current limit.The current limiter is activated in the event that the instantaneous maximum current I max through inverter is greater than the inverter's current constraint I lim .With the limiter activation the positive-and negative-sequence current references are reset as: where subscript j denotes the dor q-axis component.α is a scalar coefficient of the current limiter, and it is less than 1 if I max > I lim .I max can be expressed as I max = max(I am , I bm , I cm ).I am , I bm , and I cm are the magnitudes of instantaneous currents i a , i b , and i c through the inverter.The instantaneous currents are obtained as follows: where |I k dq | (k = p, n) represent the amplitudes of the positive-and negative-sequence current vector references, respectively.θ p = arctan(i p q /i p d ), and θ n = 2π-arctan(i n q /i n d ) are the phase angles of the positive-and negative-sequence current vectors.
Sustainability 2018, 10, 44 5 of 16 constraint Ilim.With the limiter activation the positive-and negative-sequence current references are reset as: where subscript j denotes the d-or q-axis component.α is a scalar coefficient of the current limiter, and it is less than 1 if Imax > Ilim.Imax can be expressed as Imax = max(Iam, Ibm, Icm).Iam, Ibm, and Icm are the magnitudes of instantaneous currents ia, ib, and ic through the inverter.The instantaneous currents are obtained as follows: sin( ) sin( ) sin( 23 ) sin( 23 ) sin( 23 ) sin( 23 ) By substituting Equation ( 6) into Equation ( 5), we find that the oscillating DC-link voltage with Control Goal 1 or negative-sequence current through the inverter with Control Goal 2 can still be eliminated even though the current limiter is activated.In this paper, Control Goal 1 is chosen in order to keep the DC-link voltage within an acceptable range.
Due to the activation of the current limiter, the active power through the inverter is limited.However, the DC-link input power from the wind turbine or solar cell remains unchanged.Consequently, the imbalance between the DC-link input power and output power may cause a dangerous rise in the DC-link voltage.To prevent a DC-link overvoltage, the DC-link chopper is engaged.Although the chopper circuit is widely used in practical wind and solar power systems, its control strategy has not yet been significantly explored in the existing literatures.The control is crucial to solve the DC-link overvoltage problem.The design of such a control system is also one of the novel results of this paper.
Figure 2 shows that the controller for the DC-link chopper is automatically enabled once the positive-sequence component of the grid-side voltage drops below a critical threshold (0.9 per unit (p.u.)).The proportional-integral (PI) controller is employed to timely regulate the surplus power in the DC link and to prevent the DC-link overvoltage risks.To shorten the chopper response time, the integral part of PI controller is activated and reset to the most recent measurement of the DC-link voltage at the time when the DC-link voltage is greater than 1.05 p.u.Moreover, the reference of the By substituting Equation (6) into Equation ( 5), we find that the oscillating DC-link voltage with Control Goal 1 or negative-sequence current through the inverter with Control Goal 2 can still be eliminated even though the current limiter is activated.In this paper, Control Goal 1 is chosen in order to keep the DC-link voltage within an acceptable range.
Due to the activation of the current limiter, the active power through the inverter is limited.However, the DC-link input power from the wind turbine or solar cell remains unchanged.Consequently, the imbalance between the DC-link input power and output power may cause a dangerous rise in the DC-link voltage.To prevent a DC-link overvoltage, the DC-link chopper is engaged.Although the chopper circuit is widely used in practical wind and solar power systems, its control strategy has not yet been significantly explored in the existing literatures.The control is crucial to solve the DC-link overvoltage problem.The design of such a control system is also one of the novel results of this paper.
Figure 2 shows that the controller for the DC-link chopper is automatically enabled once the positive-sequence component of the grid-side voltage drops below a critical threshold (0.9 per unit (p.u.)).The proportional-integral (PI) controller is employed to timely regulate the surplus power in the DC link and to prevent the DC-link overvoltage risks.To shorten the chopper response time, the integral part of PI controller is activated and reset to the most recent measurement of the DC-link voltage at the time when the DC-link voltage is greater than 1.05 p.u.Moreover, the reference of the PI controller is equal to that of the outer PI controller in the DVCC control loop, which enables the IIREGs to immediately return to the pre-fault state after fault clearance.With the designed controller for the DC-link chopper, the DC-link voltage can be regulated within its acceptable value.As mentioned above, the current limiter can restrict the current through inverters within the maximum allowable currents.Hence, the improved FRT control strategy can solve both the inverter over-current problem and DC-link over-voltage problem.To test the improved FRT control strategy, the hardware-in-the-loop experiments have been conducted based on the test rig shown in Figure 3.
Sustainability 2018, 10, 44 6 of 16 PI controller is equal to that of the outer PI controller in the DVCC control loop, which enables the IIREGs to immediately return to the pre-fault state after fault clearance.
With the designed controller for the DC-link chopper, the DC-link voltage can be regulated within its acceptable value.As mentioned above, the current limiter can restrict the current through inverters within the maximum allowable currents.Hence, the improved FRT control strategy can solve both the inverter over-current problem and DC-link over-voltage problem.To test the improved FRT control strategy, the hardware-in-the-loop experiments have been conducted based on the test rig shown in Figure 3.As shown in Figure 7, the test rig consists of main controller, pulse-width-modulated (PWM) generator, real-time digital simulator (RTDS), and monitor.These hardware performance indicators are devised according to the corresponding international standards or the marketable product's design criteria.In the test rig, the main controller is basically composed of the digital signal processor (DSP)/field programmable gate array (FPGA) combined control boards.It can implement the control and protection algorithms of the IIREG system based on the modular programming method.The algorithm codes can be flexibly modified.The PWM generator is used for generating the electrical firing signals for the inverters.RTDS simulator is employed to simulate the main circuit of power grid with the tested IIREG.Monitor can be utilized for starting and stopping the IIREG system, so as to reset the control and protection parameters, and so on.
Based on the experimental test rig, the two cases are as follows.
The first case is to verify the asymmetrical FRT ability of the IIREGs.The IIREG's parameters are shown in the Appendix A. It is assumed that a two-line-to-ground fault (TLGF) occurs between phase-a and b in the collector line at t = 0.6 s and lasts for 0.65 s.The fault causes a 96% imbalance in the grid-side voltage (E p dq = 0.57 p.u.; E n dq = 0.55 p.u.). Figure 4 shows the actual test results with the conventional DVCC strategy and improved control strategy.From Figure 4, when the conventional DVCC strategy is applied, during the fault the DC-link voltage and the current through inverter exceed their allowable scopes.The IIREG becomes unstable after the fault.However, the proposed FRT strategy assures the stable operation of IIREG.Both the current through inverter and the voltage in the DC link are kept within their acceptable limits.The result indicates that the proposed control strategy can effectively enlarge the feasible region of riding through the asymmetrical faults.As shown in Figure 7, the test rig consists of main controller, pulse-width-modulated (PWM) generator, real-time digital simulator (RTDS), and monitor.These hardware performance indicators are devised according to the corresponding international standards or the marketable product's design criteria.In the test rig, the main controller is basically composed of the digital signal processor (DSP)/field programmable gate array (FPGA) combined control boards.It can implement the control and protection algorithms of the IIREG system based on the modular programming method.The algorithm codes can be flexibly modified.The PWM generator is used for generating the electrical firing signals for the inverters.RTDS simulator is employed to simulate the main circuit of power grid with the tested IIREG.Monitor can be utilized for starting and stopping the IIREG system, so as to reset the control and protection parameters, and so on.
Based on the experimental test rig, the two cases are as follows.
The first case is to verify the asymmetrical FRT ability of the IIREGs.The IIREG's parameters are shown in the Appendix A. It is assumed that a two-line-to-ground fault (TLGF) occurs between phase-a and b in the collector line at t = 0.6 s and lasts for 0.65 s.The fault causes a 96% imbalance in the grid-side voltage (E p dq = 0.57 p.u.; E n dq = 0.55 p.u.). Figure 4 shows the actual test results with the conventional DVCC strategy and improved control strategy.From Figure 4, when the conventional DVCC strategy is applied, during the fault the DC-link voltage and the current through inverter exceed their allowable scopes.The IIREG becomes unstable after the fault.However, the proposed FRT strategy assures the stable operation of IIREG.Both the current through inverter and the voltage in the DC link are kept within their acceptable limits.The result indicates that the proposed control strategy can effectively enlarge the feasible region of riding through the asymmetrical faults.The second case is to test the symmetrical FRT ability of the IIREGs.It is assumed that a fault occurs in the collector line at t = 0.6 s and lasts for 0.65 s.After the fault, grid-side voltage falls from 1.02 p.u. to 0.2 p.u. Figure 5 shows the test results with the improved control strategy and conventional FRT strategy.
In Figure 5, the difference between the improved control strategy and conventional strategy is the designed controller for DC-link chopper.Moreover, the conventional strategy can only limit the balanced current through inverter.From Figure 5, with the effect of two control strategies both DC-link voltage and the current through inverter are within their allowable values after and during the fault.However, once the fault is cleared, the DC-link voltage is changed greatly (from 1.24 kV to 0.71 kV) with the conventional FRT strategy in Figure 5b.As a result, at t = 1.32 s the current through inverter is regulated into a steady-state value in Figure 5c.By comparison, with the effect of improved control strategy, after the fault clearance DC-link voltage and the current through inverter can be quickly restored into their corresponding pre-fault values.
In the test cases, it was established that the proposed FRT strategy can help the IIREGs to ride through the asymmetrical faults that causes a 96% imbalanced grid-side voltage (|E n dq |/|E p dq |).At the same time, the proposed strategy can also help the IIREGs to ride through the severe symmetrical faults.The second case is to test the symmetrical FRT ability of the IIREGs.It is assumed that a fault occurs in the collector line at t = 0.6 s and lasts for 0.65 s.After the fault, grid-side voltage falls from 1.02 p.u. to 0.2 p.u. Figure 5 shows the test results with the improved control strategy and conventional FRT strategy.

Theoretical Analysis for IIREGs' Fault Current Characteristics
Due to the instantaneousness of the fault initiation, a transient condition in IIREGs inevitably exists.Different from the CSGs, the transient characteristics of IIREGs are more complicated with multi-factor coupled effects.These factors include not only the integration circuit of IIREGs, but also the FRT control strategy, its controller parameters, and its control goals.As a result, the theoretical study on fault current characteristics of the IIREGs becomes difficult.
In this section, the characteristics of different frequency current from IIREGs are theoretically In Figure 5, the difference between the improved control strategy and conventional strategy is the designed controller for DC-link chopper.Moreover, the conventional strategy can only limit the balanced current through inverter.From Figure 5, with the effect of two control strategies both DC-link voltage and the current through inverter are within their allowable values after and during the fault.However, once the fault is cleared, the DC-link voltage is changed greatly (from 1.24 kV to 0.71 kV) with the conventional FRT strategy in Figure 5b.As a result, at t = 1.32 s the current through inverter is regulated into a steady-state value in Figure 5c.By comparison, with the effect of improved control strategy, after the fault clearance DC-link voltage and the current through inverter can be quickly restored into their corresponding pre-fault values.
In the test cases, it was established that the proposed FRT strategy can help the IIREGs to ride through the asymmetrical faults that causes a 96% imbalanced grid-side voltage (|E n dq |/|E p dq |).At the same time, the proposed strategy can also help the IIREGs to ride through the severe symmetrical faults.

Theoretical Analysis for IIREGs' Fault Current Characteristics
Due to the instantaneousness of the fault initiation, a transient condition in IIREGs inevitably exists.Different from the CSGs, the transient characteristics of IIREGs are more complicated with multi-factor coupled effects.These factors include not only the integration circuit of IIREGs, but also the FRT control strategy, its controller parameters, and its control goals.As a result, the theoretical study on fault current characteristics of the IIREGs becomes difficult.
In this section, the characteristics of different frequency current from IIREGs are theoretically discussed under the faults.It is commonly known that grid-side voltage of IIREGs is suddenly changed after a fault.The voltage variation can be viewed as the summation of a set of different frequency trigonometric functions.With the impact of different frequency voltages, the output currents of IIREGs include high-frequency and low-frequency components (near the fundamental frequency).
Figure 6a shows the connection circuit of a grid-tied IIREG.The topology is typical, and it has been widely used for the Chinese power grid with the REGs.It is assumed that a fault occurs at the point of common coupling (PCC).Figure 6b shows the flowing path of high frequency fault currents.The currents flow from the fault location into the filter of IIREGs.They are independent of the IIREGs' control.They are related with the passive circuits, i.e., local transformer(s), overhead lines, and underground cables of the collector system, filter, and so on.Next, the characteristics of different frequency fault currents are analyzed theoretically.To describe the high-frequency currents, the equivalent model of IIREG's passive network is built.Development of the model includes the following steps [33].
Step (1): At PCC, disconnect the IIREG generation units at the AC-side terminals of the corresponding converters.
Step (2): Inject a current signal into the IIREG system.The current signal is the summation of a set of sinusoidal current components at unity amplitudes, zero phase angles, and discrete frequencies that cover a specified frequency bandwidth and specified frequency steps.The frequencies of these currents cover the desired frequency bandwidth.The frequency bandwidth is As shown in Figure 6c, low frequency components flow from the IIREG into the fault location.They are mainly determined by the IIREGs' control, i.e., the FRT control schemes, its controller parameters, and its control goals.However, they are irrelevant to the aforementioned passive circuits.Moreover, although the IIREGs' control loops may also generate high-frequency currents due to the fault initiation, the currents flow into the ground through the capacitor of the LCL filter from the IIREG generation units.Thus, the high-frequency currents are non-existent, viewed from the PCC.
Next, the characteristics of different frequency fault currents are analyzed theoretically.To describe the high-frequency currents, the equivalent model of IIREG's passive network is built.Development of the model includes the following steps [33].
Step (1): At PCC, disconnect the IIREG generation units at the AC-side terminals of the corresponding converters.
Step (2): Inject a current signal into the IIREG system.The current signal is the summation of a set of sinusoidal current components at unity amplitudes, zero phase angles, and discrete frequencies that cover a specified frequency bandwidth and specified frequency steps.The frequencies of these currents cover the desired frequency bandwidth.The frequency bandwidth is specified based on the type of EMT studies, e.g., 0 to 50 kHz.
Step (3): Deduce the IIREG terminal voltage.This voltage represents the IIREG equivalent impedances at the frequencies of the injected currents.
Step (4): Decompose the voltage, based on the Fourier analysis, into its components at the frequencies of the injected current components.
Step ( 5): Fit a rational function of the form: to the deduced results of Step (4).In Equation ( 8), residues c n and poles a n can be either real or complex numbers, while d and h are real and can be obtained based on several methods, e.g., the vector fitting method.
According to the aforementioned steps, the equivalent model shown in Equation ( 8) can be built for the system shown in Figure 6b.Their related parameters are listed in the Appendix A, which are mostly based on the information from industries and the literature.Table 1 shows the residues and poles of the obtained rational function and its time-domain performance indicators.Based on the conjugate poles in Table 1, the decay time and oscillating frequency of the high-frequency fault current can be calculated.From Table 1, the decay time of 327 Hz current component is about 19.04 ms.And the attenuation time of 5034 Hz current component is approximately 27.63 ms.Other frequency current components are reduced at a very fast rate, so their reduction time can be ignored.
After the high-frequency current decays to zero, the remaining component is the fundamental frequency current.This can be calculated based on the fundamental admittance.According to the equivalent model of IIREG's passive network, the fundamental positive and negative admittance Y 1 = Y 2 = 4.0 × 10 −5 + j8.9 × 10 −4 Si are very small.Thus, the fundamental current is small through the IIREG's passive circuits during the fault.
Figure 7 shows the instantaneous phase-a current from the practical IIREG and its passive circuit when the fault occurs at t = 0.113 s.From Figure 7a, the high-frequency currents from the passive circuit decay last for only 18.8 ms during the fault.By comparing Figure 7a with Figure 7b, the fundamental current amplitudes through the passive circuit and from the overall IIREG are respectively equal to 0.00062 kA and 0.04613 kA during the steady-state fault periods.The former current is 1.34% that of the latter.
After the high-frequency current decays to zero, the remaining component is the fundamental frequency current.This can be calculated based on the fundamental admittance.According to the equivalent model of IIREG's passive network, the fundamental positive and negative admittance Y1 = Y2 = 4.0 × 10 −5 + j8.9 × 10 −4 Si are very small.Thus, the fundamental current is small through the IIREG's passive circuits during the fault.
Figure 7 shows the instantaneous phase-a current from the practical IIREG and its passive circuit when the fault occurs at t = 0.113 s.From Figure 7a, the high-frequency currents from the passive circuit decay last for only 18.8 ms during the fault.By comparing Figure 7a with Figure 7b, the fundamental current amplitudes through the passive circuit and from the overall IIREG are respectively equal to 0.00062 kA and 0.04613 kA during the steady-state fault periods.The former current is 1.34% that of the latter.Therefore, high-frequency fault currents provided by IIREGs last only for 1-2 cycles.The currents are decided by the passive circuits of IIREGs' integration topology.The fundamental fault currents always exist, and they are affected mainly by the IIREGs' control system.In the following sections, the characteristics of fundamental fault currents are discussed.

Mathematical Expression of Fundamental Fault Current
In the section, the fundamental fault current expression of IIREGs is derived on the basis of the proposed asymmetrical FRT strategy.It can provide a basis for relay setting calculations of the power grid connected with a large number IIREGs.Therefore, high-frequency fault currents provided by IIREGs last only for 1-2 cycles.The currents are decided by the passive circuits of IIREGs' integration topology.The fundamental fault currents always exist, and they are affected mainly by the IIREGs' control system.In the following sections, the characteristics of fundamental fault currents are discussed.

Mathematical Expression of Fundamental Fault Current
In the section, the fundamental fault current expression of IIREGs is derived on the basis of the proposed asymmetrical FRT strategy.It can provide a basis for relay setting calculations of the power grid connected with a large number IIREGs.

Derivationfor Fundamental Fault Current
Due to the fast response of the gird-connected inverter controller, the IIREGs can quickly reach the steady state under fault conditions.During faults, the steady-state behavior of the IIREGs is strongly dependent on the FRT control.Combining Equations (3) with ( 5), the positive-and negative-sequence components of the fundamental fault current from the IIREGs with Control Goal 1 are expressed as follows (in a p.u. system): where E p m and E n m are the positive-and negative-sequence amplitudes of grid-side voltage.γ reflects the drop coefficient of the positive-sequence grid-side voltage.β = E n m /E p m denotes the imbalance degree of grid-side voltage.E m is the rated voltage magnitude.S o represents the apparent power injected into the grid.From Equation ( 9), the IIREGs can generate the negative-sequence currents.The current characteristic is different from that of the CSGs.
By taking into account the deliverable power limit through the inverter, the apparent power S o derived using the proposed control strategy is expressed as: In addition, the three phase current amplitudes I am , I bm , and I cm through the inverter can be calculated as: where phase angles θ p and θ n are, respectively, derived as: where k s = Q o /P o and k u = e n q /e n d .The phase-angle difference θ i is expressed as: The angle θ i is closely related with negative-sequence grid-side voltage.Given the positive and negative current amplitude I k m (k = p, n), the three phase current peaks vary periodically with θ i .If θ i is equal to 0, 3π/4, or 5π/4, the current magnitude in phases a, b, or c is, respectively, the largest.The peak is equal to the magnitude sum of the positive-and negative-sequence current vectors.
By substituting Equations ( 10) and ( 13) into Equation (11), the three phase current amplitudes is also expressed as: From Equation ( 14), it is found that the short-circuit current provided by IIREGs is determined by two factors.The one is closely related with the apparent power delivered to grid and the inverter's ampere constraint.The power is determined by FRT control goal that is a fixed value for the specified grid code.The other is the amplitudes and angles of positive and negative sequence grid-side voltage vectors.These voltage vectors depend on both the equivalent short-circuit parameters of a connected grid and the grid fault conditions.In fact, the equivalent parameters and the fault conditions should be given from the perspective of the study on the relay protection.Thus, the steady-state short-circuit current expression of IIREGs as shown in Equation ( 14) is independent of the inverter's controllers and its parameters.The fault current values can be obtained without knowing the inverter's control strategies.

Verification
To verify the fault current expression, the detailed test model is built as shown in Figure 8.The topology is typical, and it has been widely used for the transmission grid with the large-scale IIREGs.The related parameters are listed in the Appendix A, which are mostly based on the information from industries and the literature.
parameters of a connected grid and the grid fault conditions.In fact, the equivalent parameters and the fault conditions should be given from the perspective of the study on the relay protection.Thus, the steady-state short-circuit current expression of IIREGs as shown in Equation ( 14) is independent of the inverter's controllers and its parameters.The fault current values can be obtained without knowing the inverter's control strategies.

Verification
To verify the fault current expression, the detailed test model is built as shown in Figure 8.The topology is typical, and it has been widely used for the transmission grid with the large-scale IIREGs.The related parameters are listed in the Appendix A, which are mostly based on the information from industries and the literature.Based on the experimental model in Figure 8, the tests was done using the hardware-in-the-loop as shown in Figure 3.At the same time, according to Equation ( 14) the fault currents from the IIREG were calculated using the MATLAB software.Table 2 shows the comparison results with different active and reactive power commands.Here, it is assumed that a two-line-to-ground fault (TLGF) occurs between phases-a and -b in bus C at t = 0.6 s and lasts for 0.65 s.Before the fault the IIREG operates at its rated state, and its output current is approximately 1.245 kA.
From Table 2, it is found that the difference between the calculation results and test results is very small.The maximal error value reaches 6.45%, only when the desired powers of grid-tie inverter are Po = 1 p.u., Qo = 0.1 p.u.Under the other power commands, the errors are less than 5%.It is indicated that the proposed IIREG's fault current expression as shown in Equation ( 14) has high accuracy.
Moreover, compared with the calculated or tested fault currents results, it is found that the relationship among the three-phase current amplitudes is different withvarious active and reactive power commands.With different cases the faulty phase-b current magnitude reaches the inverter's ampere constraint (2 p.u., 2.49 kA) due to the current limiter activation, but the relationship between the phase-a and -c current amplitudes is affected by the actual real and reactive power commands.Therefore, the active and reactive power commands for grid-tie inverter affect not only the amplitude values of IIREG's fault currents but also the relationship of the three-phase current amplitudes.The fault current characteristic of IIREG is different from that of synchronous generators.The fault current of synchronous generators is mainly influenced by the machine equivalent impedance.The impedance is not associated with the generators' active and reactive injections.Based on the experimental model in Figure 8, the tests was done using the hardware-in-the-loop as shown in Figure 3.At the same time, according to Equation ( 14) the fault currents from the IIREG were calculated using the MATLAB software.Table 2 shows the comparison results with different active and reactive power commands.Here, it is assumed that a two-line-to-ground fault (TLGF) occurs between phases-a and -b in bus C at t = 0.6 s and lasts for 0.65 s.Before the fault the IIREG operates at its rated state, and its output current is approximately 1.245 kA.From Table 2, it is found that the difference between the calculation results and test results is very small.The maximal error value reaches 6.45%, only when the desired powers of grid-tie inverter are P o = 1 p.u., Q o = 0.1 p.u.Under the other power commands, the errors are less than 5%.It is indicated that the proposed IIREG's fault current expression as shown in Equation ( 14) has high accuracy.
Moreover, compared with the calculated or tested fault currents results, it is found that the relationship among the three-phase current amplitudes is different withvarious active and reactive power commands.With different cases the faulty phase-b current magnitude reaches the inverter's ampere constraint (2 p.u., 2.49 kA) due to the current limiter activation, but the relationship between the phase-a and -c current amplitudes is affected by the actual real and reactive power commands.Therefore, the active and reactive power commands for grid-tie inverter affect not only the amplitude values of IIREG's fault currents but also the relationship of the three-phase current amplitudes.The fault current characteristic of IIREG is different from that of synchronous generators.The fault current of synchronous generators is mainly influenced by the machine equivalent impedance.The impedance is not associated with the generators' active and reactive injections.

Conclusions
In order to reveal the IIREGs' fault current characteristics and further deduce the universal fault current calculation model, it is important to study on the FRT control strategy for the IIREGs.Hence, in this paper an advanced FRT control strategy is firstly proposed.In the control strategy, a novel current limiter is designed for restricting the current through inverter.Meanwhile, a controller for the DC-link chopper is improved to keep the DC-link voltage within its allowable value.
The hardware-in-the-loop test results indicate that the proposed strategy can effectively enlarge the feasible region of riding through the faults, including the severe asymmetrical faults (the imbalance of grid-side voltage is about 100%) and serious symmetrical faults (the drop coefficient of the grid-side voltage is approximately 20%).
Based on this, the characteristics of different frequency fault currents from IIREGs are theoretically analyzed after and during the faults.It is revealed that the respective affecting factors of high frequency and fundamental frequency fault current are independent.The high currents are determined mainly by the IIREGs' passive circuits, i.e., local transformer(s), overhead lines, and underground cables of the collector system, filter, and so on.The fundamental fault currents are closely related with FRT goals and the inverter' ampere constraint.The high currents last only for 1~2 cycles after the faults, whereas the fundamental fault currents always exist.
Further, the fundamental fault current calculation model of IIREGs is derived.The deduced short-circuit current expression is determined by two factors.The one is closely related with the apparent power delivered to grid and the inverter's ampere constraint.The apparent power is related only with the FRT control goal, independent of the FRT controller parameters.The FRT control goal is a known value for the specified grid code.The other factor is the grid-side voltage vectors.The voltages vectors can be obtained if the short-circuit equivalent parameters of a connected grid and the grid fault conditions are given.For the fault analyzing or relay setting calculating, the short-circuit parameters and the fault conditions should be treated as the known values.Thus, the fault current contributions from the IIREGs can be calculated without knowing their control strategies.The proposed fault current calculation model is useful for relay-setting calculations of the grid with a large number of IIREGs.

Figure 3 .
Figure 3. Physical layout of the experimental test bench.

Figure 3 .
Figure 3. Physical layout of the experimental test bench.

Figure 4 .
Figure 4. Asymmetrical fault test results with the improved FRT strategy and conventional DVCC strategy; (a) The DC-link voltage with the improved FRT strategy; (b) The DC-link voltage with conventional DVCC strategy; (c) The current through inverter with the improved FRT strategy; (d) The current through inverter with conventional DVCC strategy.

Figure 4 .
Figure 4. Asymmetrical fault test results with the improved FRT strategy and conventional DVCC strategy; (a) The DC-link voltage with the improved FRT strategy; (b) The DC-link voltage with conventional DVCC strategy; (c) The current through inverter with the improved FRT strategy; (d) The current through inverter with conventional DVCC strategy.

Figure 5 .
Figure 5. Symmetrical fault test with the improved FRT strategy and conventional control strategy; (a) The DC-link voltage with the improved FRT strategy; (b) The DC-link voltage with conventional FRT strategy; (c) The current through inverter with the improved FRT strategy; (d) The current through inverter with conventional FRT strategy.

Figure 5 .
Figure 5. Symmetrical fault test with the improved FRT strategy and conventional control strategy; (a) The DC-link voltage with the improved FRT strategy; (b) The DC-link voltage with conventional FRT strategy; (c) The current through inverter with the improved FRT strategy; (d) The current through inverter with conventional FRT strategy.

Figure 6 .
Figure 6.The path of high-and low-frequency fault currents from IIREG; (a) Integration topology of an IIRGR; (b) The path of the high-frequency fault current; and (c) The path of the low-frequency fault current.

Figure 6 .
Figure 6.The path of high-and low-frequency fault currents from IIREG; (a) Integration topology of an IIRGR; (b) The path of the high-frequency fault current; and (c) The path of the low-frequency fault current.

Figure 7 .
Figure 7. Instantaneous phase-a current when the fault occurs at t = 0.113 s; (a) Current through the passive circuit; and (b) Current from the practical IIREG.

Figure 7 .
Figure 7. Instantaneous phase-a current when the fault occurs at t = 0.113 s; (a) Current through the passive circuit; and (b) Current from the practical IIREG.

Figure 8 .
Figure 8. Test bed system with a inverter-interfaced renewable energy generator. ).

Table 1 .
Parameters of the rational function for the IIREG's passive network.

Table 2 .
Fault currents of IIREGs with different active and reactive power commands.Test bed system with a inverter-interfaced renewable energy generator.

Table 2 .
Fault currents of IIREGs with different active and reactive power commands.