Adaptive Sliding-Mode Controller for a Zeta Converter to Provide High-Frequency Transients in Battery Applications

: Hybrid energy storage systems significantly impact the renewable energy sector due to their role in enhancing grid stability and managing its variability. However, implementing these systems requires advanced control strategies to ensure correct operation. This paper presents an algorithm for designing the power and control stages of a hybrid energy storage system formed by a battery, a supercapacitor, and a bidirectional Zeta converter. The control stage involves an adaptive sliding-mode controller co-designed with the power circuit parameters. The design algorithm ensures battery protection against high-frequency transients that reduce lifespan, and provides compatibility with low-cost microcontrollers. Moreover, the continuous output current of the Zeta converter does not introduce current harmonics to the battery, the microgrid, or the load. The proposed solution is validated through an application example using PSIM electrical simulation software (version 2024.0), demonstrating superior performance in comparison with a classical cascade PI structure.


Introduction
Current industrial processes are crucial in pursuing high efficiency, reliability, and adaptability [1,2].Harnessing the power of data and optimization algorithms is imperative, as they are the key to improving the system's control, which is needed to stay competitive in the evolving industrial landscape.Artificial intelligence (AI) algorithms and data-driven optimization models for intelligent manufacturing processes have been used to improve production efficiency, reduce costs, and improve the quality of manufacturing services [3,4].The use of optimization algorithms to obtain profitable, productive, controllable, safe, and sustainable processes is presented in [5,6].In particular, Ref. [5] reviews multi-objective algorithms for energy production, supply chains, and chemical industries.
Meanwhile, in Ref. [6], genetic algorithms (GAs) and artificial neural networks (ANNs) are used to define the objective function of the optimization algorithms applied in the metallurgical industry.In addition, Ref. [7] highlights algorithms for data-based industrial process prediction, namely time series and factor-based predictions.That work tests different prediction techniques in multiple steel plant processes.
Energy transition has forced industries to focus on critical processes such as managing electrical energy storage systems (ESSs).Multiple works have focused on ESS characterization, including the description of their components, control strategies, applications, and technologies for high-power systems [8][9][10], as well as their use in multi-source power systems [11], their techno-economic assessment when integrated with renewable energy [12], and the implementation of battery management systems (BMSs) [13].These systems are fundamental in electrical vehicles (EVs) and microgrids (MGs) based on renewable energy.For example, for EVs under heavy-duty conditions, Ref. [14] evaluates different energy storage system topologies, and Ref. [15] presents a comparison study of semi-active ESS topologies for EVs.Ref. [16] provides a critical review of devices with high energy density and high power density used in electrical transportation; meanwhile, Ref. [17] reports a review of standards and challenges of ESSs for EVs.Moreover, Ref. [18] implements several control schemes tested on EVs with a real driving cycle.Similarly, Ref. [19] presents a systematic review of ESS control techniques for grid-connected and standalone systems based on artificial intelligence.In contrast, Ref. [20] discusses the importance of ESSs in MGs with renewable energy sources.
Among energy storage systems, hybrid ESSs (HESSs) are relevant since the joint operation of complementary energy sources, i.e., sources with high energy density and sources with high power density, guarantees improved power quality, increased energy efficiency, and better dynamic response.Ref. [10] presents examples of HESS installations that improve grid stability and power quality with frequency regulation.A detailed review of HESS benefits is reported in Ref. [20], where the contributions of HESS to MGs are highlighted.For example, HESSs contribute to power quality, offering the MG the ability to provide clean and stable power with a constant power flow, as well as a wave-pure and noise-free sinusoidal within the acceptable frequency and voltage limits.Similarly, Ref. [21] evaluates the capabilities of HESSs to mitigate fluctuations and uncertainty of renewable energy.ESSs with high power density, like supercapacitors or flywheels [21,22], can support loads that demand fast power peaks, while ESSs with high energy density, like batteries [21,23], can provide sustained power for a long time (hours or days).
Different topologies exist for implementing HESSs depending on the converters action; those systems are denominated as passive, semi-active, or fully active.In a passive HESS, any source is managed using a converter, while in semi-active HESS, converters manage some of the sources.For example, the battery pack is regularly connected to the DC bus, while a DC/DC converter manages the supercapacitor [24,25].Finally, in a fully active HESS, each source is managed by a dedicated converter.Some reviews on topologies for HESS have been published in the last few years.According to the analysis reported in [26], multi-input, multi-port, coupled-inductor, switched-capacitor, and z-source/quasiz-source converter are suitable for a HESS formed by a battery and a supercapacitor.Those topologies provide bidirectional power flow in EVs, DC MGs, and renewable energy applications.Ref. [16] reports a broad analysis of passive, semi-active, and fully active topologies for HESSs formed by a battery and a supercapacitor.That article highlights the strengths, weaknesses, and opportunities associated with each HESS setup.Ref. [27] also reviews the state of the art on HESS topologies, including reconfigurable topologies at the cell and module levels.Similarly, four semi-active HESSs are discussed in Ref. [15], which are based on supercapacitors and batteries.
Many works on HESSs with semi-active and fully active configurations have been recently published.In Refs.[28,29], a PV system with a fully active HESS, formed by a battery, a supercapacitor (SC), and a bidirectional buck-boost converter, is tested with several algorithms, namely classical PI, an ANN, and Model Predictive Control (MPC).In that work, the mathematical model of the controllers is presented, but the implementation of the algorithms is not discussed.In Ref. [30], the combined control between an optimization algorithm and a neural network is applied to a bidirectional DC-DC converter of an EV; the authors state that algorithms enhanced performance and reduced computation time compared with other methods; however, the implementation is not discussed.In Ref. [31], a fully active HESS formed by a PV array, a battery, and a supercapacitor is presented.The control algorithms for each converter are classical PI structures, and the references for the controllers of both the battery and the supercapacitor converters are based on a power management strategy, in which the missing power on the load is first compensated with the battery and later with the supercapacitor.A structure similar to that reported in [31] is proposed in [25], but there is a fuel cell instead of a PV array.In that work, a fuzzy logic algorithm of 36 rules controls an energy management unit (EMU), which distributes the power among sources and sets the references for the centralized algorithm that controls all HESS converters.
Table 1 summarizes the characteristics of some works published in recent years with HESSs similar to the solution proposed in this manuscript.The review shows that HESSs are based on SCs and batteries, fully active topologies, and buck-boost converters.Control algorithms are diverse, but the classical PI structure is the most common solution.However, some works adopt control schemes based on intelligent algorithms (ANN, Recalling-Enhanced Recurrent Neural Network-RERNN), optimization algorithms (Sand Cat Swarm Optimization-SCSO, MPC), and non-linear algorithms (Supertwisting Sliding Mode Controller-SSMC).Nevertheless, none of the analyzed references implement the HESS with a Zeta converter managing the storage devices; only one reference controls the system with sliding-mode control, but it does not protect the battery from fast current transients.This manuscript introduces a unique HESS system with a semi-active topology.In this system, the SC is managed by a bidirectional converter, and the battery is directly connected to the DC bus (see Figure 1).The main feature of this setup is the use of a bidirectional Zeta converter and a sliding-mode controller (SMC).The Zeta converter has two key features; it works with any conversion relations and it has a continuous output current.In this way, the Zeta converter can connect any SC with any battery, and it prevents currents with high derivatives in the battery, decreasing its degradation.Furthermore, the SMC has several advantages when used with switching converters.First, its output is a binary signal, which fits perfectly with the converter control input, avoiding the implementation of a Pulse-Width Modulator (PWM); second, the SMC is a non-linear technique that is able to ensure global stability; third, the SMC is robust to variations in the system parameters; and finally, the SMC is integrated into a co-design process of the plant/controller, which is another contribution of this paper.The SMC algorithm proposed in this manuscript ensures three essential conditions:

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Stable DC/DC converter operation.

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Reduced harmonics in the battery current.

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Safe SC voltage regulation.
In summary, the device proposed in this manuscript is a semi-active HESS.Its purpose is to help the battery to deliver fast current transients to the load without altering the power management or the bus control system.Hence, the device's installation and operation are transparent to the microgrid.This manuscript is organized into five more sections: Section 2 presents the modeling of the power circuit, where the switched model, average model, stability conditions, and current/voltage ripple are discussed.In addition, Section 3 shows the design and analysis of the SMC, where the switching function is defined, the global stability is demonstrated, the closed-loop dynamic is designed, and the switching frequency limitation is imposed.The design process of the converter and the controller is presented in Section 4, where the algorithms for the selection of passive components and the implementation of the SMC law are illustrated; this section also includes the design of the high-pass filter used to avoid high-frequency current harmonics in the battery.The algorithms for the adaptive SMC's digital implementation and the PSIM simulations are discussed in Section 5, where the digital implementation reduces the computational burden on a low-cost microcontroller.Finally, the conclusions close the manuscript.
In summary, the contributions of this paper are: • Definition of the algorithms for designing the power stage and the adaptive SMC.

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Providing a battery current without high-frequency transients.

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Algorithms for implementing the adaptive SMC on low-cost microcontrollers with low computation burden.

Power Circuit Modeling
The proposed solution considers the parallel connection of a bidirectional Zeta converter with the battery to be supported; the electrical scheme of this solution is depicted in Figure 2.This circuit describes the electrical structure of the bidirectional Zeta converter, which is formed by two capacitors (C 1 and C 2 ), two inductors (L 1 and L 2 ), and two MOS-FETs.In addition, the proposed solution requires a fast controller with a wide operation range because the Zeta converter must be stable for capacitor voltages lower, equal to, or higher than the battery voltage; also, it must support positive, negative, and null current conditions.Therefore, the proposed solution includes the design of an adaptive slidingmode controller (adaptive SMC) to ensure the correct operation of the system.The adaptive SMC requires two voltage sensors, one for the capacitor C 2 voltage (v C 2 ) and another for the battery voltage (v b ).It also requires three current sensors, one for the L 1 current (i L 1 ), another for the L 2 current (i L 2 ), and a final one for the load/microgrid current (i o ) that is served by the battery.The design of the adaptive SMC requires a control-oriented model of the power system.Such a model is obtained by writing the differential equations of the inductor currents and capacitor voltages for each possible state of the control signal, i.e., u = 1 and u = 0, following the classical method based on charge and volt-second balances reported in [32].For the first condition (u = 1), the differential equations are given in Equations ( 1)-(4).
The previous two sets of equations must be mixed into a single set of non-linear differential equations, thus forming the switched model of the power system given in Equations ( 9)- (12).In such a model, u is the control signal of the MOSFETs, and u = 1 − u is the complementary control signal.
The switched model can be averaged within the switching period to generate the averaged model, which is useful for analyzing the main dynamic behavior of the power system; this modeling strategy is documented in [32].Taking into account that the duty cycle d corresponds to the average value of the control signal u, as given in Equation ( 13), the averaged model of the power system is obtained as reported in Equations ( 14)- (17), where d ′ = 1 − d is the complementary duty cycle and T sw is the switching period.
Finally, the steady-state conditions of the power system are obtained from the averaged model by considering the derivatives equal to zero, as described in [32]: Another important analysis concerns the current and voltage ripples in the power system.Then, the magnitude of the ripples on the inductor currents i L1 and i L2 is calculated from Equations ( 5) and ( 6) following the method reported in [32]: The magnitude of the voltage ripple in the C 2 capacitor must be calculated from the charge stored and extracted from the capacitor during a switching period.Figure 3 shows the C 2 voltage and current ripple waveforms, where current i C2 is obtained from Equation (12).The charge stored in C 2 when i C2 is positive is equal to the charge extracted when i C2 is negative due to the charge balance principle, and it is equal to ∆Q C2 = d • T sw • ∆i C2 /4.Such a charge is also related to the voltage change in C 2 as ∆Q C2 = C 2 • ∆v C2 , where ∆v C2 is the voltage ripple at C 2 .Moreover, since both i L1 and i L2 are in phase, as observed in Equations ( 1), (2), ( 5) and ( 6), the ripple magnitude in the C 2 current is ∆i C2 = ∆i L1 + ∆i L2 .Finally, the magnitude of the voltage ripple in the C 2 capacitor is given as follows: In addition, Figure 3 also shows that the peak value of the current ripple occurs when the voltage ripple is equal to zero; similarly, the peak value of the voltage ripple occurs when the current ripple is equal to zero.This condition will be important in the analysis of the switching frequency reported in Section 3.5.

Design and Analysis of the Sliding-Mode Controller
The sliding-mode controller must be designed to ensure the following conditions:

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Stable operation of the Zeta converter, which requires the stable relation between i L1 and i L2 currents given in Equation ( 20).

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Regulate the output current of the Zeta converter (i L2 ) to provide the high-frequency components of the load current (i o ), and at the same time, regulate the C 2 voltage to avoid a deep discharge or a dangerous overcharge.
The first condition is ensured by introducing the first part of the switching function Ψ given in Equation (24), which corresponds to relation (20).The second condition is achieved by introducing the second part of Ψ.The i R value is provided by a high-pass filter, which is discussed in Sections 4.2 and 4.4; the deviation of the C 2 voltage from the safe value v R is also introduced in this second part, where the value of the k v gain will be discussed in Section 3.4.Finally, the sliding surface Φ forces the switching function to slide around zero to impose a null error; this is formalized in Equation (25). where The feasibility of designing an SMC based on the previous surface must be confirmed using the transversality, reachability, and equivalent control analyses discussed in [33]; the following subsections report the results of those analyses.

Transversality Analysis
The transversality condition evaluates the controller's capability to modify the power system's behavior.Such an evaluation is focused on verifying the presence of the control variable u in the derivative of the switching function, which defines the trajectory of the SMC.The formalization of this test is the following: Therefore, the time derivative of the switching function ( 24) is calculated: Then, evaluating the transversality value using the previous derivative leads to the following equation: Finally, the design of the parameters of both the Zeta converter and SMC must fulfill the transversality condition (26) using Equation (28); this evaluation is presented in Section 4.3.

Reachability Analysis
The reachability conditions evaluate the capability of the controller to reach the sliding surface.The analysis is the following:

•
Operating above the surface (Ψ > 0) requires a negative switching function derivative dΨ dt < 0 to reach the surface (Ψ = 0).The previous analyses are formalized with the following inequalities: The evaluation of those general reachability conditions depends on the value of the transversality condition (28); a positive value of Equation ( 28) indicates a direct relation between the control signal u and derivative dΨ dt , i.e., a positive change on u produces a positive derivative dΨ dt > 0 , and a negative change on u produces a negative derivative dΨ dt < 0 .Instead, a negative value of Equation (28) indicates an inverse relation between u and dΨ dt , i.e., a positive change on u produces a negative derivative dΨ dt < 0 , and a negative change on u produces a positive derivative dΨ dt > 0 .Then, for a positive transversality value (28), the general reachability conditions (29) become: lim Evaluating the previous inequalities with the switching function derivative ( 27) leads to the stability conditions given in inequalities (31) and (32).Those dynamic limitations on di R dt must be fulfilled to ensure the reachability of the desired surface in the case of a positive transversality value.
Instead, for a negative transversality value (28), the reachability conditions are given in Equation (33).Evaluating those inequalities produces the stability conditions given in (34) and (35).lim Finally, the reachability conditions impose a dynamic restriction on the positive and negative changes for i R .Thus, the power system and controller must be designed to achieve the required dynamic response with a stable behavior.This analysis is illustrated in Section 4.3 using an application example.

Equivalent Control
The equivalent control condition evaluates the average value u eq of the control signal u, which must be constrained by the binary values of u, thus (0, 1).In the context of power converters, the average value of u is equal to the duty cycle (13); hence, this equivalent control condition evaluates the non-saturation of the duty cycle: This analysis is performed inside the sliding surface Ψ = 0 ∧ dΨ dt = 0 .Therefore, it ensures that the system remains inside the surface.Replacing the switching function derivative (27) in dΨ dt = 0, and switching u by u eq , leads to the following equivalent control value: Finally, replacing the equivalent value (37) in inequality (36) produces the same dynamic restrictions on i R obtained from the reachability conditions.Therefore, as demonstrated by Sira-Ramirez in [34], fulfilling both the transversality and reachability conditions ensures that the equivalent control condition is also fulfilled; hence, the duty cycle of the converter will not be saturated.

Closed-Loop Dynamics
The next step in the design of the adaptive SMC is calculating the switching function parameter k v .Such a design is performed considering a stable operation of the SMC (25); thus, Since the SMC generates the control signal u, the C 2 voltage can be described using the averaged model given in Equation (17), which results in the following Equation: Taking into account that i R is the output of a high-pass filter acting on the load current, the load transients always end with i R = 0. Therefore, the dynamic behavior of the C 2 voltage is described by the following Equation since Transforming the previous expression to the Laplace domain leads to Equation (40), which describes the closed-loop dynamic behavior of the power system.Since the closed-loop exhibits a first-order dynamic, the settling time of C 2 voltage is given by t s,C2 = 3.9 • τ CL as reported in [35].Therefore, the k v parameter is calculated in terms of the desired settling time using Equation (41), which shows two characteristics; k v is an adaptive value with negative sign, which is important information to finish both the transversality and reachability analyses.

Switching Frequency
The main problem of theoretical SMC is the infinite switching frequency required for the implementation.A classical solution to this problem is to introduce a hysteresis band [−∆Ψ, +∆Ψ] around the sliding surface (Ψ = 0) to limit the switching frequency: In that way, since the closed-loop operation imposes Ψ = 0, the hysteresis band produces the switching function ripple reported in Equation ( 43).The ripple magnitudes ∆i L1 and ∆i L2 were reported in Equations ( 21) and (22), respectively, and the ripple magnitude ∆v C2 was reported in Equation ( 23).Finally, the SMC ensures that i L2 follows the reference i R provided by the high-pass filter.Hence, the subtraction between those two signals is In steady-state operation, k c • i L2 = i L1 , as given in Equation (20), where 43) is equal to zero.Moreover, the analysis reported in Figure 3 shows that the peak value of i L2 occurs when the ripple in v C2 is equal to zero; similarly, the peak value of v C2 occurs when the ripple in i L2 is equal to zero.Therefore, the peak value of the term [−∆i L2 + k v • ∆v C2 ] of Equation (43) occurs at the peak value of i L2 or at the peak value of k v • ∆v C2 , depending on which component has the highest magnitude.This condition is formalized with the following equation for the ripple magnitude of the switching function: Finally, Equation ( 44) is used to design the hysteresis band [−∆Ψ, +∆Ψ] in agreement with the maximum switching frequency F sw supported by the MOSFETs used to construct the Zeta converter.

Design Procedure and Application Example
This section illustrates the design of both the power stage and the SMC to ensure the desired operation of the battery-supporting system.The first characteristic concerns the battery voltage, which is selected as 48 V due to the wide use of such a voltage level in DC loads and microgrids.The second characteristic is the C 2 nominal voltage, which is selected as 48 V to require a nominal duty cycle near 50%; however, any other value can be selected.Concerning the load transients, this example considers fast current changes up to 70 A/ms with magnitudes of 2 A, where the battery will be protected for frequencies higher than 500 Hz; again, any other values can be used depending on the load and battery characteristics.In addition, the maximum deviation of the C 2 voltage must be limited to 3% for 100 ms, thus avoiding a large discharge or overcharge of the capacitor.Finally, the maximum switching frequency is selected as 120 kHz, which is a conservative value for commercial applications.Table 2 summarizes the previous characteristics.

Inductor Design
Taking into account that i L2 (output current of the Zeta converter) provides the highfrequency components of the load current i o , the maximum derivative of i L2 must be enough to supply the maximum derivative of i o : Replacing the derivative magnitude of i L2 given in ( 6) into (45) leads to the following limit for L 2 : Using the values given in Table 2 in inequality (46) produces L 2 < 685.71 µH.However, with such a limit value, the MOSFETs will not switch states during the load transient; hence, to improve the dynamic behavior of the converter, L 2 is selected as half of the limit value, which enables the MOSFETs to produce at least two commutations during a current transient.Then, adjusting to a commercial value, L 2 = 330 µH.Finally, L 1 is set equal to L 2 to balance the current ripple injected into the C 1 capacitor; hence, L 1 = 330 µH.

Capacitors and High-Pass Filter Design
The reference current i R in the switching function (24) is generated by a high-pass filter G hp processing the load current i o .Equation (47) describes the first-order high-pass filter considered in this solution.
The most extreme transient corresponds to a step current i o = ∆i o s , which produces the following time-domain waveform obtained from the inverse Laplace transformation of Equation (47): The charge extracted from C 2 during a positive load transient (increment in i o ) is obtained by integrating the previous time-domain waveform: During a positive load transient, the v C2 voltage is decreased and the voltage deviation is negative, which produces the following charge extraction from C 2 : Finally, C 2 capacitance is obtained by relating Equations ( 49) and (50), as follows: The design of C 1 is performed to provide a balance with the energy stored in C 2 , which is equal to C1 /2, the condition for C 1 to achieve E C 1 = E C 2 is calculated using Equations ( 18) and ( 19), as follows: Evaluating Equation ( 51) with the values given in Table 2 produces a capacitance equal to 442.1 µF, which, adjusted to a commercial value, results in C 2 = 470 µF.Similarly, evaluating Equation (52) produces the commercial value C 1 = 470 µF.

Verification of the SMC Stability
The next step is to evaluate the SMC's stability, which requires verifying the transversality and reachability conditions.Evaluating the transversality value given in Equation ( 28) using the characteristics of Table 2 and the parameters previously calculated produces the average value d du dΨ dt = −2.9× 10 5 ̸ = 0, which confirms the transversality condition (26).Taking into account that the transversality value is negative, the reachability conditions that must be evaluated are inequalities (34) and (35).Evaluating those inequalities with the characteristics of Table 2 and the parameters previously calculated leads to the restrictions −145 A/ms < di R dt < 145 A/ms.Since the reference signal i R is generated by a high-pass filter processing the load current i o , as discussed in Section 4.2, the maximum derivative of i R is the same as that of i o : max di R dt = max di o dt = 70 A/ms.Therefore, the previous calculations confirm that the reachability conditions (33) are fulfilled.It must be noted that, in case of a positive transversality value, inequalities (31) and ( 32) must be evaluated.
In conclusion, the proposed design of both the power stage and SMC ensures a stable operation of the system, which guarantees the desired support for the battery.

SMC Control Law
Since the transversality value is negative, the reachability conditions are defined in (33), which also defines the control law.The reachability condition lim Ψ→0 − dΨ dt u=0 > 0 requires that u = 0 when Ψ < 0, and the reachability condition lim Ψ→0 + dΨ dt u=1 < 0 requires that u = 1 when Ψ > 0. However, the hysteresis band [−∆Ψ, +∆Ψ] introduced in Section 3.5 modifies the limits of Ψ to produce changes on u, which defines the final control law, as follows: Evaluating Equation (44) using the characteristics of Table 2, and the parameters previously calculated, leads to ∆Ψ = 0.3 A.

Summary of the Design and Control Processes
The summary of the design process for the parameters of both the power stage and SMC is synthesized in Algorithm 1.Such a process starts with the design of inductor L 2 to fulfill the maximum load current derivative.To ensure at least two switching periods within the transient, a constant k L ≤ 1/2 is used to fulfill inequality (46), where smaller k L produces higher number of periods per transient, but very small L 2 values will require very small ∆Ψ limits, which could introduce implementation problems due to circuit sensitivity.Therefore, k L must be selected to ensure that ∆Ψ magnitude enables the correct operation of the comparators used to implement the control law (53).Next, L 1 is set equal to L 1 to provide a balance in the current ripple of both inductors.
The capacitor C 2 is designed to limit the voltage deviation up to MO C2 , and C 1 is designed to balance the energy stored in both capacitors.Then, the steady-state values of both the current (k c,ss ) and voltage (k v,ss ) constants are calculated from the nominal values of the application, and both constants are used to calculate the hysteresis band value ∆Ψ.Finally, depending on the application, the high-pass filter is parameterized in agreement with the safe frequency range defined for the battery transients.

Algorithm 1 Design of both the power stage and SMC parameters
Implementing the adaptive controller requires processing, in an infinite loop, a series of calculations based on measurements and fixed parameters.Such a control process is synthesized in Algorithm 2. The algorithm requires the desired reference for the voltage in C 2 and the value of the two inductor currents, both the battery and C 2 voltages, and the load current.The next step is to detect the high-frequency transients on the load current using the high-pass filter.Then, both the current (k c ) and voltage (k v ) gains are adapted for the actual operation condition, and with those values, the switching function Ψ for the operation conditions is calculated.
Using the values of Ψ and ∆Ψ, the control law of the SMC (53) is executed, which produces the binary values for controlling the MOSFETs (u and u).Finally, the loop starts again by measuring the physical variables.

Require
▷ Filter the load current to detect the fast transients 4: ▷ Calculate the adaptive current gain 5: ▷ Calculate the adaptive voltage gain 6: return u, u ▷ u and u are provided to the MOSFETs 17: end loop Table 3 summarizes the circuital parameters calculated for this application example.This table also presents the energy stored in the elements of the Zeta converter needed to support the high-frequency transients of the load current.The table shows that the energy stored in the capacitors C 1 and C 2 is very small.In the case of L 2 , since i L2 is defined by the high-pass filter given in (47), the steady-state value of i L2 is 0 A, and from Equation (20), it is obtained that the steady-state value of i L1 is also 0 A; thus, the inductors do not store energy in the steady state, and they operate only as energy buffers during the transient conditions.Therefore, the total energy stored in the Zeta converter is 0.30 mWh or 0.006 mAh.It must be highlighted that the design of the proposed supporting device (formed by both the Zeta converter and SMC) does not depend on the battery capacity; instead, it only depends on the load transients that must be supported.The battery capacity is related to the load or microgrid operation cycle, which has a low-frequency profile.In contrast, the supporting device capacity only depends on the system's high-frequency transients.

Implementation of the Adaptive SMC and Detailed Circuital Simulations
The power system described in Figure 2 was implemented in the power electronics simulator PSIM using the electrical parameters calculated in the previous section.The adaptive sliding-mode controller can be implemented following Algorithm 2 with analog or digital circuits.The following subsections discuss both implementations.

Analog Implementation of the Adaptive SMC
The implementation of the control algorithm, using analog circuits, is presented in Figure 4.Such a circuit considers the implementation of the high-pass filter using opera-tional amplifiers, as discussed in [36].Similarly, addition, subtraction, and multiplication by a constant value can be easily implemented with operational amplifiers, as reported in [36].The multiplication and division operations can be implemented using analog integrated circuits like the AD734 described in [37].Therefore, the calculation of the adaptive parameters k c and k v , the calculation of the i R signal, and the calculation of the switching function Ψ are easily implemented with analog circuits.
Concerning the control law, the logical operations in Algorithm 2 can be implemented using two comparators and an S-R Flip-Flop, as depicted in Figure 4.When Ψ ≥ +∆Ψ, the signal Set = 1 activates the Set input of the Flip-Flop, which imposes u = 1 and u = 0; similarly, when Ψ ≤ −∆Ψ, the signal Reset = 1 activates the Reset input of the Flip-Flop, which imposes u = 0 and u = 1.Finally, Figure 4 shows a diagram of those control signals.The first simulation of this analog implementation, reported in Figure 5, evaluates the compensation of a load transient from steady state to battery charge with the maximum current derivative di o dt = 70 A/ms.Figure 5a shows two fast current transients between 0 A and 2 A, and in both cases, the Zeta converter provides the fast current component, while the battery exhibits a slow change in the current, thus fulfilling the desired behavior of the system.In addition, the C 2 voltage is constrained to the MO C2 limit for such a transient condition, which validates the design of the converter components.Moreover, since v b = v R , then the average value of k c is near 1 and the stability condition of the inductor currents is i L1 = i L2 , which is confirmed in the simulation.It is observed that the switching function Ψ is permanently trapped inside the hysteresis band [−∆Ψ, +∆Ψ]; thus, the SMC is always inside the sliding mode, which ensures the global stability.Finally, the switching frequency is always below the maximum design limit of 120 kHz.
Figure 5b presents a zoom of the previous simulation, which confirms that the Zeta converter provides the current transient, while the battery current changes with the frequency limit defined by the high-pass filter.In addition, the zoom of the inductor currents confirms the relation imposed by the first part of the switching function and confirms both currents' stable behavior.Finally, the zoom of the switching function Ψ shows the frequency reduction at the perturbation instant, which is caused by the fast change in the load current, where the SMC can impose three switching periods during the transient time.
Figure 6 reports a second simulation, which evaluates the compensation of a load transient from steady state to battery discharge with the same maximum current derivative.Figure 6a shows the correct behavior of both the Zeta converter and battery currents, while C 2 voltage and the inductor currents are regulated as expected.As in the previous case, the switching function is constrained to the hysteresis band, ensuring global stability.In this case, Figure 6b shows a zoom for the second transient (from −2 A to 0 A), where the steady-state values of the Zeta current and the battery current are different.After the transient is finished, the Zeta current becomes zero since the supporting device is designed only to provide fast current transients.Therefore, the Zeta converter provides the step-up fast transient from 0 A to 2 A needed to reach the final current of both the battery and the load (0 A).As in the previous case, the waveforms of Figure 6b confirm the stability of the proposed solution and the correct limitation of the switching frequency.The next simulation, reported in Figure 7a, evaluates the performance of the proposed solution to a sequence of load transients.In this case, the load current changes from 0 A to 14 A with transients of 2 A. As expected, the Zeta converter provides the fast current transients, returning to 0 A for the steady-state condition.Therefore, despite the consistent increment in the battery current, the supporting device (Zeta converter) always provides the same behavior, which prevents the battery from suffering the fast current transients imposed by the load.Since the consecutive transients occur in intervals of 2 ms, which is much shorter than the settling time (t s,C2 = 100 ms), the voltage of C 2 capacitor is reduced up to 40 V, but the SMC always operates inside the sliding surface, thus ensuring global stability and demonstrating the adaptability and robustness to changes on the operation conditions.
Figure 7b presents the fourth simulation, which evaluates the settling time of the C 2 voltage.In this test, a single load current perturbation is applied to charge the battery with a load current equal to −2 A. The simulation confirms that C 2 voltage is below the designed deviation MO C2 for that perturbation, and the voltage compensation is achieved in the designed settling time (100 ms).Therefore, both discharging (positive load transients) and charging (negative load transients) times are predictable and equal to the designed settling time.This satisfactory performance confirms that the switching function operates as expected, thus ensuring the capability of providing or absorbing load current transients to protect the battery.

Digital Implementation of the Adaptive SMC
The proposed SMC can be implemented in a digital microprocessor by coding Algorithm 2 in any supported language.However, such an approach will impose high requirements on the Analog-to-Digital Converters (ADCs) needed to measure the two inductor currents, both the battery and C 2 voltages, and the load current.Since Algorithm 2 produces the control signals u and u, the time resolution for the rising and falling of u (and u) impacts the accuracy of the SMC implementation.Therefore, adopting an acquisition time between 80 and 100 times smaller than the switching period is common, thus providing a resolution for the control signal between 1% and 1.25% of the period.Using such a traditional approach, the implementation of Algorithm 2, for the application characteristics reported in Table 2, will require ADCs with sampling frequencies between 9.6 MSPS (9.6 × 10 6 samples per second) and 12 MSPS, which are very high.
Therefore, this section proposes a modified formulation of the practical sliding surface (42) to reduce the ADC sampling frequency.This new formulation represents the highfrequency signal i L1 of Ψ (24) as a function of the other terms, which results in the following representation of the practical sliding surface −∆Ψ < Ψ < +∆Ψ: Then, using the new Ψ formulation given in (54)-(56), we also obtain a new formulation for the control law (53), as follows: Then, two processes are needed.The first one calculates the limits Ψ L1,Set and Ψ L1,Reset , and the second one uses those limits to calculate the MOSFET signals with Equation (57).Considering that the calculation of Ψ L1,Set and Ψ L1,Reset requires the measurement of multiple analog signals, this process imposes the requirements in the ADC frequency.Instead, the calculations of u and u only require simple comparisons; hence, this section proposes using a microcontroller able to perform both processes.For example, the F28379D Microcontroller reported in [38] has multiple ADC channels, has Digital-to-Analog Converters (DACs), and has a Comparator Subsystem (CMPSS).The CMPSS is based on two analog comparators, which have the negative inputs of the comparators connected to two DAC channels, and the positive inputs of the comparators are connected to a single pin of the F28379D.Therefore, two threads can be designed to run with different sampling periods inside the microcontroller, using the CMPSS to perform the analog comparisons of the new control law given in (57).
The first thread (Thread 1) calculates the comparator inputs Ψ L1,Set and Ψ L1,Reset .Since such a comparison is used in each switching period, the values of Ψ L1,Set and Ψ L1,Reset must be updated at least twice in each period; thus, the sampling frequency must be at minimum double the maximum switching frequency.From Table 2, it is observed that the application example imposes a maximum switching frequency of 120 kHz, and introducing a safety factor of 10%, the sampling frequency needed is 264 kSPS (0.264 MSPS), hence reducing the sampling frequency to 2.2% of the requirement imposed by the traditional digital implementation.Figure 8 illustrates the digital implementation of the control algorithm, where Thread 1 delivers the limits Ψ L1,Set and Ψ L1,Reset to the CMPSS.Figure 8 shows that i L1 is introduced in the CMPSS; hence, an ADC channel is not needed for i L1 .Since the external input of the CMPSS (i L1 ) is connected to the positive inputs of the comparators, the lower comparator correctly produces the reset signal (Reset).In contrast, the upper comparator produces an inverted version of the set signal (Set = 1 − Set).The outputs of the CMPSS are logic signals, which is the main advantage of the structure given in Figure 8, since those logic signals can be captured by the second thread (Thread 2) at the full speed of the microprocessor (200 MHz); hence, the capture frequency is not limited by the conversion time of the ADC.Similarly, the control signal of the MOSFETs (u and u) are logic signals; therefore, executing Thread 2 at 10 MHz or 12 MHz will provide a resolution between 1% and 1.25% of the switching period for both the rising and falling times of u (and u).In fact, executing Thread 2 at the full speed of the F28379D Microprocessor (200 MHz) could improve the resolution of u (and u) to 0.06% of the switching period.

CMPSS Microcontroller
Algorithm 3 reports the pseudocode for Thread 1, which calculates the comparator inputs Ψ L1,Set and Ψ L1,Reset .This algorithm considers the discrete implementation of the high-pass filter given in Equation (58), which is obtained from the analog highpass filter previously reported in Equation (47) by performing the Tustin transformation [39], and subsequently applying the inverse Z-transformation to obtain the difference equation representation of i R(k) .In such an expression, T adq is the ADC sampling time.Therefore, Thread 1 can be executed at 264 kHz for the application example, which ensures an ADC frequency of 264 kSPS (T adq = 3.8 µs).The calculations of Ψ L1,Set and Ψ L1,Reset show that those values are continuous; hence, those signals must be provided to the CMPSS using two DAC channels.The F28379D Microcontroller has DAC channels with minimum conversion times equal to 2 µs; hence, T adq = 3.8 µs can be fulfilled by the on-board DAC.Finally, the values of i R and i o are stored for the next iteration of the algorithm.
▷ High-Pass filter 4: ▷ Calculate the adaptive current gain 5: ▷ Calculate the adaptive voltage gain 6: ▷ Signals for the comparators of the CMPSS 11: end loop Algorithm 4 reports the pseudocode for Thread 2, which produces the control signals for the MOSFETs (u and u); hence, it must be executed between 80 and 100 times the maximum switching frequency.For the application example, 10 MHz was selected.Thread 2 starts by capturing the output signals of the CMPSS (Reset and Set); then, Thread 2 detects if a rising edge on the Reset signal has been produced by the CMPSS.To take into account that the set Set signal produced by the CMPSS is inverted (Set = 1 − Set), Thread 2 detects if a falling edge on the Set signal has been produced.Then, the algorithm changes the MOSFET signals u and u following the new formulation of the control law previously obtained in Equation (57); if no rising edge on Reset or falling edge on Set occurs, then u and u are not changed.The last steps of the algorithm store the states of Reset, Set, u, and u for the next iteration.Figure 9 summarizes the digital implementation, where the processes of both threads are synthesized.In addition, the connection of both threads with the analog CMPSS module is illustrated, which occurs inside the microprocessor to generate the MOSFET control signals.Finally, the figure also illustrates the signal processing of the modified control law adopted for this digital implementation.
end if 13: Calculate the digital filter output iR(k) using (58) Calculate kc(k) using (24)   The digital implementation of the SMC reported in Figure 9 was performed in the power electronics simulator PSIM, as follows.Thread 1 and Thread 2 algorithms were implemented using a C-code block for each thread, and the CMPSS was implemented using two comparators.Thread 1 was executed with a sampling frequency equal to 264 kHz (sampling time equal to 3.8 µs), while Thread 2 was executed with a sampling frequency equal to 10 MHz (sampling time equal to 0.1 µs).
The simulation of this digital implementation, reported in Figure 10, evaluates the compensation of a load transient from steady state to battery charge with the maximum current derivative di o dt = 70 A/ms; hence, it reproduces the conditions considered for the simulation of the analog implementation reported in Figure 5.The new simulation results of Figure 10a show two fast current transients between 0 A and 2 A, where the Zeta converter provides the fast current components, as expected.The stable condition i L1 = i L2 is also confirmed in this simulation, where i L1 is constrained by Ψ L1,Set and Ψ L1,Reset , thus ensuring the global stability of the SMC, as given in inequality (54).In addition, the C 2 voltage is constrained to the MO C2 limit, demonstrating that the SMC's digital implementation provides the same performance of the analog implementation.Finally, the switching frequency is always below the maximum design limit (120 kHz), thus requiring the same MOSFETs used for the analog implementation of the SMC. Figure 10b shows a zoom of this simulation, which confirms that the Zeta converter provides the high-frequency component of the load current transient.The zoom also shows the detail of Ψ L1,Set and Ψ L1,Reset , where the discretization caused by the sampling frequency of Thread 1 (264 kSPS) is observed.This simulation also shows the correct operation of the modified formulation of the sliding surface given in inequality (54), and it reports both the Set and Reset signals generated by the CMPSS, where Set = 1 − Set.Finally, the control signal u generated by Thread 2 is also presented, which agrees with the modified control law.
In summary, the simulations of both the analog and digital implementations of the SMC confirm the correct operation of the power system and the adaptive SMC for any operation condition.Therefore, the proposed solution can supply the current transients imposed by the load, thus forcing the battery to supply only low-frequency components.In addition, it was demonstrated that both analog and digital implementations of the adaptive SMC exhibit equivalent performances; hence, the one more suitable for the particular application can be adopted.

Comparison with a Classical Controller
This subsection presents the design of a cascade structure based on PI controllers to provide a comparison with a classical solution.The first step is to obtain the small-signal model of the power stage as Ẋ ] T is the input vector, A m is the state Jacobian and B m is the input Jacobian.This process is performed by deriving the differential equations given in ( 14)-( 17), as described in [40], obtaining the following Jacobian matrices: The output of the small-signal model is calculated from Y = C m × X + D m × U x , where C m and D m relate the output with the states and the inputs, respectively.The output of the small-signal model is Y = [i L2 ] because i L2 must be regulated to follow the i R value provided by the high-pass filter; hence, C m = [0 1 0 0] and D m = [0 0].
The steady-state values of d, i L1 , i L2 , v C1 and v C2 are calculated from Equations ( 18)-( 20) and replaced into Jacobians (59), and such a numerical small-signal model is introduced into the sisotool function of Matlab to design a PI controller; in [40], such a design is implemented using the classical root-locus technique.The design of that PI controller considers a damping ratio equal to 0.707 and a closed-loop bandwidth equal to F sw /10, which are standard criteria for linearized models; the resulting controller was Finally, this G PI c controller processes the error between i R and i L2 to produce the duty cycle of an additional PWM circuit used to generate the MOSFET signals; Figure 11 shows the structure of this inner current loop.
The v C2 voltage is also regulated with a PI controller named G PI,v .Such a second PI controller processes the error between v C2 and the reference v R to produce the additional changes on i L2 needed to regulate v C2 with the desired settling time.This cascade controller requires a closed-loop model of the inner current loop.Equation ( 17) describes the dynamic behavior of v C2 with respect to the inductor currents, where the inner current loop guarantees the current relation given in Equation (20); hence, the resulting closed-loop model is given in both time domain (60) and Laplace domain (61).
The design of the voltage PI controller (G PI,v ) was performed using Equation (61) for a unitary damping ratio to avoid any voltage oscillation and to request a slow current profile to the battery, thus avoiding high-frequency transients.In addition, the controller was designed to impose the desired settling time t s,C2 = 100 ms, which results in the controller G PI,v = −0.055•(s+29.412)s designed with the sisotool function of Matlab.The control structure of Figure 11 was implemented in PSIM, and the performances of both the classical solution (cascade PI structure) and proposed SMC were contrasted.Figure 12 shows the circuital simulation of both solutions, where the proposed SMC (right side) imposes the desired low-frequency behavior i LP = i o − i R on the battery current; instead, the cascade PI structure (left side) introduces an undesired high-frequency transient to the battery current.This undesired behavior is caused by the tracking error of G PI,c observed in i L2 for the cascade PI structure, which is the result of the bandwidth limitation introduced in the linearization process; moreover, i L2 also exhibits an overshoot caused by the change on the operation point.Instead, the proposed SMC forces i L2 to track i R with null error, thus ensuring the desired low-frequency behavior of the battery current.
Figure 12 also presents, in the bottom waveforms, the behavior of v C2 for both controllers.The v C2 waveform imposed by the proposed SMC has the desired MO C2 and t s,C2 without any overshoot, thus requesting a low-frequency current in the battery in order to restore the energy in C 2 .Instead, the G PI,v controller from the cascade PI structure, despite being designed with a unitary damping ratio, cannot avoid the voltage overshoot.In addition, G PI,v imposes a higher derivative, thus requiring faster changes to the battery current, which is an undesired battery condition.
The analog implementation of the cascade PI structure requires two adders, two PI controllers formed by two integrators, two gains and two adders, and a PWM circuit formed by a comparator, a triangular waveform generator and an adder.The analog implementation of the proposed SMC, depicted in Figure 4, requires four adders, two dividers, a multiplier, and a gain; the SMC control circuit is formed by two comparators and an S-R flip-flop.Therefore, the proposed SMC requires integrated circuits for multiplication and division operations, while the cascade PI structure requires analog integrators.Thus, the analog implementation complexity of both controllers is similar.The digital implementation of the cascade PI structure also requires two threads, one for the inner current loop and another for the voltage loop.In addition, a complementary PWM peripheral must be used to produce both control signals.Hence, it has a complexity similar to the digital implementation of the proposed SMC reported in Figure 8.
In conclusion, the proposed SMC performs better than a classical solution based on cascade PI controllers.This performance is observed in the tracking efficiency that ensures i L2 = i R , which imposes the desired low-frequency performance in the battery.Finally, the implementation complexity of both solutions is similar since both control solutions can be implemented using a few integrated circuits.

Conclusions
This paper presented an algorithm for designing both the power and control stages of a HESS based on a Zeta converter, a battery, and a capacitor.The designed adaptive sliding-mode controller, which can be implemented on a low-cost platform, guarantees a safe battery current, which prevents distortion of the DC bus voltage waveform and avoids high-frequency transients that could reduce the battery's lifespan.Moreover, the implementation of the adaptive sliding-mode controller is presented in detail using analog and digital circuits.An application example, where the battery was both charged and discharged, confirmed that during fast current transients, the Zeta converter provided the fast current components, while the battery responded with slow current derivatives.In addition, the switching function remained within the hysteresis band, ensuring the global stability of the adaptive sliding-mode controller.Finally, a comparison with a classical cascade PI structure demonstrated that the proposed adaptive controller provided superior performance, as evidenced by the tracking efficiency, which ensures that the inductor current matches the reference current, thus imposing the desired low-frequency performance on the battery.Funding: This research was funded by Instituto Tecnológico Metropolitano, Universidad Nacional de Colombia, Universidad del Valle, and Minciencias-Ministerio de Ciencia Tecnología e Innovación of Colombia under project "Estrategias de dimensionamiento, planeación y gestión inteligente de energía a partir de la integración y la optimización de las fuentes no convencionales, los sistemas de almacenamiento y cargas eléctricas, que permitan la generación de soluciones energéticas confiables para los territorios urbanos y rurales de Colombia", with Minciencias code 71148, inside the research program RC80740-178-2021, Hermes code 46771, and Sicop code CI21154.

Figure 1 .
Figure 1.Structure of the hybrid energy storage system.

Figure 2 .
Figure 2. Zeta power system designed to support battery transients.

Figure 4 .
Figure 4. Analog implementation of the control algorithm.

Figure 8 .
Figure 8. Digital implementation of the control algorithm.

Figure 9 .
Figure 9. Flowchart of the digital implementation.

Figure 10 .
Figure 10.Response of the digital implementation to fast load transients.

Figure 12 .
Figure 12.Comparison with a cascade PI structure.

Table 1 .
Characteristics of some works on HESS.

Table 2 .
Characteristics of the application example.

Table 3 .
Circuital parameters of the application example.