Highly Reliable Ovonic Threshold Switch with TiN/GeTe/TiN Structure

A new architecture has become necessary owing to the power consumption and latency problems of the von Neumann architecture. A neuromorphic memory system is a promising candidate for the new system as it has the potential to process large amounts of digital information. A crossbar array (CA), which consists of a selector and a resistor, is the basic building block for the new system. Despite the excellent prospects of crossbar arrays, the biggest obstacle for them is sneak current, which can cause a misreading between the adjacent memory cells, thus resulting in a misoperation in the arrays. The chalcogenide-based ovonic threshold switch (OTS) is a powerful selector with highly nonlinear I–V characteristics that can be used to address the sneak current problem. In this study, we evaluated the electrical characteristics of an OTS with a TiN/GeTe/TiN structure. This device shows nonlinear DC I–V characteristics, an excellent endurance of up to 109 in the burst read measurement, and a stable threshold voltage below 15 mV/dec. In addition, at temperatures below 300 °C, the device exhibits good thermal stability and retains an amorphous structure, which is a strong indication of the aforementioned electrical characteristics.


Introduction
The success of today's computing systems is due to the von Neumann architecture, whose design involves moving data back and forth between the processor and the memory. There are two major reasons for the success of this architecture. The first one is its Turing completeness, which means that, given a sufficient amount of memory and time, it can complete any mathematical task. The second one is its scalability, which makes it possible to expand the memory. As the amount of data increases, the computation speed also increases. There is no need to modify the architecture or the associated programming model [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. However, this data transfer system accounts for a large part of the power consumed. Even though the next-generation computer systems can perform exascale (10 18 ) calculations per second, enabling them to deal with complex data, they will consume about 30 MW of power when using the von Neumann architecture. Furthermore, the von Neumann system suffers from latency owing to the huge amount of data transfer between the separate memory unit and logic unit [16,17]. This problem resulted in the development of a neuromorphic computing system, which is inspired by the biological neural system and has a much lower power consumption than that of conventional processors. This new computing system has the potential to process large amounts of digital information and can be used for natural language processing, driving automation, and big data analysis.
A crossbar array (CA) is the basic building block of the neuromorphic system; it is composed of a memory and a selector. The memory acts as a synaptic weight for storing information and processing of input signals. Among the candidates for the memory, resistive random-access memory (RRAM) is the most promising one because of its high capacity, multilevel programming, high speed, and scalability down to the 4F 2 design rule.
In this study, we investigated an OTS device, namely, GeTe (GT), which has shown excellent thermal stability and electrical endurance characteristic.

Materials and Methods
Device Fabrication: Figure 1a shows a schematic diagram of the top electrode (TE) TiN/OTS (GT)/bottom electrode (BE) TiN structure. A heavily doped P-type Si wafer (ρ < 0.01 Ωcm) and a thermally oxidized SiO2 wafer with a dimension of 300 nm were used as the substrates. The BE was patterned using an inductively coupled plasma-reactive ion etching method after depositing the TiN with a physical vapor deposition system. A radio frequency (RF) sputtering system with a Ge-Te (1:1) target was used to deposit the GT layers. The basal vacuum pressure in the chamber was set to less than 1.0 × 10 −6 Torr, and the working pressure of the Ar gas (purity of 99.999%) and RF power were maintained at 2.0 × 10 −3 Torr and 50 W, respectively, during sputtering. Before the deposition, pre-sputtering was performed for 30 min to eliminate any contaminants on the target. After the deposition of the GT layers, TE TiN was deposited and patterned using the lift-off method. Figure 1b shows a top-view image of the device.
Materials Analysis: The samples for material analysis were prepared simultaneously for the GT device on the SiO2/Si substrate. The sample for the high-resolution transmission electron microscopy (HR-TEM) analysis was prepared by a focused ion beam operation (FIB (Leeuwarden, The Netherlands), Helios NanoLab™ (Sarasota, FL, USA), FEI (Hillsboro, OR, USA)). HR-TEM (Tecnai G2 F30 S-TWIN, FEI) analysis was then performed to obtain a cross-sectional view of the Si/SiO2/TiN/GeT/TiN stacked device.
Electrical Measurements: The electrical characteristics of the device were measured using an HP4145B semiconductor parameter analyzer (SPA) in the DC I-V sweep mode. The temperature was controlled by a hot-stage microscope using a temperature controller. Pulse-based electrical measurements were conducted using the HP4145B, an arbitrary function generator (Agilent 81150 A, Santa Clara, CA, USA), an oscilloscope (MSOX3024T, Tektronix, Beaverton, OR, USA), and an electromechanical RF electrical circuit switch box. A radio frequency (RF) sputtering system with a Ge-Te (1:1) target was used to deposit the GT layers. The basal vacuum pressure in the chamber was set to less than 1.0 × 10 −6 Torr, and the working pressure of the Ar gas (purity of 99.999%) and RF power were maintained at 2.0 × 10 −3 Torr and 50 W, respectively, during sputtering. Before the deposition, presputtering was performed for 30 min to eliminate any contaminants on the target. After the deposition of the GT layers, TE TiN was deposited and patterned using the lift-off method. Figure 1b shows a top-view image of the device.
Materials Analysis: The samples for material analysis were prepared simultaneously for the GT device on the SiO 2 /Si substrate. The sample for the high-resolution transmission electron microscopy (HR-TEM) analysis was prepared by a focused ion beam operation (FIB (Leeuwarden, The Netherlands), Helios NanoLab™ (Sarasota, FL, USA), FEI (Hillsboro, OR, USA)). HR-TEM (Tecnai G2 F30 S-TWIN, FEI) analysis was then performed to obtain a cross-sectional view of the Si/SiO 2 /TiN/GeT/TiN stacked device.
Electrical Measurements: The electrical characteristics of the device were measured using an HP4145B semiconductor parameter analyzer (SPA) in the DC I-V sweep mode. The temperature was controlled by a hot-stage microscope using a temperature controller. Pulse-based electrical measurements were conducted using the HP4145B, an arbitrary function generator (Agilent 81150 A, Santa Clara, CA, USA), an oscilloscope (MSOX3024T, Tektronix, Beaverton, OR, USA), and an electromechanical RF electrical circuit switch box. Throughout the measurement process, the voltage was biased to the TiN TE, while the TiN BE was electrically grounded. The resistance (or current) values of the programming and erasure were verified at 2 V using the SPA. These two types of electrical circuits were alternately used by the electromechanical RF electrical circuit switch boxes. All the electrical measurements were performed using a LabVIEW-based control program. Figure 2a shows the DC I-V characteristic curves of the TiN/OTS (GT)/TiN device, which were measured by applying a DC bias. We set the compliance current to prevent a dielectric breakdown of the device. The black lines in the positive bias region and the red lines in the negative bias region were the results of the measurement under a current compliance of 500 µA. Moreover, the blue line is the characteristic under the bias of an external 1-kΩ load resistor. We found that the threshold voltage (Vth) of this device was under 0.5 V during the forward voltage sweep. At Vth, the OTS device maintained a high resistance state (off state), and the current increased abruptly (on state). During the backward sweep, the on state returned to the off state again. Throughout the measurement process, the voltage was biased to the TiN TE, while the TiN BE was electrically grounded. The resistance (or current) values of the programming and erasure were verified at 2 V using the SPA. These two types of electrical circuits were alternately used by the electromechanical RF electrical circuit switch boxes. All the electrical measurements were performed using a LabVIEW-based control program.

Figure 2a
shows the DC I-V characteristic curves of the TiN/OTS (GT)/TiN device, which were measured by applying a DC bias. We set the compliance current to prevent a dielectric breakdown of the device. The black lines in the positive bias region and the red lines in the negative bias region were the results of the measurement under a current compliance of 500 μA. Moreover, the blue line is the characteristic under the bias of an external 1-kΩ load resistor. We found that the threshold voltage (Vth) of this device was under 0.5 V during the forward voltage sweep. At Vth, the OTS device maintained a high resistance state (off state), and the current increased abruptly (on state). During the backward sweep, the on state returned to the off state again. The OTS device exhibited identical values of Vth. Considering that typical OTS devices generally have different Vth values, our OTS device shows special features and, thus, should be investigated further [28,29]. In the results of the study, Valea, A. et al., it The OTS device exhibited identical values of Vth. Considering that typical OTS devices generally have different Vth values, our OTS device shows special features and, thus, should be investigated further [28,29]. In the results of the study, Valea, A. et al., it can be confirmed that the Vth is 1.4 V, which is different from the Vth (0.5 V) of our OTS device. In addition, the results of studies by Laguna, C. et al. also show that Vth is different from ours. Figure 2b shows the pulse-based current voltage (PIV) characteristics of the device with different external load resistors. Here, the pulse is ISPP (Incremental step pulse programming), and a method of measuring while continuously increasing the amplitude value in the same pulse width state is applied. During the PIV measurement, a series of pulses with different voltages was applied, and the resistance value of each step was measured using an oscilloscope. To prevent the device from breakdown during AC measurement, we set the external load resistance from 1 kΩ to 5 kΩ to check for breakdown voltage, which did not occur. As the external resistance approaches zero, more current flows through the element. Therefore, the pulse width was changed from 10 ns to 100 ns at a fixed external load of 1 kΩ to determine the minimum pulse width for proper operation of the device, as shown in Figure 2c.
The OTS is not used alone but is connected in series to the RRAM in the CA. The most important role of the OTS is to prevent a sneak current during a read operation. The leakage paths through unselected cells in the CA can lead to an inaccurate output signal and clear identification of the high-resistance state from the low-resistance state of the RRAM cell. Figure 2 shows the nonlinear characteristics of the OTS, which can suppress sneak current and thus improve the read margin of the CA. Figure 3a shows the Vth change with different pulse widths. We changed the pulse widths from 10 ns to 10 µs and checked the Vth value of each state, which showed little change. It has excellent stability, and the result has significance for CA applications. Because the OTS is part of the 1 Selector-1 Resistance (1S1R) CA, how the RRAM works is very important. Therefore, the operating voltage of the memristor affects the operation of the selector. The maximum operating voltage of the memristor that the selector can operate is up to 3 V. However, if the voltage is greater than 3 V, breakdown may occur in the initial cycle, so the lower the voltage, the better. The current trend for increasing the memory density is by using multi-bit operation, which is a very effective way to store more information in a single device. For the RRAM, multi-bit resistive switching has been reported in previous studies by setting the current compliance, changing the reset voltage, and modulating the voltage pulse amplitude or height. Among those studies, Alamgir et al. reported the feasibility of the multi-bit operation of the RRAM by modulating the pulse width [39][40][41]. They demonstrated this possibility by changing the pulse width without any overlapping of the resistance levels. If the OTS is serially connected to the RRAM, the crucial role of the OTS is to maintain Vth while voltages of different pulse widths are applied to the cell. Figure 3b shows the Vth shift with delay time.
After the OTS was turned on, the values of Vth were measured at different times on a log scale to check whether the OTS maintained its initial value. The OTS endurance was measured because the reliability of the OTS is a key issue that can affect the performance and accuracy of a large-scale cell array. The burst read endurance was measured, as shown in Figure 3c. In contrast to nonvolatile memory, such as the RRAM, the OTS is a volatile device. The burst read scheme differs from the conventional one, which repeats the write/read operation. After 10 to n numbers of pulses were applied to the OTS cell, the OTS resistance was determined. Through this method, we can reduce the read damage using the conventional read scheme. Figure 3d shows a comparison of the PIV results before and after the endurance test. Robust OTS characteristics showed good switching characteristics after 10 9 cycles of the endurance test. From the results, we can confirm the robust endurance of the OTS cell.
To confirm the thermal stability, we performed an XRF analysis on the different components of the GT samples. A quantitative analysis of the Ge and Te of the compounds was performed every 50 • C after 200 • C. As shown in Figure 4a-c, the quantity of Te dramatically decreases after 350 • C, and the rate of decrease of Te is higher than that of Ge at 400 • C.
We performed an HR-TEM analysis for the direct observation of the GT thin film. Figure 5a shows a cross-sectional view of a TiN/GT/TiN structure before annealing the GT layer. Figure 5c shows a cross-sectional view of the same structure after 400 • C annealed. We analyzed the diffraction pattern in the blue dotted-ray rectangular region visible in the GT layer according to the fast Fourier transform (FFT) method. Figure 5b shows the diffraction pattern in the GT layer before annealing, and Figure 5d shows the pattern after 400 • C annealing. The FFT results of the GT layer before annealing showed amorphous characteristics, as illustrated in Figure 5b, and crystalline Te could be observed in the GT layer after annealing. This indicates that GT loses its amorphous properties at this temperature.
The biggest advantage of the OTS is its highly nonlinear current flow (in the DC I-V characteristic), which plays a crucial role in preventing sneak current in the 1S1R cell array structure, as mentioned earlier. In particular, the endurance of the OTS in pulse-based operations must be greater than that of the resistor because the OTS is turned on for every programming and reading event. The amorphous structure of the OTS is responsible for this endurance, which offers electronic trap sites between the conduction band and the Fermi level. Trapping and de-trapping by the external electric field can cause high nonlinearity.
To investigate the composition of the device, we performed a transmission electron microscopy (TEM)/energy dispersive X-ray spectroscopy (EDS) analysis on the sample. Figure 6a shows a cross-sectional image of the TiN/GT/TiN device obtained by TEM analysis, and Figure 6b illustrates the results of the EDS analysis of the cross-section of the device. We can confirm that Te and Ge coexist between the bottom and top TiN layers. Figure 6c shows the map sum spectrum of the sample. The elements and atomic ratios of the TiN/GT/TiN device are shown in Table 1. . The burst read scheme differs from the conventional one, which repeats the write/read operation. The resistance of the OTS was determined after 10 to n numbers of pulses were applied to the OTS cell. (d) Comparison of the PIV results before and after the endurance test. We found robust OTS characteristics, which show good switching characteristics after 10 9 cycles of the endurance test.
After the OTS was turned on, the values of Vth were measured at different times on a log scale to check whether the OTS maintained its initial value. The OTS endurance was measured because the reliability of the OTS is a key issue that can affect the performance and accuracy of a large-scale cell array. The burst read endurance was measured, as shown in Figure 3c. In contrast to nonvolatile memory, such as the RRAM, the OTS is a volatile device. The burst read scheme differs from the conventional one, which repeats the write/read operation. After 10 to n numbers of pulses were applied to the OTS cell, the OTS resistance was determined. Through this method, we can reduce the read damage using the conventional read scheme. Figure 3d shows a comparison of the PIV results . The burst read scheme differs from the conventional one, which repeats the write/read operation. The resistance of the OTS was determined after 10 to n numbers of pulses were applied to the OTS cell. (d) Comparison of the PIV results before and after the endurance test. We found robust OTS characteristics, which show good switching characteristics after 10 9 cycles of the endurance test.  We performed an HR-TEM analysis for the direct observation of the GT thin film. Figure 5a shows a cross-sectional view of a TiN/GT/TiN structure before annealing the GT layer. Figure 5c shows a cross-sectional view of the same structure after 400 °C annealed. We analyzed the diffraction pattern in the blue dotted-ray rectangular region visible in the GT layer according to the fast Fourier transform (FFT) method. Figure 5b shows the diffraction pattern in the GT layer before annealing, and Figure 5d shows the pattern after 400 °C annealing. The FFT results of the GT layer before annealing showed amorphous characteristics, as illustrated in Figure 5b, and crystalline Te could be observed in the GT layer after annealing. This indicates that GT loses its amorphous properties at this temperature. The biggest advantage of the OTS is its highly nonlinear current flow (in the DC I-V characteristic), which plays a crucial role in preventing sneak current in the 1S1R cell array structure, as mentioned earlier. In particular, the endurance of the OTS in pulse-based operations must be greater than that of the resistor because the OTS is turned on for every programming and reading event. The amorphous structure of the OTS is responsible for this endurance, which offers electronic trap sites between the conduction band and the Fermi level. Trapping

Conclusions
In summary, in this study, the electrical characteristics of an OTS with a TiN/GT/ TiN structure were investigated. This device shows nonlinear DC I-V characteristics and excellent endurance of up to 10 9 in the burst read measurement. Considering that the OTS is turned on for every programming and reading event, the endurance of the OTS must be greater than that of the resistor, and the device meets this requirement. In addition, the device exhibited a stable threshold voltage below 15 mV/dec. The thermal stability indicates a stable thermal property below 300 °C. The thermal stability above this temperature requires further study. Moreover, the device retains an amorphous structure below 300 °C, which is a strong indication of the aforementioned electrical characteristics.

Conclusions
In summary, in this study, the electrical characteristics of an OTS with a TiN/GT/TiN structure were investigated. This device shows nonlinear DC I-V characteristics and excellent endurance of up to 10 9 in the burst read measurement. Considering that the OTS is turned on for every programming and reading event, the endurance of the OTS must be greater than that of the resistor, and the device meets this requirement. In addition, the device exhibited a stable threshold voltage below 15 mV/dec. The thermal stability indicates a stable thermal property below 300 • C. The thermal stability above this temperature requires further study. Moreover, the device retains an amorphous structure below 300 • C, which is a strong indication of the aforementioned electrical characteristics.