The Effect of Gate Work Function and Electrode Gap on Wide Band-Gap Sn-Doped α-Ga2O3 Metal–Semiconductor Field-Effect Transistors

We present technology computer aided design (TCAD) results for wide band-gap Sn-doped α-Ga2O3 metal–semiconductor field-effect transistors (MESFETs). In particular, the effect of gate work function and electrode gap length on the electrical characteristics is demonstrated for a thorough understanding of the behavior of such devices. The gate work function significantly affects the reverse bias drain current under the gate-current dominant regime, whereas a gate-source/drain gap larger than 0.1 µm has a negligible effect on the drain current.

Conventionally, β-Ga 2 O 3 has been grown via molecular beam epitaxy [1,2] on a β-Ga 2 O 3 substrate grown from the melt [9]. However, it is difficult to produce a β-Ga 2 O 3 wafer with a diameter large enough for practical application due to easy formation of cleavages such that the wafer size is limited to four inches [9]. Recently, mist chemical vapor deposition (Mist-CVD) has been introduced as a non-vacuum solution-process heteroepitaxy for α-Ga 2 O 3 on mass-produced sapphire (Al 2 O 3 ) wafers up to six inches, with a similar a crystal structure to α-Ga 2 O 3 [10][11][12][13][14]. Being able to lift α-Ga 2 O 3 off of the sapphire substrate and bond it to other substrates with high thermal conductivity (such as SiC, AlN, diamond, etc.) provides an additional advantage in high power switching and RF applications over β-Ga 2 O 3 with a low thermal conductivity [9]. Despite these promising results on the epitaxial growth of α-Ga 2 O 3 on sapphire, there are few demonstrations of electronic devices based on α-Ga 2 O 3 [15][16][17].
A high-quality Silver oxide AgO x Schottky contact was incorporated into Sn-doped α-Ga 2 O 3 metal-semiconductor field-effect transistors (MESFET) [16] in order to achieve high rectifying Schottky contact at the gate-semiconductor interface. The use of the nonmetallic gate electrode for the α-Ga 2 O 3 MESFET enables the formation of the gate electrode and the metallic source/drain contact at the same plane (i.e., a coplanar configuration). In 2019, an in-depth experimental study on the oxidized metal Schottky contacts (of which the metallic gate electrode for the α-Ga2O3 MESFET enables the formation of the gate electrode and the metallic source/drain contact at the same plane (i.e., a coplanar configuration). In 2019, an in-depth experimental study on the oxidized metal Schottky contacts (of which the work function ranges from 4.70 to 5.80 eV) including AgOx, on β-Ga2O3 was reported [18]. However, a similar work on the oxidized metal Schottky contacts on α-Ga2O3 has not been reported yet. Therefore, the design strategy for optimal operation is lacking.
In this study, we begin by conducting a study on the effect of the gate work function on the electrical characteristics of wide band-gap Sn-doped α-Ga2O3 MESFET for a broad range of the work function, from 4.40 to 5.80 eV. The optimal gate work function found thusly will be applied while varying the source/drain-gate gap length between 0.1 to 2.0 µm. Electrical characteristics issued from these parameters will then be discussed, deepening our knowledge of the optimal configuration of such a device.

Metal-Semiconductor Field-Effect Transistor (MESFET)
A metal-semiconductor field-effect transistor (MESFET) consists of a substrate, a semiconductor layer, the gate electrode (G), and the source (S) and drain (D) electrodes ( Figure 1). For a coplanar structure, the channel length L is defined as the distance between the S and D electrode; hence, L = LG + 2 × Lgap, where LG is the gate length and Lgap is the gap between the S/D electrode and the G electrode. The channel width is denoted by W. The thickness of the semiconductor layer is denoted by ds. The energy structure of an n-type MESFET is determined by the conduction and the valence band edge level, EC and EV; the total density of states for the conduction and valence band of the semiconductor, NC and NV; the donor level, ED; the total density of states for donor ND of the n-type dopant; and the work function of S/D and G, WS/D and WG, respectively. The dielectric constant εs, electron and hole mobility, respectively μe and μh, and electron effective mass, me, describe the electrical properties of the semiconductor.
A complete list of parameters used for the simulation is provided in Table 1. The values correspond to the Sn-doped α-Ga2O3 MESFET with Ti as the S/D electrodes and AgOx as the gate electrode. α-Ga2O3 is amenable to n-type doping by Sn as well [10,19,20], which enhances the free electron concentration and hence the mobility, and facilitates charge carrier injection at the source/drain. The values for ED and ND were taken from [16]. The typical value and the range of WG were determined considering the reported values in [18,21]. The value for WS/D was taken from [22]. Note that edge dislocation could present in the α-Ga2O3 epitaxy layer, around 10 7 (epitaxial lateral overgrowth) ~ 10 10 cm −2 (Mist-CVD), depending on the deposition methods [9], which lowers electron mobility, i.e., 1.3 The energy structure of an n-type MESFET is determined by the conduction and the valence band edge level, E C and E V ; the total density of states for the conduction and valence band of the semiconductor, N C and N V ; the donor level, E D ; the total density of states for donor N D of the n-type dopant; and the work function of S/D and G, W S/D and W G , respectively. The dielectric constant ε s , electron and hole mobility, respectively µ e and µ h , and electron effective mass, m e , describe the electrical properties of the semiconductor.
A complete list of parameters used for the simulation is provided in Table 1. The values correspond to the Sn-doped α-Ga 2 O 3 MESFET with Ti as the S/D electrodes and AgO x as the gate electrode. α-Ga 2 O 3 is amenable to n-type doping by Sn as well [10,19,20], which enhances the free electron concentration and hence the mobility, and facilitates charge carrier injection at the source/drain. The values for E D and N D were taken from [16]. The typical value and the range of W G were determined considering the reported values in [18,21]. The value for W S/D was taken from [22]. Note that edge dislocation could present in the α-Ga 2 O 3 epitaxy layer, around 10 7 (epitaxial lateral overgrowth)~10 10 cm −2 (Mist-CVD), depending on the deposition methods [9], which lowers electron mobility, i.e., 1.3 cm 2 V −1 s −1 for high edge dislocation density [5,15,23] and 24 cm 2 V −1 s −1 for low edge dislocation density [24] compared to the theoretical value 300 cm 2 V −1 s −1 . In this study, the effect of dislocation is considered by carrier mobility. Although there is a lack of study on the effect of defects at the interface between α-Ga 2 O 3 and metal/oxidized metal, for oxide semiconductors the most likely defects are oxygen vacancies, V O , formed by chemical reactions during metal deposition [25,26]. The number of V O is smaller at the semiconductor-oxidized metal interface compared to the semiconductor-metal interface because of the oxygen-rich deposition conditions for oxidized metal layer [18], which is likely to prevent Fermi level pinning by V O . Therefore, in this study, the effect of Fermi level pinning is not considered at the semiconductorgate interface.

Numerical Simulation
The numerical simulation of MESFET resolves the coupled drift-diffusion current equation and the Poisson's equation to obtain the current-voltage characteristics and the current density, charge carrier, and potential distribution. We adopted TCAD software Atlas from Silvaco, Santa Clara, CA, USA. [27]. It is an advantage of numerical simulation that the work function can be varied without altering other physical parameters, which is difficult to achieve experimentally. We considered the Schottky barrier lowering and tunneling models computed by Wentzel-Kramers-Brillouin approximation [28] at both the source/drain-semiconductor and the gate-semiconductor junction. This allows description of the charge carrier injection at the Schottky junction with a large injection barrier.
In order to investigate the effect of the gate work function, W G , we varied the latter from 4.4 to 5.8 eV by 0.2 eV while fixing the source/drain-gate gap to 1.0 µm and the gate length to 8.0 µm. Then, in order to investigate the effect of the source/drain-gate gap, L gap , L gap was varied as 0.1, 0.2, 0.5, 1.0, and 2.0 µm. Concomitantly, the gate length changed accordingly, as 9.8, 9.6, 9.0, 8.0, and 6.0 µm, as the channel length L was fixed to 10 µm. The gate work function W G for the second simulation set was fixed at 5.4 eV.

Effect of Gate Work Function Variation on Sn-Doped α-Ga 2 O 3 Metal-Semiconductor
Field-Effect Transistors 3.1.1. Current-Voltage (I-V) Characteristics Figure 2 shows the simulated current-voltage (I-V) characteristics of MESFETs with various gate work functions. The gate current I G and drain current I D are plotted as a function of the gate-source voltage V GS . When V GS is larger than the on voltage, V on , and smaller than a certain voltage (~7 V, which is similar to the drain-source, V DS ), V on < V GS V DS and I D dominates over I G . When V GS V DS , I G dominates over I D because the drain-gate diode is now forward biased. When V GS is smaller than the on voltage V on , I G is a dominant factor.  Figure 2 shows the simulated current-voltage (I-V) characteristics of MESFETs with various gate work functions. The gate current IG and drain current ID are plotted as a function of the gate-source voltage VGS. When VGS is larger than the on voltage, Von, and smaller than a certain voltage (~7 V, which is similar to the drain-source, VDS), Von < VGS ⪅ VDS and ID dominates over IG. When VGS ⪆ VDS, IG dominates over ID because the draingate diode is now forward biased. When VGS is smaller than the on voltage Von, IG is a dominant factor. The on-off ratio, defined as the ratio of ID at VGS = 7 V to that at VGS = −7 V, increases as the gate Fermi level is lowered. When WG ≤ 5.0 eV, the drain current ID under the IGdominant regime becomes comparable and even larger than that under the normaloperation regime. Therefore, the device could not be used as a switching element. When WG > 5.0 eV, the on-off ratio is around 10 1 ~ 10 7 , showing good rectification behavior. In summary, the degree of electron injection into the gate electrode on the drain side, as will be shown in the following sections, determines the level of off-current, and hence the onoff ratio of the transistor.

Current-Voltage (I-V) Characteristics
In addition, Von should be as close as possible to 0 V to guarantee functional transistor behavior. Thus, a gate work function of WG = 5.4 eV is the optimal condition. This condition was used to analyze the effect of the source/drain-gate gap Lgap. Figure 3a,b provides direct evidence that the current flows into the gate electrode under the IG-dominant regime and the off regime. In particular, the current density is high The on-off ratio, defined as the ratio of I D at V GS = 7 V to that at V GS = −7 V, increases as the gate Fermi level is lowered. When W G ≤ 5.0 eV, the drain current I D under the I G -dominant regime becomes comparable and even larger than that under the normaloperation regime. Therefore, the device could not be used as a switching element. When W G > 5.0 eV, the on-off ratio is around 10 1~1 0 7 , showing good rectification behavior. In summary, the degree of electron injection into the gate electrode on the drain side, as will be shown in the following sections, determines the level of off-current, and hence the on-off ratio of the transistor.

Current Density Distribution and Vector
In addition, V on should be as close as possible to 0 V to guarantee functional transistor behavior. Thus, a gate work function of W G = 5.4 eV is the optimal condition. This condition was used to analyze the effect of the source/drain-gate gap L gap . at the edge of gate on the drain side (black boxes). On the other hand, the current flows out from the gate electrode ( Figure 3c). The current coming from the drain joins that coming from the gate, and flows into the source, which establishes the current path of the device under the normal-operation regime.

Carrier Concentration and Potential Distribution
The semiconductor under the gate electrode is fully or partially depleted, whereas the semiconductor under the source/drain-gate gap is accumulated and the charge carrier concentration is high (n ~ 10 17 cm −3 ) (Figure 4a-c). In addition, the potential difference is −7 V between G and S and −14 V between G and D (under the IG-dominant regime, Figure  4d), and 0 V between G and S and −7 V between G and D (under the off regime, Figure  4e). Thus, the current flows into the gate under the IG-dominant regime and the off regime.

Carrier Concentration and Potential Distribution
The semiconductor under the gate electrode is fully or partially depleted, whereas the semiconductor under the source/drain-gate gap is accumulated and the charge carrier concentration is high (n~10 17 cm −3 ) (Figure 4a-c). In addition, the potential difference is −7 V between G and S and −14 V between G and D (under the I G -dominant regime, Figure 4d), and 0 V between G and S and −7 V between G and D (under the off regime, Figure 4e). Thus, the current flows into the gate under the I G -dominant regime and the off regime. at the edge of gate on the drain side (black boxes). On the other hand, the current flows out from the gate electrode (Figure 3c). The current coming from the drain joins that coming from the gate, and flows into the source, which establishes the current path of the device under the normal-operation regime.

Carrier Concentration and Potential Distribution
The semiconductor under the gate electrode is fully or partially depleted, whereas the semiconductor under the source/drain-gate gap is accumulated and the charge carrier concentration is high (n ~ 10 17 cm −3 ) (Figure 4a-c). In addition, the potential difference is −7 V between G and S and −14 V between G and D (under the IG-dominant regime, Figure  4d), and 0 V between G and S and −7 V between G and D (under the off regime, Figure  4e). Thus, the current flows into the gate under the IG-dominant regime and the off regime.

Current-Voltage (I-V) Characteristics
In general, the current-voltage characteristics for all cases of L gap between 0.1 to 2.0 µm (shown in Figure 5) feature the typical I-V characteristics of MESFET, with a greater I D compared to I G when V GS is higher than V on and a greater I G compared to I D when V GS is lower than V on .

Current-Voltage (I-V) Characteristics
In general, the current-voltage characteristics for all cases of Lgap between 0.1 to 2 µm (shown in Figure 5) feature the typical I-V characteristics of MESFET, with a great ID compared to IG when VGS is higher than Von and a greater IG compared to ID when VGS lower than Von. In detail, ID decreases as Lgap increases in the IG-dominant regime, whereas increases as Lgap increases in the normal-operation regime. However, IG decreases as Lg increases in both the IG-dominant regime and the normal-operation regime. It is noticeab that the I-V characteristics for Lgap = 0.1 µm are significantly different, with a longer Lgap 0.2, 0.5, 1.0, and 2.0 µm. Such differences are explained in the following sections b considering the current path of the device with the current density, charge concentratio and potential distribution. It can be inferred that under the normal operation regim electron transport under the gate-source gap does not deteriorate the current unless th carrier concentration under the gap is maintained at a high enough level. Figure 6 shows the current density distribution and its vector in the IG-dominan regime, off regime, and normal-operation regime for Lgap = 0.1 µm (Figure 6a-c) and Lgap 2.0 µm (Figure 6d-f). As discussed in Section 3.2.1, the current flows into the gate electrod from the drain electrode under the IG-dominant regime and the off regime. For both value of Lgap, the current density is high at the edge of the gate on the drain side (highlighted b the black rectangle) under the IG-dominant regime and the off regime. In the norma operation regime, the drain current joins the gate current to flow into the source. In detail, I D decreases as L gap increases in the I G -dominant regime, whereas I D increases as L gap increases in the normal-operation regime. However, I G decreases as L gap increases in both the I G -dominant regime and the normal-operation regime. It is noticeable that the I-V characteristics for L gap = 0.1 µm are significantly different, with a longer L gap = 0.2, 0.5, 1.0, and 2.0 µm. Such differences are explained in the following sections by considering the current path of the device with the current density, charge concentration and potential distribution. It can be inferred that under the normal operation regime electron transport under the gate-source gap does not deteriorate the current unless the carrier concentration under the gap is maintained at a high enough level. Figure 6 shows the current density distribution and its vector in the I G -dominant regime, off regime, and normal-operation regime for L gap = 0.1 µm (Figure 6a-c) and L gap = 2.0 µm (Figure 6d-f). As discussed in Section 3.2.1, the current flows into the gate electrode from the drain electrode under the I G -dominant regime and the off regime. For both values of L gap , the current density is high at the edge of the gate on the drain side (highlighted by the black rectangle) under the I G -dominant regime and the off regime. In the normal-operation regime, the drain current joins the gate current to flow into the source. The differences in current-voltage characteristics between Lgap = 0.1 µm and the cases can be elucidated by the current path. In the IG-dominant regime, the current from the source and drain electrodes toward the gate electrodes. Therefore, a smalle length between the gate and source/drain electrodes increases both ID and IG by prov a shorter resistive path to the gate electrode. In the case of the off regime, the current from the drain electrode to the source electrode while being leaked in the gate ch area. A smaller Lgap decreases both ID and IG due to a longer gate current path betwe drain and source electrodes. Noticeably, a greater difference in the drain curr compared to IG undermines leakage of the drain current while crossing the gate ch area. Lastly, in the normal-operation regime the current flows from the drain and electrodes toward the source electrode. Therefore, there is no crowding of current frontier of the gate electrode and drain-gate electrode gap. Due to this phenomeno current density ID remains almost constant when Lgap > 0.1 µm. Meanwhile, the current ID shows a drastic difference in cases where Lgap is 0.1 µm. This could orig from the fact that the current from both the gate and the drain accumulates itself edge of the source electrode. A more plausible explanation can be made by referr the charge carrier concentration and potential distribution, as detailed in the follo section.

Carrier Concentration and Potential Distribution
The simulation results of the carrier concentration distribution n(x, y), show Figure 7, reveal that the semiconductor under the gate electrode is either fully deple the IG-dominant regime or partially depleted in the off regime and normal-ope regime for both cases of Lgap. On the other hand, a high carrier concentration up to cm −3 is observed beneath the electrodes gap, where the effect of the gate field is o reach. This phenomenon is more pronounced in the case of a larger Lgap. For Lgap = 0 when the gap becomes comparable to a few Debye length, the effect of the gate fi present in the gap, as reported in [29]. In this case, the carrier concentration in th becomes approximately 10 6 cm −3 lower than 10 17 cm −3 by several orders of magnitud  for (a,b), 9.9 µm ≤ x ≤ 10.2 µm for (c), 17 µm ≤ x ≤ 21 µm for (d,e), 9 µm ≤ x ≤ 13 µm for (f)) is shown for all panels. The work function of the gate is W G = 5.4 eV. The black boxes indicate the region where the total current density is high.
The differences in current-voltage characteristics between L gap = 0.1 µm and the other cases can be elucidated by the current path. In the I G -dominant regime, the current flows from the source and drain electrodes toward the gate electrodes. Therefore, a smaller gap length between the gate and source/drain electrodes increases both I D and I G by providing a shorter resistive path to the gate electrode. In the case of the off regime, the current flows from the drain electrode to the source electrode while being leaked in the gate channel area. A smaller L gap decreases both I D and I G due to a longer gate current path between the drain and source electrodes. Noticeably, a greater difference in the drain current I D compared to I G undermines leakage of the drain current while crossing the gate channel area. Lastly, in the normal-operation regime the current flows from the drain and gate electrodes toward the source electrode. Therefore, there is no crowding of current at the frontier of the gate electrode and drain-gate electrode gap. Due to this phenomenon, the current density I D remains almost constant when L gap > 0.1 µm. Meanwhile, the gate current I D shows a drastic difference in cases where L gap is 0.1 µm. This could originate from the fact that the current from both the gate and the drain accumulates itself at the edge of the source electrode. A more plausible explanation can be made by referring to the charge carrier concentration and potential distribution, as detailed in the following section.

Carrier Concentration and Potential Distribution
The simulation results of the carrier concentration distribution n(x, y), shown in Figure 7, reveal that the semiconductor under the gate electrode is either fully depleted in the I G -dominant regime or partially depleted in the off regime and normal-operation regime for both cases of L gap . On the other hand, a high carrier concentration up to~10 17 cm −3 is observed beneath the electrodes gap, where the effect of the gate field is out of reach. This phenomenon is more pronounced in the case of a larger L gap . For L gap = 0.1 µm when the gap becomes comparable to a few Debye length, the effect of the gate field is present in the gap, as reported in [29]. In this case, the carrier concentration in the gap becomes approximately 10 6 cm −3 lower than 10 17 (Figure 8b,e) justifies the high current density concentration at the edge of the gate electrode from the drain electrode. In the normal-operation regime (Figure 8c,f), a greater potential difference is found at the edge of the source electrode from the gate electrode. Thereby, the high current density flows in this area.

Conclusions
In this study, we have described the effects of the gate work function and electrode gap on the electrical characteristics of Sn-doped α-Ga 2 O 3 MESFETs using TCAD software. The gate work function significantly changes the current level of the I G -dominant regime, hence the rectification ratio. The existence and the mechanism of the gate current under the I G -dominant regime were illustrated by simulated current density distribution and vector as well as by charge carrier and potential distribution, allowing for determination of a theoretical optimal gate work function value of a coplanar MESFET. As for the electrode gap, the simulation results of the current vector enabled us to understand the current path in Sn-doped α-Ga 2 O 3 MESFETs. It is imperative to respect a certain amount of gap distance between electrodes of at least than 0.1 µm to prevent the effect of the gate field in the gap region. Considering that most research efforts have been focused on the deposition and characterization of an Sn-doped α-Ga 2 O 3 heteroepitaxial layer, this study on device simulation will help to translate such knowledge concerning α-Ga 2 O 3 heteroepitaxy into device design, fabrication and optimization for further improvement of device performance.