Remarkable Reduction in IG with an Explicit Investigation of the Leakage Conduction Mechanisms in a Dual Surface-Modified Al2O3/SiO2 Stack Layer AlGaN/GaN MOS-HEMT

We demonstrated the performance of an Al2O3/SiO2 stack layer AlGaN/GaN metal–oxide semiconductor (MOS) high-electron-mobility transistor (HEMT) combined with a dual surface treatment that used tetramethylammonium hydroxide (TMAH) and hydrochloric acid (HCl) with post-gate annealing (PGA) modulation at 400 °C for 10 min. A remarkable reduction in the reverse gate leakage current (IG) up to 1.5×10−12 A/mm (@ VG = −12 V) was observed in the stack layer MOS-HEMT due to the combined treatment. The performance of the dual surface-treated MOS–HEMT was significantly improved, particularly in terms of hysteresis, gate leakage, and subthreshold characteristics, with optimized gate annealing treatment. In addition, an organized gate leakage conduction mechanism in the AlGaN/GaN MOS–HEMT with the Al2O3/SiO2 stack gate dielectric layer was investigated before and after gate annealing treatment and compared with the conventional Schottky gate. The conduction mechanism in the reverse gate bias was Poole–Frankel emission for the Schottky-gate HEMT and the MOS–HEMT before annealing. The dominant conduction mechanism was ohmic/Poole-Frankel at low/medium forward bias. Meanwhile, gate leakage was governed by the hopping conduction mechanism in the MOS–HEMT without gate annealing modulation at a higher forward bias. After post-gate annealing (PGA) treatment, however, the leakage conduction mechanism was dominated by trap-assisted tunneling at the low to medium forward bias region and by Fowler–Nordheim tunneling at the higher forward bias region. Moreover, a decent product of maximum oscillation frequency and gate length (fmax × LG) was found to reach 27.16 GHz∙µm for the stack layer MOS–HEMT with PGA modulation. The dual surface-treated Al2O3/SiO2 stack layer MOS–HEMT with PGA modulation exhibited decent performance with an IDMAX of 720 mA/mm, a peak extrinsic transconductance (GMMAX) of 120 mS/mm, a threshold voltage (VTH) of −4.8 V, a higher ION/IOFF ratio of approximately 1.2×109, a subthreshold swing of 82 mV/dec, and a cutoff frequency(ft)/maximum frequency of (fmax) of 7.5/13.58 GHz.


Introduction
Considering the unique features of III-nitride, e.g., high carrier density (~10 13 /cm 3 ), large band gap (~3.4 eV), high saturation velocity (~2 × 10 7 cm/s), and large breakdown field (>3 MV/cm), extensive research has been conducted on AlGaN/GaN high-electronmobility transistors (HEMTs) for high-power and high-frequency applications [1][2][3]. The high-density and high-mobility two-dimensional electron gas (2DEG) generated at the AlGaN/GaN interface enables us to understand how a power-switching transistor with low ON resistance is relevant to next-generation power conversion systems [4]. However, the performance of this type of transistor is inherently limited by high gate leakage current

Materials and Methods
The AlGaN/GaN epitaxy was grown using a low-pressure metal-organic chemical vapour deposition (MOCVD) system on a p-type low-resistive (111) Si substrate. The epilayers consisted 3.9 µm GaN buffer layer, a 300 nm undoped GaN layer, a 20 nm Al 0.25 Ga 0.75 N barrier layer, and a 2 nm GaN cap layer. The measured sheet carrier concentration and Hall mobility were 6.15 × 10 12 /cm 2 and 2338 cm 2 /V·s, respectively.
Device processing started with mesa isolation by using an ICP reactive ion etching system with a Cl 2 /BCl 3 gas mixture. Then, the sample was immersed into 5% TMAH solution at 85 • C for 1 min to remove native oxide and ICP etching damage. Thereafter, the source and the drain regions were defined via ultraviolet (UV) photolithography. Then, Ti/Al/Ni/Au (25/150/30/120 nm) metal contacts were deposited using an electron beam (e-beam) evaporator system, followed by rapid thermal annealing at 875 • C for 30 s under N 2 ambient atmosphere to ensure good ohmic contact. Subsequently, HCl wet treatment was performed for 3 min prior to gate metal deposition for conventional HEMT and gate oxide deposition for MOS-HEMT. Then, a stack gate dielectric layer composed of a 5 nm SiO 2 followed by a 10 nm Al 2 O 3 layer, was deposited using an ALD system (Picosun) at 250 • C. Finally, the gate region was defined via UV photolithography, and a Ni/Au (80/100 nm) gate stack was deposited using an e-beam evaporator followed by a liftoff process. To improve device performance further, PGA was performed at 400 • C for 10 min. Sheet resistance was 434 Ω/ . For reference, a MOS-HEMT with 5 nm SiO 2 gate dielectric and a conventional HEMT were also fabricated. The gate width (W G ) and gate length (L G ) were 100 µm and 2 µm for all devices, and L GD and L SG were both 2 µm. To understand the gate annealing treatment on the MOS-HEMT and the conventional HEMT, all devices were fabricated following the same processing conditions without PGA treatment. Figure 1a,b shows the typical schematic of a MOS-HEMT and a planar HEMT. UV photolithography was performed using an MJB3 Karl Suss mask aligner system. DC I-V and RF performance were measured with a B1500A semiconductor characterization system and an Agilent N5245A network analyzer with an HP 4142B DC monitor, respectively. To understand the gate dielectric thickness we used transmission electron microscopy (TEM) (JEOL JEM-2100F) system. After the focused ion beam, we used carbon lacey grid for better resolution of the TEM image. To understand the quantitative analysis of the surface composition and material elemental composition we did X-ray photoelectron spectroscopy (XPS) (JEOL). To analyze the effect of TMAH wet surface treatment on the performance of the stack layer MOS-HEMT device, XPS was conducted using a k-alpha X-ray photoelectron spectrometer. To stick the sample on the holder for XPS a copper foil conductive has been used. A monochromatic Al Kα X-ray source with 90 • taken off-angle was used. The sputtering depth was approximately 30-50 nm.

Results
Figure 1c,d shows the TEM image of the Al2O3/SiO2 MOS-HEMT before and after gate annealing treatment. Clear layers of the 5 nm SiO2 and 10 nm Al2O3 were found without intermixing before PGA treatment. Owing to the diffusion of atoms, a less layered structure was observed after gate annealing treatment. Typical atomic force microscopy (AFM) images are shown in Figure 2a-e under different conditions. As shown in Figure  2a,b, side wall surface morphology was improved with TMAH surface treatment. After dual surface treatment with PGA modification, the root-mean-square roughness was sig-

Figure 1c
,d shows the TEM image of the Al 2 O 3 /SiO 2 MOS-HEMT before and after gate annealing treatment. Clear layers of the 5 nm SiO 2 and 10 nm Al 2 O 3 were found without intermixing before PGA treatment. Owing to the diffusion of atoms, a less layered structure was observed after gate annealing treatment. Typical atomic force microscopy (AFM) images are shown in Figure 2a-e under different conditions. As shown in Figure 2a,b, side wall surface morphology was improved with TMAH surface treatment. After dual surface treatment with PGA modification, the root-mean-square roughness was significantly improved from 0.70 nm to 0.24 nm, subsequently enhancing device performance.  Figure 3 illustrates the change in the atomic composition of the Ga 3 core levels before and after surface treatment, with both spectra deconvoluted into two peaks of Ga-N and Ga-O. The Ga 3d5/2 and Ga2O3 (Ga 3+ ) peaks were de-convoluted by considering spin-orbital splitting [30]. Figure 3 clearly shows that the intensity of Ga-O is considerably lower after TMAH surface treatment. The peak intensity ratio of Ga-O/Ga-N significantly decreased to 6.6% from 63%. The removal of native oxide at the GaN surface via wet surface treatment reduced the intensity of the Ga-O bond, subsequently improving device performance as previously reported [31][32][33][34].  Figure 3 illustrates the change in the atomic composition of the Ga 3 core levels before and after surface treatment, with both spectra deconvoluted into two peaks of Ga-N and Ga-O. The Ga 3d 5/2 and Ga 2 O 3 (Ga 3+ ) peaks were de-convoluted by considering spin-orbital splitting [30]. Figure 3 clearly shows that the intensity of Ga-O is considerably lower after TMAH surface treatment. The peak intensity ratio of Ga-O/Ga-N significantly decreased to 6.6% from 63%. The removal of native oxide at the GaN surface via wet surface treatment reduced the intensity of the Ga-O bond, subsequently improving device performance as previously reported [31][32][33][34].
The typical drain current versus voltage (I D -V D ) characteristics of the conventional HEMT and the Al 2 O 3 /SiO 2 stack layer MOS-HEMT are shown in Figure 4. The I DMAX of the dual surface-treated stack layer (SiO 2 ) MOS-HEMT and the conventional HEMT was 720 mA/mm (650 mA/mm) (@ V G = 3 V) and 520 mA/mm (@ V G = 1 V), respectively, with PGA modulation, as shown in Figure 4. Better pinch-off behavior in the stack layer MOS-HEMT suggested better gate controllability than in the SiO 2 MOS-HEMT. The conventional HEMT was not biased with higher V G due to the large late leakage current. The reduction of I DMAX in the conventional HEMT was attributed to the large I G [35]. Moreover, I DMAX was 650 mA/mm (500 mA/mm) for the MOS-HEMT (HEMT) without annealing modulation. In addition, the ON resistance (R ON ) was significantly reduced from 6.3 Ω.mm to 4.9 Ω.mm in the MOS-HEMT due to dual surface treatment with the application of a stack dielectric layer.  Figure 3 illustrates the change in the atomic composition of the Ga 3 core levels before and after surface treatment, with both spectra deconvoluted into two peaks of Ga-N and Ga-O. The Ga 3d5/2 and Ga2O3 (Ga 3+ ) peaks were de-convoluted by considering spin-orbital splitting [30]. Figure 3 clearly shows that the intensity of Ga-O is considerably lower after TMAH surface treatment. The peak intensity ratio of Ga-O/Ga-N significantly decreased to 6.6% from 63%. The removal of native oxide at the GaN surface via wet surface treatment reduced the intensity of the Ga-O bond, subsequently improving device performance as previously reported [31][32][33][34].  The typical drain current versus voltage (ID-VD) characteristics of the conventional HEMT and the Al2O3/SiO2 stack layer MOS-HEMT are shown in Figure 4. The IDMAX of the dual surface-treated stack layer (SiO2) MOS-HEMT and the conventional HEMT was 720 mA/mm (650 mA/mm) (@ VG = 3 V) and 520 mA/mm (@ VG = 1 V), respectively, with PGA modulation, as shown in Figure 4. Better pinch-off behavior in the stack layer MOS-HEMT suggested better gate controllability than in the SiO2 MOS-HEMT. The conventional HEMT was not biased with higher VG due to the large late leakage current. The reduction of IDMAX in the conventional HEMT was attributed to the large IG [35]. Moreover, IDMAX was 650 mA/mm (500 mA/mm) for the MOS-HEMT (HEMT) without annealing modulation. In addition, the ON resistance (RON) was significantly reduced from 6.3 Ω.mm to 4.9 Ω.mm in the MOS-HEMT due to dual surface treatment with the application of a stack dielectric layer. The transfer characteristics of the stack layer MOS-HEMT and the conventional HEMT before and after gate annealing treatment (@ VD = 4 V) are shown in Figure 5. The Al2O3/SiO2 stack layer MOS-HEMT exhibited a VTH of −4.8 V (−4.4 V) with (without) gate annealing modulation. For the conventional HEMT and the SiO2 MOS-HEMT, VTH was −2.7 V and −3.6 V, respectively. The threshold voltage is defined as the gate bias intercept point of the linear extrapolation of the drain current at GMMAX [22]. The VTH difference between HEMT and MOS-HEMT can be expressed as [5]: where Qint is the total interface charge, tox is the thickness of the dielectric layer, is the effective dielectric constant of the stack dielectric layer, and nox is the oxide bulk charge. In accordance with Equation (1), the negative shift of VTH is attributable to the increment of the interface fixed charge at the interface and oxide layers and the increase in the 2DEG concentration after passivation [36][37][38]. Moreover, the increase in separation between the gate and the channel layer may be another reason for the negative shifting of VTH. The shift of VTH to the reverse direction with gate annealing treatment was confirmed in Figure  5b. The transfer characteristics of the stack layer MOS-HEMT and the conventional HEMT before and after gate annealing treatment (@ V D = 4 V) are shown in Figure 5. The Al 2 O 3 /SiO 2 stack layer MOS-HEMT exhibited a V TH of −4.8 V (−4.4 V) with (without) gate annealing modulation. For the conventional HEMT and the SiO 2 MOS-HEMT, V TH was −2.7 V and −3.6 V, respectively. The threshold voltage is defined as the gate bias intercept point of the linear extrapolation of the drain current at G MMAX [22]. The V TH difference between HEMT and MOS-HEMT can be expressed as [5]: where Q int is the total interface charge, t ox is the thickness of the dielectric layer, ε ox is the effective dielectric constant of the stack dielectric layer, and n ox is the oxide bulk charge. In accordance with Equation (1), the negative shift of V TH is attributable to the increment of the interface fixed charge at the interface and oxide layers and the increase in the 2DEG concentration after passivation [36][37][38]. Moreover, the increase in separation between the gate and the channel layer may be another reason for the negative shifting of V TH . The shift of V TH to the reverse direction with gate annealing treatment was confirmed in Figure 5b.  An improvement in peak extrinsic transconductance (GMMAX) was observed in the dual surface-treated Al2O3/SiO2 stack layer MOS-HEMT after gate annealing modulation compared with the SiO2 MOS-HEMT or the conventional HEMT shown in Figure 5. The GMMAX values were 120 mS/mm (102 mS/mm) and 123 mS/mm (110 mS/mm) in the stack layer MOS-HEMT and the conventional HEMT with annealing (without annealing) modulation. The insertion of the two gate dielectrics increased the distance between the gate and the 2DEG channel, reducing gate controllability and decreasing GMMAX in MOS-HEMT. In addition, GVS, defined as the 10% drop in maximum transconductance, was calculated for both devices to understand the linearity behavior of the device [20]. GVS improved from 1.10 V to 1.92 V in the dual surface-treated stack layer MOS-HEMT after gate annealing treatment. Thus, low phase noise, device linearity, and wide dynamic range were improved after dual surface treatment and PGA modulation in the stack layer MOS-HEMT [39]. Moreover, GMMAX was 91 mS/mm in the SiO2 MOS-HEMT. Figure 6 shows the subthreshold characteristics as a function of gate voltage (@ VD = 4 V) for all devices. In this figure, the subthreshold drain leakage current was decreased by more than three orders of magnitude in the Al2O3/SiO2 MOS-HEMT after gate annealing modulation compared with that of the conventional HEMT. The subthreshold drain leakage current was influenced by the reverse bias gate leakage current in the pinch-off region [39]. Given that IG was suppressed by the combined effects of the stack layer gate dielectric and dual surface treatment with PGA modulation in MOS-HEMT, as discussed later, the subthreshold drain leakage current was decreased to a considerable extent. Subthreshold swing (SS) also depends on IG. The SS values of different devices were extracted from Figure 6. The SS values were improved from 130 mV/dec to 82 mV/dec in the stack layer MOS-HEMT after gate annealing treatment. Meanwhile, for the conventional HEMT (SiO2 MOS-HEMT), the SS value was 178 mV/dec (91 mV/dec). The current ON/OFF (ION/IOFF) ratios were 1.2 × 10 and 5.8 × 10 for the stack layer MOS-HEMT with and without PGA treatment. By contrast, no significant improvement in the current ratio was found in the planar HEMT after gate annealing treatment. An improvement in peak extrinsic transconductance (G MMAX ) was observed in the dual surface-treated Al 2 O 3 /SiO 2 stack layer MOS-HEMT after gate annealing modulation compared with the SiO 2 MOS-HEMT or the conventional HEMT shown in Figure 5. The G MMAX values were 120 mS/mm (102 mS/mm) and 123 mS/mm (110 mS/mm) in the stack layer MOS-HEMT and the conventional HEMT with annealing (without annealing) modulation. The insertion of the two gate dielectrics increased the distance between the gate and the 2DEG channel, reducing gate controllability and decreasing G MMAX in MOS-HEMT. In addition, GVS, defined as the 10% drop in maximum transconductance, was calculated for both devices to understand the linearity behavior of the device [20]. GVS improved from 1.10 V to 1.92 V in the dual surface-treated stack layer MOS-HEMT after gate annealing treatment. Thus, low phase noise, device linearity, and wide dynamic range were improved after dual surface treatment and PGA modulation in the stack layer MOS-HEMT [39]. Moreover, G MMAX was 91 mS/mm in the SiO 2 MOS-HEMT. Figure 6 shows the subthreshold characteristics as a function of gate voltage (@ V D = 4 V) for all devices. In this figure, the subthreshold drain leakage current was decreased by more than three orders of magnitude in the Al 2 O 3 /SiO 2 MOS-HEMT after gate annealing modulation compared with that of the conventional HEMT. The subthreshold drain leakage current was influenced by the reverse bias gate leakage current in the pinch-off region [39]. Given that I G was suppressed by the combined effects of the stack layer gate dielectric and dual surface treatment with PGA modulation in MOS-HEMT, as discussed later, the subthreshold drain leakage current was decreased to a considerable extent. Subthreshold swing (SS) also depends on I G . The SS values of different devices were extracted from Figure 6. The SS values were improved from 130 mV/dec to 82 mV/dec in the stack layer MOS-HEMT after gate annealing treatment. Meanwhile, for the conventional HEMT (SiO 2 MOS-HEMT), the SS value was 178 mV/dec (91 mV/dec). The current ON/OFF (I ON /I OFF ) ratios were 1.2 × 10 9 and 5.8 × 10 7 for the stack layer MOS-HEMT with and without PGA treatment. By contrast, no significant improvement in the current ratio was found in the planar HEMT after gate annealing treatment.
The reverse and forward gate leakage current (I G -V G ) characteristics of the dual surface-treated stack layer MOS-HEMT before and after gate annealing treatment and the Schottky gate HEMT without PGA were measured, and the results are presented in Figure 7.
The reverse gate leakage current (@ V G = −12 V) of the Al 2 O 3 /SiO 2 MOS-HEMT was 2.3 × 10 −8 A/mm before gate annealing treatment. Evidently, I G was significantly reduced by four orders of magnitude to 1.5 × 10 −12 A/mm after annealing treatment with dual surface modification. The insertion of large bandgap materials as gate dielectric combined with dual surface treatment and PGA modulation reduced I G to a considerable extent. The reverse and forward gate leakage current (IG-VG) characteristics of the dual surface-treated stack layer MOS-HEMT before and after gate annealing treatment and the Schottky gate HEMT without PGA were measured, and the results are presented in Figure  7. The reverse gate leakage current (@ VG = −12 V) of the Al2O3/SiO2 MOS-HEMT was 2.3 × 10 A/mm before gate annealing treatment. Evidently, IG was significantly reduced by four orders of magnitude to 1.5 × 10 A/mm after annealing treatment with dual surface modification. The insertion of large bandgap materials as gate dielectric combined with dual surface treatment and PGA modulation reduced IG to a considerable extent. To explore the charge of transportation mechanisms responsible for the gate leakage phenomenon, IG-VG characteristics were divided into five regions as indicated in Figure  7. Leakage characteristics were analyzed in different regions to determine the dominant leakage mechanism for each particular region. The multiple conduction mechanism was studied to justify the appropriate charge transport phenomenon in the stack layer MOS-HEMT before and after gate annealing treatment and conventional HEMT. The conduction band edge diagram of the MOS-HEMT before and after PGA treatment and HEMT  The reverse and forward gate leakage current (IG-VG) characteristics of the dual surface-treated stack layer MOS-HEMT before and after gate annealing treatment and the Schottky gate HEMT without PGA were measured, and the results are presented in Figure  7. The reverse gate leakage current (@ VG = −12 V) of the Al2O3/SiO2 MOS-HEMT was 2.3 × 10 A/mm before gate annealing treatment. Evidently, IG was significantly reduced by four orders of magnitude to 1.5 × 10 A/mm after annealing treatment with dual surface modification. The insertion of large bandgap materials as gate dielectric combined with dual surface treatment and PGA modulation reduced IG to a considerable extent. To explore the charge of transportation mechanisms responsible for the gate leakage phenomenon, IG-VG characteristics were divided into five regions as indicated in Figure  7. Leakage characteristics were analyzed in different regions to determine the dominant leakage mechanism for each particular region. The multiple conduction mechanism was studied to justify the appropriate charge transport phenomenon in the stack layer MOS-HEMT before and after gate annealing treatment and conventional HEMT. The conduction band edge diagram of the MOS-HEMT before and after PGA treatment and HEMT To explore the charge of transportation mechanisms responsible for the gate leakage phenomenon, I G -V G characteristics were divided into five regions as indicated in Figure 7. Leakage characteristics were analyzed in different regions to determine the dominant leakage mechanism for each particular region. The multiple conduction mechanism was studied to justify the appropriate charge transport phenomenon in the stack layer MOS-HEMT before and after gate annealing treatment and conventional HEMT. The conduction band edge diagram of the MOS-HEMT before and after PGA treatment and HEMT under different operating regions that illustrated the conduction mechanisms is shown in Figure 8.

Gate Leakage Mechanisms in the AlGaN/GaN MOS-HEMT before Gate Annealing
For the stack layer MOS-HEMT before annealing treatment, as indicated in Region (I) for V G ≤ V TH , the leakage current was saturated due to the saturation of the vertical electrical fields across the gate dielectric and the barrier layer [5]. However, the I G -V G characteristics in Region (II) exhibited dependency on the applied electric field, and the PFE mechanism clearly dominated this region, as suggested in the fitted curve of [ln (I/V) vs. V 1/2 ] in Figure 9a. A comparatively high electric field supported the PFE conduction depicted in the fitted Figure 9a, and the charge transferred through a trap shown in the band edge diagram in Figure 8a in this region exhibited the following relation [5,40]: where ε Di is the permittivity of the dielectric materials, k B is the Boltzmann's constant, T is the temperature, and q is the electronic charge. The effective dielectric constant (ε Di ) was extracted to 7.2 from the ln (I/V) vs V 1/2 characteristics, which was sufficiently close to the calculated effective dielectric constant of the Al 2 O 3 /SiO 2 layer [41].
The dominant leakage conduction mechanism in Region (III) was ohmic due to the linear relationship of ln (I) vs. ln (V), with a slope value close to 1, as shown in Figure 9b. The leakage mechanism was assumed to be PFE at a comparatively higher voltage region. The linear fitting in Figure 9c further confirmed PFE conduction because electrons can be de-trapped with an increased electric field as shown in the band edge diagram in Figure 8b. In addition, the dominant conduction mechanism in a high field region (V G ≥ 3 V) was satisfied with hopping conduction from the fitted curve of ln (I) vs. V, as shown in Figure 9d. Hopping distance (λ) can be extracted from the fitted curve by considering the following equation [40,42]: where n is the electron concentration, f is the thermal vibration frequency of the trapping sites, E is the corresponding electric field, and E a is the activation energy. The hopping distance was calibrated to 0.47 nm by using Equation (4). The electrons can overcome the hopping distance (λ) in the higher field region, as shown in Figure 8c, due to the higher energy. To explore the charge of transportation mechanisms responsible for the gate leakage phenomenon, IG-VG characteristics were divided into five regions as indicated in Figure 7. Leakage characteristics were analyzed in different regions to determine the dominant leakage mechanism for each particular region. The multiple conduction mechanism was studied to justify the appropriate charge transport phenomenon in the stack layer MOS-HEMT before and after gate annealing treatment and conventional HEMT. The conduction band edge diagram of the MOS-HEMT before and after PGA treatment and HEMT under different operating regions that illustrated the conduction mechanisms is shown in Figure 8.

Gate Leakage Mechanisms in the AlGaN/GaN MOS-HEMT before Gate Annealing
For the stack layer MOS-HEMT before annealing treatment, as indicated in Region (I) for VG ≤ VTH, the leakage current was saturated due to the saturation of the vertical electrical fields across the gate dielectric and the barrier layer [5]. However, the IG-VG characteristics in Region (II) exhibited dependency on the applied electric field, and the PFE mechanism clearly dominated this region, as suggested in the fitted curve of [ln (I/V) vs V 1/2 ] in Figure 9a. A comparatively high electric field supported the PFE conduction depicted in the fitted Figure 9a, and the charge  The dominant leakage conduction mechanism in Region (III) was ohmic due to the linear relationship of ln (I) vs. ln (V), with a slope value close to 1, as shown in Figure 9b. The leakage mechanism was assumed to be PFE at a comparatively higher voltage region. The linear fitting in Figure 9c further confirmed PFE conduction because electrons can be de-trapped with an increased electric field as shown in the band edge diagram in Figure  8b. In addition, the dominant conduction mechanism in a high field region (VG ≥ 3 V) was satisfied with hopping conduction from the fitted curve of ln (I) vs. V, as shown in Figure 9d. Hopping distance ( ) can be extracted from the fitted curve by considering the following equation [40,42]: where n is the electron concentration, f is the thermal vibration frequency of the trapping sites, E is the corresponding electric field, and Ea is the activation energy. The hopping distance was calibrated to 0.47 nm by using Equation (4). The electrons can overcome the hopping distance ( ) in the higher field region, as shown in Figure 8c, due to the higher energy.

Gate Leakage Mechanisms in the AlGaN/GaN MOS-HEMT after Gate Annealing
The leakage mechanism of the Al2O3/SiO2 MOS-HEMT after gate annealing modulation was also investigated as shown in Figure 10. After gate annealing modulation, shallow traps were reduced [39] and IG was independent of gate voltage at VG ≤ 2 V due to the saturation of the electric field [5]. The conduction band diagram in Region (IV) for the stack layer MOS-HEMT after annealing treatment is shown in Figure 8d. In this region, leakage transportation was estimated from the fitting curve of [ln (I) vs. 1/V], as shown in Figure 10a, to a two-step TAT mechanism. The electric field dependence of the TAT current (JTAT) is given by the following equation [43]:

Gate Leakage Mechanisms in the AlGaN/GaN MOS-HEMT after Gate Annealing
The leakage mechanism of the Al 2 O 3 /SiO 2 MOS-HEMT after gate annealing modulation was also investigated as shown in Figure 10. After gate annealing modulation, shallow traps were reduced [39] and I G was independent of gate voltage at V G ≤ 2 V due to the saturation of the electric field [5]. The conduction band diagram in Region (IV) for the stack layer MOS-HEMT after annealing treatment is shown in Figure 8d. In this region, leakage transportation was estimated from the fitting curve of [ln (I) vs. 1/V], as shown in Figure 10a, to a two-step TAT mechanism. The electric field dependence of the TAT current (J TAT ) is given by the following equation [43]: where ∅ T is the trapped energy of electron traps with respect to the conduction band edge, A is a constant, and h is Planck's constant. Shallow traps were reduced through the creation of deep traps via PGA modulation, causing the conduction mechanism to shift toward TAT from PFE after gate annealing treatment as indicated in the band diagram of TAT in Figure 8d [44]. Consequently, the leakage mechanism in the high forward bias region was dominated by FNT across the Al 2 O 3 /SiO 2 gate dielectric layer, as shown in Figure 10b. FNT current density (J FNT ) can be related to the electric field across the dielectric (E Di ) by [45]: where A is a constant, B = 8π (2 m n *(q∅ e f f ) 3 ) 1/2 /(3qh), m n * is the effective mass of the electron in the gate dielectric, ∅ e f f is the effective barrier height of the electrons for FNT, and h is Planck's constant. The linear relationship of the ln I V 2 vs. 1/V graph in Figure 10b verified the FNT conduction mechanism in Region (V) for the MOS-HEMT after gate annealing modulation. The band edge diagram of FNT is shown in Figure 8e.
where ∅ is the trapped energy of electron traps with respect to the conduction band edge, A is a constant, and h is Planck's constant. Shallow traps were reduced through the creation of deep traps via PGA modulation, causing the conduction mechanism to shift toward TAT from PFE after gate annealing treatment as indicated in the band diagram of TAT in Figure 8d [44]. Consequently, the leakage mechanism in the high forward bias region was dominated by FNT across the Al2O3/SiO2 gate dielectric layer, as shown in Figure 10b. FNT current density (JFNT) can be related to the electric field across the dielectric (EDi) by [45]: where is a constant, = 8 (2 mn*(q∅ ) 3 ) 1/2 /(3qh), mn* is the effective mass of the electron in the gate dielectric, ∅ is the effective barrier height of the electrons for FNT, and h is Planck's constant. The linear relationship of the ln vs. 1/V graph in Figure   10b verified the FNT conduction mechanism in Region (V) for the MOS-HEMT after gate annealing modulation. The band edge diagram of FNT is shown in Figure 8e.

Gate Leakage Mechanisms in the AlGaN/GaN HEMT
We also investigated the conduction mechanism of leakage current in the conventional HEMT without PGA by dividing the IG-VG characteristics into different regions, as shown in Figure 7. From Figure 7, IG (@ VG ≤ −4 V) was clearly saturated due to the saturation of the vertical electrical fields as mentioned previously. The conduction mechanism in Region (II) was confirmed as PFE conduction from the ln (I/V) vs. V 1/2 graph by following Equation (2), similar to the stack layer MOS-HEMT before PGA treatment, as shown in Figure 11a. In addition, Schottky emission (SE) dominated Region (III) with increasing electric fields at VG > 0 from the linear slope of ln (I/T 2 ) vs. V 1/2 , as shown in Figure 11b, in accordance with the following relation [7]:

Gate Leakage Mechanisms in the AlGaN/GaN HEMT
We also investigated the conduction mechanism of leakage current in the conventional HEMT without PGA by dividing the I G -V G characteristics into different regions, as shown in Figure 7. From Figure 7, I G (@ V G ≤ −4 V) was clearly saturated due to the saturation of the vertical electrical fields as mentioned previously. The conduction mechanism in Region (II) was confirmed as PFE conduction from the ln (I/V) vs. V 1/2 graph by following Equation (2), similar to the stack layer MOS-HEMT before PGA treatment, as shown in Figure 11a. In addition, Schottky emission (SE) dominated Region (III) with increasing electric fields at V G > 0 from the linear slope of ln (I/T 2 ) vs. V 1/2 , as shown in Figure 11b, in accordance with the following relation [7]: where S SE is the SE lowering coefficients, and ∅ B is the Schottky barrier height as depicted in the conduction band edge of Region (III) in Figure 8f. In general, SE leads to conduction through the contact interface rather than from bulk material. By contrast, PFE is closely related to the tunneling of carriers and associated with the wide distribution of traps in the band gap of dielectric materials, which originates from impurities and/or structural defects. To understand the interface quality of the devices, the hysteresis characteristics of the Al 2 O 3 /SiO 2 stack layer MOS-HEMT and the conventional MOS-HEMT were measured (@ V G = 6 V) before and after gate annealing treatment, as shown in Figure 12. Hysteresis behavior was significantly improved after gate annealing modulation in both devices. After gate annealing modulation, the MOS-HEMT exhibited nearly low hysteresis of 0.1 V due to the affective neutralization of the surface caused by the combined effects of TMAH/HCl surface treatment with gate annealing modulation [7]. In addition, a counterclockwise hysteresis was observed in both devices. No surface states were available to capture electrons at a high gate voltage due to the presence of acceptor-like surface states, and electron density in the 2DEG channel was increased to raise the channel current, resulting in counterclockwise hysteresis [7,46].
where is the SE lowering coefficients, and ∅ is the Schottky barrier height as depicted in the conduction band edge of Region (III) in Figure 8f. In general, SE leads to conduction through the contact interface rather than from bulk material. By contrast, PFE is closely related to the tunneling of carriers and associated with the wide distribution of traps in the band gap of dielectric materials, which originates from impurities and/or structural defects.
To understand the interface quality of the devices, the hysteresis characteristics of the Al2O3/SiO2 stack layer MOS-HEMT and the conventional MOS-HEMT were measured (@ VG = 6 V) before and after gate annealing treatment, as shown in Figure 12. Hysteresis behavior was significantly improved after gate annealing modulation in both devices. After gate annealing modulation, the MOS-HEMT exhibited nearly low hysteresis of 0.1 V due to the affective neutralization of the surface caused by the combined effects of TMAH/HCl surface treatment with gate annealing modulation [7]. In addition, a counterclockwise hysteresis was observed in both devices. No surface states were available to capture electrons at a high gate voltage due to the presence of acceptor-like surface states, and electron density in the 2DEG channel was increased to raise the channel current, resulting in counterclockwise hysteresis [7,46].
where is the SE lowering coefficients, and ∅ is the Schottky barrier height as depicted in the conduction band edge of Region (III) in Figure 8f. In general, SE leads to conduction through the contact interface rather than from bulk material. By contrast, PFE is closely related to the tunneling of carriers and associated with the wide distribution of traps in the band gap of dielectric materials, which originates from impurities and/or structural defects.
To understand the interface quality of the devices, the hysteresis characteristics of the Al2O3/SiO2 stack layer MOS-HEMT and the conventional MOS-HEMT were measured (@ VG = 6 V) before and after gate annealing treatment, as shown in Figure 12. Hysteresis behavior was significantly improved after gate annealing modulation in both devices. After gate annealing modulation, the MOS-HEMT exhibited nearly low hysteresis of 0.1 V due to the affective neutralization of the surface caused by the combined effects of TMAH/HCl surface treatment with gate annealing modulation [7]. In addition, a counterclockwise hysteresis was observed in both devices. No surface states were available to capture electrons at a high gate voltage due to the presence of acceptor-like surface states, and electron density in the 2DEG channel was increased to raise the channel current, resulting in counterclockwise hysteresis [7,46].  To understand the reduction of trap states after dual surface treatment and PGA modulation with the stack layer gate dielectric in the MOS-HEMT compared with that in the conventional HEMT, capacitance-voltage (C-V) measurements were performed at 1 MHz for both devices as shown in Figure 13a. The high-frequency performance of the stack layer MOS-HEMT and the conventional HEMT without PGA, and short-circuit current gain (|H21|), maximum stable gain/maximum available gain (MSG/MAG) were measured as shown in Figure 13b. The measured cut-off frequency (ft) and maximum oscillation frequency (fmax) of the MOS-HEMT were 7.5 GHz and 13.5 GHz, while those for the conventional HEMT were only 2.7 GHz and 5 GHz, respectively. The comparatively higher (f max × L G ) was recorded in the MOS-HEMT after PGA modification in contrast with previous reports as indicated in Table 1. The interface state density (D it ) for the dual surface-treated MOS-HEMT can be extracted from a previously reported formula [47] to be 1.61 × 10 12 eV −1 cm −2 , which is significantly improved from that of the conventional HEMT 1.1 × 10 13 eV −1 cm −2 . For the SiO 2 MOS-HEMT, D it was 3.8 × 10 12 eV −1 cm −2 . Given the combined effects of dual surface treatment and the stack dielectric layer with gate annealing modulation, D it was significantly reduced up to one order of magnitude lower in the MOS-HEMT compared with that in the conventional HEMT. Table 1  tional HEMT 1.1 × 10 eV cm . For the SiO2 MOS-HEMT, Dit was 3.8 × 10 eV cm . Given the combined effects of dual surface treatment and the stack dielectric layer with gate annealing modulation, Dit was significantly reduced up to one order of magnitude lower in the MOS-HEMT compared with that in the conventional HEMT. Table 1 presents the DC performance and high-frequency comparison of the different gate structure MOS-HEMTs, including the PGA modulated dual surface-treated Al2O3/SiO2 stack layer MOS-HEMT [17,19,31,[48][49][50][51].

Reference
LG (

Conclusions
In summary, we successfully demonstrated the performance of an Al 2 O 3 /SiO 2 stack layer MOS-HEMT that used TMAH and HCl dual surface treatment prior to gate oxide deposition with PGA modulation. The off-state gate leakage current was remarkably reduced to 1.5 × 10 −12 A/mm, which was seven orders of magnitude lower (~10 −5 A/mm) than that of the conventional HEMT. A significant reduction in I G was observed in MOS-HEMT due to the combined effects of dual surface treatment and the stack gate dielectric layer with gate annealing modulation at 400 • C. In addition, a systematic investigation of the gate leakage conduction mechanism of the conventional HEMT and the MOS-HEMT before and after PGA modulation was conducted. At reverse bias, the PFE conduction mechanism dominated both devices. At low and medium forward bias, the dominant conduction mechanisms were ohmic and PFE, and at higher forward bias, gate leakage was governed by the hopping conduction mechanism for the MOS-HEMT before PGA. By contrast, after the gate annealing treatment of MOS-HEMT, the dominant leakage conduction mechanism was TAT at the low to medium forward bias region and FNT at the higher forward bias region due to the reduction of shallow traps.
Author Contributions: S.M. was responsible for the device preparation, characterization, modeling discussion and writing the draft. P.P. was responsible for the characterization and modeling discussion; K.-W.L. was responsible for the data analysis and editing of the manuscript; Y.-H.W. was the advisor who supervised the progress and paper editing. All authors have read and agreed to the published version of the manuscript.

Data Availability Statement:
The data presented in this study are available on request from the corresponding author.