Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.


Introduction
With etching, oxidation, and other critical processing technologies becoming more and more mature, SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are gradually applied to power electronic fields to replace traditional silicon power devices [1][2][3][4]. Numerous SiC MOSFET products have been pushed into the market [5][6][7]. Due to the advantages of low-specific ON resistance (R onsp ), high power density, fast switching speed, and low switching loss, trench-gate SiC MOSFETs are more promising than planar-gate ones [8][9][10]. However, for the sidewall and the bottom of a trench gate, which suffer from higher electric fields during practical applications, trench-gate SiC MOSFETs are faced with more serious reliability issues when compared with planar-gate devices [11,12].
In this work, the variations in the degradation trends resulting from the structure difference between two types of trench-gate devices, which are the double-trench SiC MOS-FET produced by Rohm and the asymmetric trench SiC MOSFET produced by Infineon, are investigated in detail. The avalanche stress, which applies load current (I load ) and extremely high breakdown voltage (BV) to a device simultaneously and leads to obvious degradation or even damage, is chosen as the targeted stress. It is found that after enduring repetitive avalanche stress, the static and dynamic characteristics of the two trench-gate devices exhibit different degradation trends. With the help of Silvaco TCAD simulations, the dominant mechanism is found and proved by analyzing the physical characteristics of both the devices under avalanche state.

Device Structures and Experiment Conditions
The cross-sectional schematic diagrams of the double-trench SiC MOSFET (SCT3160KL) and the asymmetric trench SiC MOSFET (IMW120R140M1H) studied in this work are shown in Figure 1a,b. Their rated BV is 1200 V, as listed in Table 1. The rated ON-state resistance (R on ) and the DC drain current (I D ) of the double-trench SiC MOSFET were 160 mΩ and 18 A, while the R on and the I D of the asymmetric trench SiC MOSFET were 140 mΩ and 19 A. They share similar conduction and blocking characteristics. 2022, 14, x FOR PEER REVIEW 2 of 12 the short-circuit stress, has been well studied [15][16][17][18][19][20][21][22][23][24][25][26]. Most of the existing articles only report the failure or the degradation mechanism of one single trench-gate device [15][16][17][18][19][20][21][22]. Very few of them investigated the failure of both devices at the same time [23][24][25][26]. However, no one reported that the disparate device structures would result in different degradations in the device performances, even if they are both trench-gate SiC MOSFETs. In this work, the variations in the degradation trends resulting from the structure difference between two types of trench-gate devices, which are the double-trench SiC MOSFET produced by Rohm and the asymmetric trench SiC MOSFET produced by Infineon, are investigated in detail. The avalanche stress, which applies load current (Iload) and extremely high breakdown voltage (BV) to a device simultaneously and leads to obvious degradation or even damage, is chosen as the targeted stress. It is found that after enduring repetitive avalanche stress, the static and dynamic characteristics of the two trench-gate devices exhibit different degradation trends. With the help of Silvaco TCAD simulations, the dominant mechanism is found and proved by analyzing the physical characteristics of both the devices under avalanche state.

Device Structures and Experiment Conditions
The cross-sectional schematic diagrams of the double-trench SiC MOSFET (SCT3160KL) and the asymmetric trench SiC MOSFET (IMW120R140M1H) studied in this work are shown in Figure 1a,b. Their rated BV is 1200 V, as listed in Table 1     The double-trench SiC MOSFET has not only a gate trench to form the two vertical channels but also a source trench. The length and depth of each trench were both 1 µm. The P-well in the source trench can reduce the bottom electric field of the trench gate. For an asymmetric trench SiC MOSFET, there is only one channel in a single cell. The right corner of the gate is surrounded by the highly doped deep P+ well, which extends to the bottom of the trench gate, protecting the left trench corner where current flows. As shown in Figure 1b, different from the double-trench device, the left trench sidewall of the asymmetric device was parallel to the (11)(12)(13)(14)(15)(16)(17)(18)(19)(20) crystal plane. Since the N epitaxial layer is homoepitaxially grown on a 4 • off-axis 4H-SiC (0001) substrate, the channel of the asymmetric trench SiC MOSFET is inclined [27]. At the same time, the (11)(12)(13)(14)(15)(16)(17)(18)(19)(20) crystal plane provides twice the channel mobility of other crystal planes, which improves the current density of the asymmetric trench SiC MOSFET [27,28].
The cell pitch of the double-trench SiC MOSFET was 3.6 µm, while that of the asymmetric one was 3.2 µm. The doping concentrations of the P-body and N-drift region of the double-trench device were set to be 1 × 10 17 cm −3 and 8 × 10 15 cm −3 , while those of the asymmetric one were 1 × 10 17 cm −3 and 1 × 10 16 cm −3 , respectively. All the cell dimensions and the doping concentrations were modified based on the real device structures and the measured characteristics. The simulations performed in this paper were based on the device structures in Figure 1. Figure 2 expresses the schematic circuit diagram of the avalanche stress system and the oscilloscope waveforms generated by the system on the asymmetric trench SiC MOSFET. A drive circuit controlled the ON and OFF of the device under testing (DUT). The gate-source voltage (V gs ) was set from 0 to 18 V. The DUT was connected in series with an inductor (L = 1 mH). The power supply voltage (V DD ) was 100 V. As shown in Figure 2b, when the gate of the DUT turns ON, the drain-source current (I ds ) gradually rises. The rising slope of the current was proportional to the V DD and inversely proportional to the inductance value: corner of the gate is surrounded by the highly doped deep P+ well, which extends to the bottom of the trench gate, protecting the left trench corner where current flows. As shown in Figure 1b, different from the double-trench device, the left trench sidewall of the asymmetric device was parallel to the (11)(12)(13)(14)(15)(16)(17)(18)(19)(20) crystal plane. Since the N epitaxial layer is homoepitaxially grown on a 4° off-axis 4H-SiC (0001) substrate, the channel of the asymmetric trench SiC MOSFET is inclined [27]. At the same time, the (11)(12)(13)(14)(15)(16)(17)(18)(19)(20) crystal plane provides twice the channel mobility of other crystal planes, which improves the current density of the asymmetric trench SiC MOSFET [27,28]. The cell pitch of the double-trench SiC MOSFET was 3.6 μm, while that of the asymmetric one was 3.2 μm. The doping concentrations of the P-body and N-drift region of the double-trench device were set to be 1 × 10 17 cm −3 and 8 × 10 15 cm −3 , while those of the asymmetric one were 1 × 10 17 cm −3 and 1 × 10 16 cm −3 , respectively. All the cell dimensions and the doping concentrations were modified based on the real device structures and the measured characteristics. The simulations performed in this paper were based on the device structures in Figure 1. Figure 2 expresses the schematic circuit diagram of the avalanche stress system and the oscilloscope waveforms generated by the system on the asymmetric trench SiC MOSFET. A drive circuit controlled the ON and OFF of the device under testing (DUT). The gate-source voltage (Vgs) was set from 0 to 18 V. The DUT was connected in series with an inductor (L = 1 mH). The power supply voltage (VDD) was 100 V. As shown in Figure 2b, when the gate of the DUT turns ON, the drain-source current (Ids) gradually rises. The rising slope of the current was proportional to the VDD and inversely proportional to the inductance value: When the gate of the DUT turns OFF, the energy stored in the inductor is dissipated on the DUT. At this time, the SiC MOSFET is under the avalanche state. The Vds equals to the BV and the current flows through the inductor following the formula: When the current in the circuit falls to 0 A, the energy stored in the inductor is completely consumed and the avalanche state of the device ends. When the gate of the DUT turns OFF, the energy stored in the inductor is dissipated on the DUT. At this time, the SiC MOSFET is under the avalanche state. The V ds equals to the BV and the current flows through the inductor following the formula: When the current in the circuit falls to 0 A, the energy stored in the inductor is completely consumed and the avalanche state of the device ends. When applying the avalanche stress on the device and gradually increasing the gate pulse width until it fails, the asymmetric trench SiC MOSFET can endure a peak I load (I peak ) of 22 A, as shown in Figure 2a. All the three ports of the failed device were short-circuited, indicating that the device dies from thermal runaway [25]. The avalanche waveforms with an I peak of 18 A, which is 80% of 22 A, as shown in Figure 2b, were adopted here to repetitively stress the asymmetric trench SiC MOSFET. The gate pulse width was 180 µs and the I ds increased to 18 A at a rate of 0.1 A/µs. After that, the gate of the device turns OFF and the device is under the avalanche state while the V ds is kept at 1600 V.
The avalanche-induced failure waveforms of the double-trench SiC MOSFET are shown in Figure 3a. After enduring a 16 A-avalanche stress, the gate leakage current (I gss ) is higher than 1 µA, indicating that the gate failure is the dominant mechanism [18,19]. Obviously, the asymmetric trench SiC MOSFET can endure much more serious single-pulse avalanche stress than the double-trench one, implying that the asymmetric structure has a better protection effect [25]. Similarly, the avalanche stress with 13 A I peak , which is 80% the maximum avalanche current the device can endure, was adopted to stress the double-trench SiC MOSFET. The stress waveforms are presented in Figure 3b. The gate pulse width was 130 µs. When under the avalanche state, the V ds of the double-trench device is 1700 V. When applying the avalanche stress on the device and gradually increasing the gate pulse width until it fails, the asymmetric trench SiC MOSFET can endure a peak Iload (Ipeak) of 22 A, as shown in Figure 2a. All the three ports of the failed device were short-circuited, indicating that the device dies from thermal runaway [25]. The avalanche waveforms with an Ipeak of 18 A, which is 80% of 22 A, as shown in Figure 2b, were adopted here to repetitively stress the asymmetric trench SiC MOSFET. The gate pulse width was 180 μs and the Ids increased to 18 A at a rate of 0.1 A/μs. After that, the gate of the device turns OFF and the device is under the avalanche state while the Vds is kept at 1600 V.
The avalanche-induced failure waveforms of the double-trench SiC MOSFET are shown in Figure 3a. After enduring a 16 A-avalanche stress, the gate leakage current (Igss) is higher than 1 μA, indicating that the gate failure is the dominant mechanism [18,19]. Obviously, the asymmetric trench SiC MOSFET can endure much more serious singlepulse avalanche stress than the double-trench one, implying that the asymmetric structure has a better protection effect [25]. Similarly, the avalanche stress with 13 A Ipeak, which is 80% the maximum avalanche current the device can endure, was adopted to stress the double-trench SiC MOSFET. The stress waveforms are presented in Figure 3b. The gate pulse width was 130 μs. When under the avalanche state, the Vds of the double-trench device is 1700 V. In addition, during the repetitive avalanche stress experiments for both the devices, the duty cycle of all pulses was 0.1%. Wind heat dissipation was also added to suppress the rise in the junction temperature. The repetitive avalanche stress with extremely high voltage and current will lead to the degradation of the devices, which is going to be analyzed in Section 3.

Asymmetric Trench SiC MOSFET
After enduring repetitive avalanche stress, the electrical characteristics under different stress cycles were measured and compared. Figure 4 shows the degradation in the threshold voltage (Vth) of the asymmetric trench SiC MOSFET. With the increase of the total stress cycles, the Vth curves shifted to the negative direction. The Vth under the condition of Vds = 1 V and Ids = 2.5 mA is extracted in Figure 4c. After enduring 10k cycles, the In addition, during the repetitive avalanche stress experiments for both the devices, the duty cycle of all pulses was 0.1%. Wind heat dissipation was also added to suppress the rise in the junction temperature. The repetitive avalanche stress with extremely high voltage and current will lead to the degradation of the devices, which is going to be analyzed in Section 3.

Asymmetric Trench SiC MOSFET
After enduring repetitive avalanche stress, the electrical characteristics under different stress cycles were measured and compared. Figure 4 shows the degradation in the threshold voltage (V th ) of the asymmetric trench SiC MOSFET. With the increase of the total stress cycles, the V th curves shifted to the negative direction. The V th under the condition of V ds = 1 V and I ds = 2.5 mA is extracted in Figure 4c. After enduring 10k cycles, the V th of the asymmetric device dropped from 4.4 to 3.9 V. In the logarithmic scale, the V th at I ds = 1 nA was reduced by 1.15 V, as shown in Figure 4b, which is more obvious than that in the linear scale. This indicates that after enduring the repetitive avalanche stress, the channel of the asymmetric trench SiC MOSFET degrades.
Vth of the asymmetric device dropped from 4.4 to 3.9 V. In the logarithmic scale, the Vth at Ids = 1 nA was reduced by 1.15 V, as shown in Figure 4b, which is more obvious than that in the linear scale. This indicates that after enduring the repetitive avalanche stress, the channel of the asymmetric trench SiC MOSFET degrades.   The variations of the capacitance characteristic of the asymmetric trench device were also measured. As shown in Figure 6, with the increase of the stress cycles, the gate-drain capacitance (Cgd) of the device increased slightly. Within 10k cycles, the maximum Cgd rose from 128 pF to 154 pF, equaling to an increment of 20.3%. This is because there were The variations of the capacitance characteristic of the asymmetric trench device were also measured. As shown in Figure 6, with the increase of the stress cycles, the gate-drain capacitance (C gd ) of the device increased slightly. Within 10k cycles, the maximum C gd rose from 128 pF to 154 pF, equaling to an increment of 20.3%. This is because there were positive charges injected into the left corner and the bottom interface of the gate trench, which will be explained later in Section 3.2. The variations of the capacitance characteristic of the asymmetric trench device were also measured. As shown in Figure 6, with the increase of the stress cycles, the gate-drain capacitance (Cgd) of the device increased slightly. Within 10k cycles, the maximum Cgd rose from 128 pF to 154 pF, equaling to an increment of 20.3%. This is because there were positive charges injected into the left corner and the bottom interface of the gate trench, which will be explained later in Section 3.2.

Double-Trench SiC MOSFET
The repetitive avalanche experiment was also performed on the double-trench SiC MOSFET. As can be seen in Figure 7, the Vth of the device only expressed a slight negative shift during the experiment, implying that the channel of the device was rarely degraded, which is quite different from the phenomenon monitored in Figure 4. Meanwhile, as shown in Figure 8, with the increase of the stress cycles, the Id-Vd curve under the condition of Vgs = 18 V rose significantly. This means that the Ron at Vgs = 18 V and Ids = 18 A was decreased by 14%.

Double-Trench SiC MOSFET
The repetitive avalanche experiment was also performed on the double-trench SiC MOSFET. As can be seen in Figure 7, the V th of the device only expressed a slight negative shift during the experiment, implying that the channel of the device was rarely degraded, which is quite different from the phenomenon monitored in Figure 4. Meanwhile, as shown in Figure 8, with the increase of the stress cycles, the I d -V d curve under the condition of V gs = 18 V rose significantly. This means that the R on at V gs = 18 V and I ds = 18 A was decreased by 14%.
The repetitive avalanche experiment was also performed on the double-trench SiC MOSFET. As can be seen in Figure 7, the V th of the device only expressed a slight negative shift during the experiment, implying that the channel of the device was rarely degraded, which is quite different from the phenomenon monitored in Figure 4. Meanwhile, as shown in Figure 8, with the increase of the stress cycles, the I d -V d curve under the condition of V gs = 18 V rose significantly. The repetitive avalanche experiment was also performed on the double-trench SiC MOSFET. As can be seen in Figure 7, the Vth of the device only expressed a slight negative shift during the experiment, implying that the channel of the device was rarely degraded, which is quite different from the phenomenon monitored in Figure 4. Meanwhile, as shown in Figure 8, with the increase of the stress cycles, the Id-Vd curve under the condition of Vgs = 18 V rose significantly.
As plotted in Figure 9, after enduring 10k avalanche stress cycles, the maximum Cgd of the double-trench device increased from 274 pF to 397 pF, equaling to an increment of 44.9%. This obvious degradation resulted from the positive charges injected into the bottom oxide [20]. This indicates that compared with the asymmetric trench SiC MOSFET, much more positive charges were injected into the trench bottom oxide of the doubletrench device during the avalanche process, making the Cgd change greatly. At the same time, the positive charges attracted electrons and decreased the resistance of the JFET region. Therefore, the Vth of the double-trench SiC MOSFET was unchanged while the Ron was reduced. As plotted in Figure 9, after enduring 10k avalanche stress cycles, the maximum C gd of the double-trench device increased from 274 pF to 397 pF, equaling to an increment of 44.9%. This obvious degradation resulted from the positive charges injected into the bottom oxide [20]. This indicates that compared with the asymmetric trench SiC MOSFET, much more positive charges were injected into the trench bottom oxide of the doubletrench device during the avalanche process, making the C gd change greatly. At the same time, the positive charges attracted electrons and decreased the resistance of the JFET region. Therefore, the V th of the double-trench SiC MOSFET was unchanged while the R on was reduced.

Simulations and Analysis
Simulations were then performed to help analyze the various degradation trends between the two types of devices with different structures. Figure 10a reflects the electric field distribution of the double-trench SiC MOSFET under the avalanche state. The highest electric field was located at the bottom of the source trench, where the avalanche breakdown occurred. Meanwhile, the electric field at the gate trench cannot be ignored. The oxide electric field (Eox) and the impact ionization rate (I.I.) along the gate oxide interface are extracted in Figure 10b. The peak value of the Eox appeared at the bottom, pointing from the semiconductor to the oxide, while the peak I.I. appeared at the corners. This illustrates that the Eox and I.I. at the bottom and corners of the trench together lead to the injection of positive charges into the gate oxide, resulting in an increase in Cgd and decrease in the resistance of the JFET region. There was no I.I. in the channel region of the double-trench device, meaning that the channel was not affected by the stress, which is consistent with the measured data in Figure 7.

Simulations and Analysis
Simulations were then performed to help analyze the various degradation trends between the two types of devices with different structures. Figure 10a reflects the electric field distribution of the double-trench SiC MOSFET under the avalanche state. The highest electric field was located at the bottom of the source trench, where the avalanche breakdown occurred. Meanwhile, the electric field at the gate trench cannot be ignored. The oxide electric field (E ox ) and the impact ionization rate (I.I.) along the gate oxide interface are extracted in Figure 10b. The peak value of the E ox appeared at the bottom, pointing from the semiconductor to the oxide, while the peak I.I. appeared at the corners. This illustrates that the E ox and I.I. at the bottom and corners of the trench together lead to the injection of positive charges into the gate oxide, resulting in an increase in C gd and decrease in the resistance of the JFET region. There was no I.I. in the channel region of the double-trench device, meaning that the channel was not affected by the stress, which is consistent with the measured data in Figure 7. field distribution of the double-trench SiC MOSFET under the avalanche state. The highest electric field was located at the bottom of the source trench, where the avalanche breakdown occurred. Meanwhile, the electric field at the gate trench cannot be ignored. The oxide electric field (Eox) and the impact ionization rate (I.I.) along the gate oxide interface are extracted in Figure 10b. The peak value of the Eox appeared at the bottom, pointing from the semiconductor to the oxide, while the peak I.I. appeared at the corners. This illustrates that the Eox and I.I. at the bottom and corners of the trench together lead to the injection of positive charges into the gate oxide, resulting in an increase in Cgd and decrease in the resistance of the JFET region. There was no I.I. in the channel region of the double-trench device, meaning that the channel was not affected by the stress, which is consistent with the measured data in Figure 7. Furthermore, an asymmetric trench SiC MOSFET structure with a vertical channel was built to help analyze the different degradations resulting from the double-trench and the asymmetric structures, ignoring the influence brought by the inclined channel. The physical characteristics of it under the avalanche state are shown in Figure 11. As can be seen in Figure 11a, the peak value of the electric field was located at the bottom of the Furthermore, an asymmetric trench SiC MOSFET structure with a vertical channel was built to help analyze the different degradations resulting from the double-trench and the asymmetric structures, ignoring the influence brought by the inclined channel. The physical characteristics of it under the avalanche state are shown in Figure 11. As can be seen in Figure 11a, the peak value of the electric field was located at the bottom of the deep P+ well. Different from the double-trench SiC MOSFET, due to the narrower JFET region, the serious E ox did not appear at the bottom of the trench in the asymmetric device. Comparing Figure 11b with Figure 10b, it can be concluded that both the E ox and the I.I. along the trench bottom and the corner of the asymmetric device are much lower than those in the double-trench device. The peak E ox fell from 2.18 × 10 6 V/cm to 8.51 × 10 5 V/cm, decreasing by 61.0%. Meanwhile, the peak I.I. reduced from 1.46 × 10 20 pairs/cm 3 /s to 1.70 × 10 17 pairs/cm 3 /s, equating to a nearly three-orders of magnitude reduction. This demonstrates that the deep P+ well in the asymmetric trench SiC MOSFET can protect the bottom gate oxide well. This is why the double-trench SiC MOSFET shows much more serious degradation in the C gd and the I d -V d curve under the high gate bias condition. Moreover, it is worth noting that there existed a 3.80 × 10 7 pairs/cm 3 /s I.I. peak in the channel, even though it was still minor.
The real asymmetric trench SiC MOSFET produced by Infineon adopted the (11-20) crystal plane to form the channel, making the channel inclined. Figure 12 simulates the physical characteristics of the device. The most obvious difference between Figures 12b and 11b is that a much higher I.I., reaching a peak value of 7.14 × 10 14 pairs/cm 3 /s, appears at the inclined channel region. This is because the inclined crystal plane made the channel become exposed to the avalanche stress, promoting the positive charges to be injected into the channel oxide. Therefore, the V th of the asymmetric trench SiC MOSFET continued to decrease, just as presented in Figure 4. The simulation results are mostly agreeable with the measured data, proving the correctness of the mechanisms discovered and the investigation made in this work. decreasing by 61.0%. Meanwhile, the peak I.I. reduced from 1.46 × 10 20 pairs/cm 3 /s to 1.70 × 10 17 pairs/cm 3 /s, equating to a nearly three-orders of magnitude reduction. This demonstrates that the deep P+ well in the asymmetric trench SiC MOSFET can protect the bottom gate oxide well. This is why the double-trench SiC MOSFET shows much more serious degradation in the Cgd and the Id-Vd curve under the high gate bias condition. Moreover, it is worth noting that there existed a 3.80 × 10 7 pairs/cm 3 /s I.I. peak in the channel, even though it was still minor. The real asymmetric trench SiC MOSFET produced by Infineon adopted the (11-20) crystal plane to form the channel, making the channel inclined. Figure 12 simulates the physical characteristics of the device. The most obvious difference between Figure 12b and Figure 11b is that a much higher I.I., reaching a peak value of 7.14 × 10 14 pairs/cm 3 /s, appears at the inclined channel region. This is because the inclined crystal plane made the channel become exposed to the avalanche stress, promoting the positive charges to be injected into the channel oxide. Therefore, the Vth of the asymmetric trench SiC MOSFET continued to decrease, just as presented in Figure 4. The simulation results are mostly agreeable with the measured data, proving the correctness of the mechanisms discovered and the investigation made in this work.

Conclusions
Based on the measured discrepant degradation trends between the double-trench SiC MOSFET and the asymmetric trench SiC MOSFET before and after enduring the repetitive avalanche stress, the mechanisms brought by the different device structures were revealed. On the one hand, since ultrahigh peak values of Eox and I.I. appeared at the bottom oxide of the double-trench SiC MOSFET under the avalanche state, the positive charges injected there contributed to the obvious decrease of the Ron and to the increase of the Cgd. These phenomena were not observed in the asymmetric trench device because the deep P+ well protected the bottom gate oxide well. On the other hand, the inclined channel of the asymmetric device attracted a much higher I.I. in the channel region, leading more positive charges to be injected into the oxide there. Hence, the degradation of the Vth of the asymmetric trench SiC MOSFET was more obvious. The differences in the degradation brought about by the different device structures were summarized and verified. Different from the double-trench SiC MOSFET, the gate oxide at the corner of the trench of the asymmetric trench SiC MOSFET device was well protected. However, when adopting inclined channel, the channel of the asymmetric device is more vulnerable to damage. Therefore, the reliability of both the bottom and the sidewall of the trench needs to be considered in the trench design. It is believed that for these two types of trench-gate SiC MOSFETs, there also exists different degradation phenomena induced by other repetitive stresses, such as the short-circuit stress, the power cycling stress, and the surge current

Conclusions
Based on the measured discrepant degradation trends between the double-trench SiC MOSFET and the asymmetric trench SiC MOSFET before and after enduring the repetitive avalanche stress, the mechanisms brought by the different device structures were revealed. On the one hand, since ultrahigh peak values of E ox and I.I. appeared at the bottom oxide of the double-trench SiC MOSFET under the avalanche state, the positive charges injected there contributed to the obvious decrease of the R on and to the increase of the C gd . These phenomena were not observed in the asymmetric trench device because the deep P+ well protected the bottom gate oxide well. On the other hand, the inclined channel of the asymmetric device attracted a much higher I.I. in the channel region, leading more positive charges to be injected into the oxide there. Hence, the degradation of the V th of the asymmetric trench SiC MOSFET was more obvious. The differences in the degradation brought about by the different device structures were summarized and verified. Different from the double-trench SiC MOSFET, the gate oxide at the corner of the trench of the asymmetric trench SiC MOSFET device was well protected. However, when adopting inclined channel, the channel of the asymmetric device is more vulnerable to damage. Therefore, the reliability of both the bottom and the sidewall of the trench needs to be considered in the trench design. It is believed that for these two types of trench-gate SiC MOSFETs, there also exists different degradation phenomena induced by other repetitive stresses, such as the short-circuit stress, the power cycling stress, and the surge current stress, which will be studied in detail in the future.