High-κ van der Waals Oxide MoO3 as Efficient Gate Dielectric for MoS2 Field-Effect Transistors

Two-dimensional van der Waals crystals (2D vdW) are recognized as one of the potential materials to solve the physical limits caused by size scaling. Here, vdW metal oxide MoO3 is applied with the gate dielectric in a 2D field-effect transistor (FET). Due to its high dielectric constant and the good response of MoS2 to visible light, we obtained a field effect transistor for photodetection. In general, the device exhibits a threshold voltage near 0 V, Ion/Ioff ratio of 105, electron mobility about 85 cm2 V−1 s−1 and a good response to visible light, the responsivity is near 5 A/W at low laser power, which shows that MoO3 is a potential material as gate dielectric.


Introduction
There is no doubt that the transistor is an indispensable part of modern life, it is the brain of all electronic devices today. Unfortunately, the short channel effect caused by the reduction in channel size and the direct electron tunneling caused by the decrease in dielectric layer thickness seriously restricts the performance of devices [1][2][3][4]. Two-dimensional van der Waals materials (2D vdW) with superior carrier migration and excellent gate controllability at atomic thickness are considered as the next-generation potential channel materials [5]. In addition, since the capacitance is inversely proportional to the gate dielectric material thickness and proportional to the dielectric constant [6]. It can be seen that materials with high dielectric constant can satisfy the thickness reduction while providing strong capacitive coupling. To date, the 2D field-effect transistors supported by high-κ material substrate has been reported. For example, Ganapathi et al. fabricated MoS 2 short channel devices with 5 nm-thick HfO 2 , achieving an extremely low threshold voltage (approximately −1 V), 10 6 switching ratio, and extremely low subthreshold swing (110~120 mV/dec) [7]. Ah-Jin Cho et al. also successfully fabricated the field effect devices using Al 2 O 3 as the gate dielectric layer [8]. However, there are a lot of dangling bonds and surface trap states in the thin film dielectric layer, resulting in a large hysteresis. High-quality vdW dielectric has received much attention due to its atomic plane, hanging bonds-free, and low trap density. Hexagonal boron nitride (hBN) is the most common two-dimensional insulator and is widely regarded as a promising gate insulator in twodimensional material transistors. However, the dielectric constant of hBN is only 5 [9]. Recently, Liu et al. showed that MoS 2 field-effect transistors supported by Sb 2 O 3 dielectric substrate exhibit negligible hysteresis [10]. However, the dielectric constant of Sb 2 O 3 is also only 11.5, there is still a lot of room for improvement.
As a member of transition metal oxides (TMO), α-MoO 3 is widely used in electronics, sensors, energy storage and other fields [11]. More importantly, α-MoO 3 has high dielectric constant. It has been shown that α-MoO 3 has the relative dielectric constant as high as 35, near 10 times that of SiO 2 [12]. In addition, the unique vdW characteristics can be easily integrated with other 2D vdW semiconductors, promising applications in future 2D electronics and optoelectronics [13,14].
Here, we constructed the α-MoO 3 flake support MoS 2 field effect transistor. Thanks to high capacitive coupling, we achieve a low-threshold voltage (−1 V), which is lower than hBN (−2 V) and Sb 2 O 3 (−7 V), and has greater electron mobility (85 cm 2 V −1 s −1 ) compared to the SiO 2 dielectric layer (41 cm 2 V −1 s −1 ). In addition, due to the good response of MoS 2 to visible light, combined with the excellent performance of the MoO 3 gate dielectric layer, we can obtain photodetectors with higher responsivity (5 A/W).

Structural Characteristics of α-MoO 3 Flakes
α-MoO 3 is a wide-bandgap material (3 ev), has a large work function (6 ev), and is an orthorhombic crystal structure [15][16][17]. As shown in Figure 1a, it consists of double layers of MoO 6 octahedrons of approximately 1.4 nm thickness. In each layer, the octahedrons are arranged by sharing angles in the directions [001] and [100], and the different layers are arranged in the direction [010] by van der Waals forces. The preparation of uniform largesize MoO 3 nanosheets is the key to the application of the gate dielectric, so several α-MoO 3 nanosheets were grown using rapid-cooling chemical vapor deposition (CVD) (growth details are shown in the experimental section and Figure S1) [18]. Figure 1b shows the optical image of the prepared MoO 3 nanosheet. It can be seen that MoO 3 nanosheet has a large area, with micron level length and width, regular shape and smooth surface. As show in Figure 1c, the layered structure of MoO 3 is well illustrated by the multi-thickness steps at the edge in atomic force microscopy (AFM) image. XRD characterization revealed that the lattice has a series of sharp peaks at 13.7 • , 26.6 • and 39.8 • , which correspond to the (020), (040), and (060) planes of α-MoO 3 , indicating the high quality of MoO 3 single crystal (Figure 1d).

Device Performance
Good insulation is the key to gate dielectric applications, therefore, we first studied the insulation of MoO3 before preparing heterojunction devices. As shown in Figure S2, when the source-drain voltage (Vds) is 2 V, the MoO3 FET device presents a high resistance

Device Performance
Good insulation is the key to gate dielectric applications, therefore, we first studied the insulation of MoO 3 before preparing heterojunction devices. As shown in Figure S2, when the source-drain voltage (V ds ) is 2 V, the MoO 3 FET device presents a high resistance state of 10 −13 A and remains stable under the action of gate voltage, suggesting the good insulation of MoO 3 . Furthermore, we constructed a graphene/MoO 3 /MoS 2 field effect devices by the dry method of location transfer where graphene, MoO 3 and MoS 2 are the gate electrode, gate dielectric layer and channel layer, respectively (details are shown in the experimental section and Figure S3). An optical image of the prefabricated device is shown in Figure 2b. The AFM in Figure 2c shows that the corresponding thickness of MoS 2 , MoO 3 and Gr are 50 nm, 90 nm and 50 nm, respectively. Raman spectroscopy is further used to confirm heterojunction composition. In the Raman spectrum of graphene, the G peak near 1580 cm −1 can correspond to the c-c σ bond of carbon atoms, reflecting the in-plane vibration of carbon atoms, while the G' peak near 2700 cm −1 corresponds to carbon atom π-bond in the z direction, reflecting graphene-layered connections [19,20]. In the Raman spectrum of MoS 2 , the E 1 2g peak located near 386 cm −1 is caused by the opposite vibrations of the two S atoms relative to the Mo atom, while the A 1g peak located near 408 cm −1 is due to the S atoms in opposite directions out-of-plane vibration [21]. In the Raman spectrum of MoO 3 , there is a strong Raman peak at 820 cm −1 , which corresponds to the O 3 -Mo-O 3 stretching vibration in the [100] direction [22]. Due to the special structure of MoO 3 , there may be oxygen vacancies inside, which will affect the electron mobility, band gap, etc. [23]. Thus, we calculated the exact MoO 3 stoichiometry by analyzing the Raman spectrum. From the Raman spectrum of MoO 3 in Figure 2d, the ratio of I 512 /I 820 is approximately 3.997, and finally, we calculated the ratio of O/Mo to be approximately 2.998, which indicates that there are very few oxygen vacancies in the MoO 3 nanosheets we used. In the Gr/MoO 3 /MoS 2 heterojunction region, Raman signals corresponding to different materials can be obtained simultaneously, which proves the composition of the heterojunction. Raman spectrum. From the Raman spectrum of MoO3 in Figure 2d, the ratio of I512/I820 is approximately 3.997, and finally, we calculated the ratio of O/Mo to be approximately 2.998, which indicates that there are very few oxygen vacancies in the MoO3 nanosheets we used. In the Gr/MoO3/MoS2 heterojunction region, Raman signals corresponding to different materials can be obtained simultaneously, which proves the composition of the heterojunction. MoS2 FETs using MoO3 nanosheets as the gate dielectric show interesting device performance. Figure 3b shows the transfer curves of MoS2 FETs with different gate dielectric layers. Compared with SiO2 as the gate dielectric layer, it can be found that when the MoO3 nanosheet is used as the gate dielectric layer, MoS2 channel conductance increases with the increase in gate voltage, and obvious on-off current can be observed, showing MoS 2 FETs using MoO 3 nanosheets as the gate dielectric show interesting device performance. Figure 3b shows the transfer curves of MoS 2 FETs with different gate dielectric layers. Compared with SiO 2 as the gate dielectric layer, it can be found that when the MoO 3 nanosheet is used as the gate dielectric layer, MoS 2 channel conductance increases with the increase in gate voltage, and obvious on-off current can be observed, showing obvious n-type modulation characteristics, which is caused by the natural sulfur vacancy of MoS 2 [24]. Additionally, due to the low gate current leakage of~10 −11 A, this FET exhibits an equally high on/off ratio (~10 5 ). However, the MoS 2 transistor using SiO 2 as the gate dielectric layer cannot achieve obvious on-off state current within the same gate voltage range. By further increasing the gate voltage, we still observe that MoS 2 channel conductance increases with increasing V gs , because a larger V gs may gradually open the whole channel and increase the conductivity of the whole channel. At the same time, it requires a more negative V gs to close the channel, and a threshold voltage of approximately −9 V can be observed (Figure 3a). This indicates that MoS 2 /MoO 3 FET has lower starting voltage and lower power consumption. In addition, the hysteresis of a transfer curve is usually used to study the charge trap state at the interface. The change of threshold voltage ∆V th in the double-scan transmission characteristic curve is usually affected by the charge ∆Q of the trap state density. It can be found that, with vdW dielectric, ultra-small hysteresis can be observed in the double scan, and the MoS 2 /SiO 2 FET hysteresis window is quite big. According to ∆Q = ∆V th × C where C and ∆Q represent the gate capacitance and capture charge, respectively, the trap state density can be obtained as 9.8 × 10 10 cm −2 , while the trap state density of SiO 2 is 1.4 × 10 12 cm −2 , indicating that MoO 3 is within low effective trap state density. By processing transfer curve data (Figure 3b), we obtained that the subthreshold swing (SS) of molybdenum disulfide with MoO 3 as the gate dielectric layer is basically stable at approximately 400 mV/dec. The gate control characteristics of the channel conductance and the ohmic contact between the electrode and MoS 2 can be further verified from the output curve in Figure 3c. In order to clearly compare the effect of dielectric effects (MoO 3 and SiO 2 ) on FET mobility, we plot together their electron mobility, which is modulated by the gate voltage ( Figure 3d). The electron mobility can be calculated by the following formula: where L and W are the channel length and width, respectively, C is the capacitance, and C can be calculated as 3.27 × 10 −7 F/cm 2 by the following formula: where ε 0 , ε r and d are vacuum permittivity, relative permittivity and dielectric thickness of dielectric layers, respectively. It was evident that MoS 2 on MoO 3 substrate showed approximately twice the mobility (85 cm 2 V −1 S −1 ) compared with that on the SiO 2 substrate (41 cm 2 V −1 S −1 ).
Finally, we statistically compared the performance of this device with other MoS 2 devices with difference gate dielectric layers ( Table 1), showing that the MoO 3 dielectric layer can still have a larger current switching ratio under the small threshold voltage, and its requirements on material thickness is also low.  It was evident that MoS2 on MoO3 substrate showed approximately twice the mobility (85 cm 2 V −1 S −1 ) compared with that on the SiO2 substrate (41 cm 2 V −1 S −1 ).

Device Mechanism Exploration
In order to further understand the carrier transport characteristics of heterojunction devices, Kelvin probe force microscopy (KPFM) was used to obtain the function of the surface potential position along the channel of the sample. Figure 4a is a schematic diagram of KPFM experiments on heterogeneous junction devices under different working conditions. We fixed the source-drain voltage V ds = 0 V and studied the functional relationship between the surface potential and back-gate voltage (V gs ). As shown in Figure 4b, since both ends of the source and drain are grounded, the corresponding surface potential is 0 V, while the channel has an obvious potential difference. When the gate voltage is between −10 V and −2 V, there is no obvious change in the surface potential difference. When the gate voltage rises to within the range of −2 V-0 V, the surface potential of the channel gradually rises, and then it exceeds the source-drain surface potential, and the potential difference is 0.5 V; the gate voltage continues to rise, the surface potential continues to rise, but the upward trend has weakened. Through the change of surface potential difference and the corresponding transfer curve, it can be found that when the gate voltage is −10 V, the surface potential is the smallest, which means that the contact barrier is low, electrons are prone to transition at the interface, and the source-drain current has a large upward trend. As the gate voltage increases, the surface potential difference rises, so the contact potential barrier is raised rapidly, and it is difficult for electrons to transition at the interface, and finally the rising trend of the source-drain current is weakened.
tionship between the surface potential and back-gate voltage (Vgs). As shown in Figure 4b, since both ends of the source and drain are grounded, the corresponding surface potential is 0 V, while the channel has an obvious potential difference. When the gate voltage is between −10 V and −2 V, there is no obvious change in the surface potential difference. When the gate voltage rises to within the range of −2 V-0 V, the surface potential of the channel gradually rises, and then it exceeds the source-drain surface potential, and the potential difference is 0.5 V; the gate voltage continues to rise, the surface potential continues to rise, but the upward trend has weakened. Through the change of surface potential difference and the corresponding transfer curve, it can be found that when the gate voltage is −10 V, the surface potential is the smallest, which means that the contact barrier is low, electrons are prone to transition at the interface, and the source-drain current has a large upward trend. As the gate voltage increases, the surface potential difference rises, so the contact potential barrier is raised rapidly, and it is difficult for electrons to transition at the interface, and finally the rising trend of the source-drain current is weakened.

Device Specific Performance Parameters
Furthermore, the photoelectric performance of the device is verified. We irradiated the entire surface of the device with a 405 nm laser, adjusted the different laser powers and tested whether the relationship between the source-drain current and the gate voltage would be changed compared with the dark state ( Figure 5a). As can be seen from Figure 5a, the photoelectric response of the device is more obvious under the action of negative gate pressure. According to the following formula: is photoresponsivity, is the optical power density, is the effective area of the device, and denote the photocurrent and dark current, respectively. The highest responsivity of the device can be obtained as the power is 1 mW/cm 2 in Figure 5b. Figure 5c summarizes the functional relationship between the responsivity of MoS2 on different substrates and the gate voltage. Since the difference between the photocurrent and dark current of MoS2/MoO3 is larger than that of MoS2/SiO2, by comparison, it is found that the responsivity of MoS2/MoO3 is significantly higher than that of

Device Specific Performance Parameters
Furthermore, the photoelectric performance of the device is verified. We irradiated the entire surface of the device with a 405 nm laser, adjusted the different laser powers and tested whether the relationship between the source-drain current and the gate voltage would be changed compared with the dark state ( Figure 5a). As can be seen from Figure 5a, the photoelectric response of the device is more obvious under the action of negative gate pressure. According to the following formula: where R is photoresponsivity, P is the optical power density, A is the effective area of the device, I light and I dark denote the photocurrent and dark current, respectively.

Conclusions
We demonstrate that MoS2/MoO3 can effectively reduce the device operating voltage. The device exhibits a high on-off ratio (10 5 ), low SS (400 mV/dec), high electron mobility (85 cm 2 V −1 s −1 ), low lag and high stability due to fewer surface defects. In addition to this, we obtained devices with higher electron mobility and a lower density of defect states, which favors smaller hysteresis voltage. Furthermore, the device is capable of significant response to visible light and the most responsivity is near 5 A/W. In general, this study proves that high-κ van der Waals MoO3 can be effectively applied to the gate dielectric layer to improve the photoelectric performance of the device. The highest responsivity of the device can be obtained as the power is 1 mW/cm 2 in Figure 5b. Figure 5c summarizes the functional relationship between the responsivity of MoS 2 on different substrates and the gate voltage. Since the difference between the photocurrent and dark current of MoS 2 /MoO 3 is larger than that of MoS 2 /SiO 2 , by com-parison, it is found that the responsivity of MoS 2 /MoO 3 is significantly higher than that of MoS 2 /SiO 2 under the same optical power, indicating that MoS 2 on MoO 3 substrate shows superior photoelectric performance.

Conclusions
We demonstrate that MoS 2 /MoO 3 can effectively reduce the device operating voltage. The device exhibits a high on-off ratio (10 5 ), low SS (400 mV/dec), high electron mobility (85 cm 2 V −1 s −1 ), low lag and high stability due to fewer surface defects. In addition to this, we obtained devices with higher electron mobility and a lower density of defect states, which favors smaller hysteresis voltage. Furthermore, the device is capable of significant response to visible light and the most responsivity is near 5 A/W. In general, this study proves that high-κ van der Waals MoO 3 can be effectively applied to the gate dielectric layer to improve the photoelectric performance of the device.

Experimental Section
MoO 3 Single Crystal Growth: We used the vapor deposition method, placed approximately 0.1 g of MoO 3 powder in the center of the ark, and then placed the ark in the center of the tube furnace, continued to pass in the gas Ar at a rate of 100 sccm, and connected the gas outlet to the atmosphere. The heating started from room temperature (25 • C), 25 min to 780 • C, keeping warm for 1 min, then the heating tube was quickly removed, and the tube furnace was allowed to cool down rapidly, during which MoO 3 nanosheets could be seen flying out and depositing on the silicon wafer approximately 10 cm away from the powder on the side near the gas outlet. This resulted in large-area MoO 3 nanosheets.

Gr/MoO 3 /MoS 2 Heterostructure Memory Devices Fabrication:
We used the mechanical exfoliation method, used the layered structure of 2D materials, used tape to obtain thin-layer materials, and transferred the thin-layer materials to the same silicon wafer through PDMS. Figure S3 shows the transfer schematic diagram, and displays the transfer and stacking of Gr, MoO 3 and MoS 2 from left to right, respectively. Then, we used the flocculated crystals generated in the tube furnace during the growth of MoO 3 nanosheets to cover the surface of the transistor part with the probes. The surface of the transistor is covered with gold by evaporation method, and the channel of the transistor can be obtained by removing the crystal. Finally, the device is obtained by drawing electrodes with a probe.
Device Characterization: AFM (NT-MDT NTEGRA) was used to characterize the change of surface morphology. The photoluminescence spectrum was measured using confocal Raman microscope (Horiba LabRAM HR Evolution Inc., Palaiseau, France). Semiconductor device parameter analyzer (FS-Pro, Primarius Electronic Technology, Beijing, China) was employed to characterize the electrical properties of the devices. Semiconductor lasers with a wavelength of 405 nm were used to study the photoresponse properties of the devices.