Fabrication and Evaluation of N-Channel GaN Metal–Oxide–Semiconductor Field-Effect Transistors Based on Regrown and Implantation Methods

We have demonstrated the enhancement-mode n-channel gallium nitride (GaN) metal-oxide field-effect transistors (MOSFETs) on homoepitaxial GaN substrates using the selective area regrowth and ion implantation techniques. Both types of MOSFETs perform normally off operations. The GaN-MOSFETs fabricated using the regrowth method perform superior characteristics over the other relative devices fabricated using the ion implantation technique. The electron mobility of 100 cm2/V·s, subthreshold of 500 mV/dec, and transconductance of 14 μs/mm are measured in GaN-MOSFETs based on the implantation technique. Meanwhile, the GaN-MOSFETs fabricated using the regrowth method perform the electron mobility, transconductance, and subthreshold of 120 cm2/V s, 18 μs/mm, and 300 mV/dec, respectively. Additionally, the MOSFETs with the regrown p-GaN gate body show the Ion/Ioff ratio of approximately 4 × 107, which is, to our knowledge, among the best results of GaN-MOSFETs to date. This research contributes a valuable information for the design and fabrication of power switching devices based on GaN.


Introduction
Gallium nitride (GaN) possesses such extraordinary characteristics as high breakdown electric field (3 MV/cm) [1], high saturation velocity (1.4 × 10 7 cm/s) [1], high electron mobility, and good thermal conductivity (~100 W/m·K) [1], thus emerging as one of the most promising materials for next generation power switching devices. Among GaN-based transistor structures, heterostructure field-effect transistors (HFETs) based on AlGaN/GaN heterojunction have been widely used for high-power and high-frequency applications owing to the high electron mobility deriving from the two-dimensional electron gas (2DEG) source. However, because HFETs operate at the normally on mode, there are many significant disadvantages, such as large leakage current, high power consumption in their analog and/or power applications. In order to demonstrate normally off GaN-based HEMTs, several approaches have been proposed. In general, a thin AlGaN barrier layer with a low Al concentration is usually used to achieve the 2DEG depletion region in normally off GaN-based HEMTs. Because the depletion of the 2DEG channel must be formed under the gate, the recession structure of the AlGaN barrier layer has been considered as one of effective solutions for normally off GaN HEMTs [2]. However, an accurate control of the AlGaN etching technology is highly required in this method. Moreover, the damages derived from the etching process probably increase the gate leakage current and hysteresis of threshold voltages. Recently, p-GaN (or p-AlGaN) layer on the

Experimental
The fabrication of the GaN-MOSFET structure with the implantation technique starts with the 500 nm-thick homoepitaxial Mg-doped p-GaN (2 × 10 17 cm −3 ) layer grown by MOCVD on a free standing GaN substrate consisting of a thin unintentionally doped GaN (UID-GaN) and high-resistance insulation GaN substrate, as shown in Figure 1a. The SiO 2 hard mask is deposited on the top of the free standing GaN structure using the plasma enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate and oxygen. Subsequently, mesa structures are defined using the conventional lithography and wet etching of the SiO 2 hard mask. The GaN mesa-insulation regions are formed using Cl 2 /BCl 3 reactive-ion etching, as shown in Figure 1b. The SiO 2 hard mask is removed using the buffered hydrofluoric (BHF) acid. Subsequently, the source and drain (S/D) regions are implanted with Si atoms at room temperature with 10 nm-thick SiO x N y and photoresist protection layer on the gate regions, as shown in Figure 1c. The implantation energy is 15 keV and the dose implantation is 10 15 cm −2 . The rapid thermal annealing (RTA) in the N 2 atmosphere at 1000 • C is used to activate the dopants after the implantation. For the GaN-MOSFET structure fabricated by the regrowth method, the fabrication process is based on the n-GaN (3 × 10 18 cm −3 ), as shown in Figure 2a. The GaN mesa-insulation regions and n-GaN layer on the gate-body region are etched using the reactive-ion etching with Cl 2 /BCl 3 gas mixture, as shown in Figure 2b,c. The sample is immerged in the tetramethyl ammonium hydroxide (TMAH) with 10 wt% at 70 • C in 5 min to etch the damaged n-GaN on the vertical side because of the reactive-ion etching. Subsequently, 200 nm-thick Mg-doped p-GaN (2 × 10 17 cm −3 ) is selectively regrown on the gate region. The regrown p-GaN layer is formed using trimethylgallium (TMGa), bis (cyclopentadienyl) magnesium (Cp 2 Mg), and NH 3 as precursors at 950 • C. The growth is performed with the NH 3 flux of 10 slm and TMGa flux of 20 sccm. An ozone oxidation at 300 • C is used to form the sacrificial GaO x of the damaged GaN layer, which is subsequently removed using BHF acid. The treatment of forming and removing the sacrificial GaO x layer is repeated two times and re-cleaned using diluted hydrofluoric (DHF) acid and HCl acid with the concentration of 0.8 M (mole/litter). The 28 nm-thick Al 2 O 3 thin film as a dielectric is deposited using PEALD with trimethylaluminum and oxygen plasma, as shown in Figures 1d and 2d. According to previous studies, the Al 2 O 3 thin film transforms from amorphous to crystalline phase at over 800 • C [28]. Therefore, Al 2 O 3 dielectric is annealed at 700 • C in a nitrogen (N 2 ) ambience for 1 minute using the rapid temperature annealing (RTA) technique. The electron beam evaporation and conventional wet etching methods are used to form the Ni gate electrodes. The Ti/Al stack structure is formed on the S/D regions by the lift-off technique and subsequently treated with the metallization annealing (PMA) at 600 • C in a N 2 ambience to obtain the ohmic contact, as shown in Figures 1e and 2e. The top view of the fabricated MOSFETs is shown in Figure 2f. The fabrication of the GaN-MOSFET structure with the implantation technique starts with the 500 nm-thick homoepitaxial Mg-doped p-GaN (2 × 10 17 cm −3 ) layer grown by MOCVD on a free standing GaN substrate consisting of a thin unintentionally doped GaN (UID-GaN) and highresistance insulation GaN substrate, as shown in Figure 1a. The SiO2 hard mask is deposited on the top of the free standing GaN structure using the plasma enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate and oxygen. Subsequently, mesa structures are defined using the conventional lithography and wet etching of the SiO2 hard mask. The GaN mesa-insulation regions are formed using Cl2/BCl3 reactive-ion etching, as shown in Figure 1b. The SiO2 hard mask is removed using the buffered hydrofluoric (BHF) acid. Subsequently, the source and drain (S/D) regions are implanted with Si atoms at room temperature with 10 nm-thick SiOxNy and photoresist protection layer on the gate regions, as shown in Figure 1c. The implantation energy is 15 keV and the dose implantation is 10 15 cm −2 . The rapid thermal annealing (RTA) in the N2 atmosphere at 1000 °C is used to activate the dopants after the implantation. For the GaN-MOSFET structure fabricated by the regrowth method, the fabrication process is based on the n-GaN (3 × 10 18 cm −3 ), as shown in Figure  2a. The GaN mesa-insulation regions and n-GaN layer on the gate-body region are etched using the reactive-ion etching with Cl2/BCl3 gas mixture, as shown in Figure 2b,c. The sample is immerged in the tetramethyl ammonium hydroxide (TMAH) with 10 wt% at 70 °C in 5 min to etch the damaged n-GaN on the vertical side because of the reactive-ion etching. Subsequently, 200 nm-thick Mg-doped p-GaN (2 × 10 17 cm −3 ) is selectively regrown on the gate region. The regrown p-GaN layer is formed using trimethylgallium (TMGa), bis (cyclopentadienyl) magnesium (Cp2Mg), and NH3 as precursors at 950 °C. The growth is performed with the NH3 flux of 10 slm and TMGa flux of 20 sccm. An ozone oxidation at 300 °C is used to form the sacrificial GaOx of the damaged GaN layer, which is subsequently removed using BHF acid. The treatment of forming and removing the sacrificial GaOx layer is repeated two times and re-cleaned using diluted hydrofluoric (DHF) acid and HCl acid with the concentration of 0.8 M (mole/litter). The 28 nm-thick Al2O3 thin film as a dielectric is deposited using PEALD with trimethylaluminum and oxygen plasma, as shown in Figures 1d and 2d. According to previous studies, the Al2O3 thin film transforms from amorphous to crystalline phase at over 800 °C [28]. Therefore, Al2O3 dielectric is annealed at 700 °C in a nitrogen (N2) ambience for 1 minute using the rapid temperature annealing (RTA) technique. The electron beam evaporation and conventional wet etching methods are used to form the Ni gate electrodes. The Ti/Al stack structure is formed on the S/D regions by the lift-off technique and subsequently treated with the metallization annealing (PMA) at 600 °C in a N2 ambience to obtain the ohmic contact, as shown in Figures 1e and 2e. The top view of the fabricated MOSFETs is shown in Figure 2f.

Results and Discussion
According to the previous studies, interface state densities (Dit) of approximately 10 12 cm −2 eV −1 and higher are observed in the GaN-MOS capacitors without the surface treatment [29,30]. Because GaN cannot be formed with an oxides-free pristine interface, pre-deposition surface treatments are crucial for a good nucleation of dielectric layers. An erratic nucleation can lead to the formation of such defects as vacancies, vacancy-complexes, interstitials, etc., resulting in high densities of interface traps and fixed charges. By using the proposed treatment process, a low Dit can be obtained because of the removal of nitrogen vacancy (Nv), Ga dangling bonds, and damages on the surface of GaN layer. As a result, the surface trapped state density of approximately 10 11 cm −2 eV −1 is obtained in our previous work [31]. This value is low enough to satisfy the operation of general MOSFETs.
Two types of GaN-MOSFETs fabricated with different techniques are evaluated and compared. Figure 3 shows the output current-voltage (Id-Vd) characteristics of the GaN-MOSFETs with the channel length and channel width of 100 μm. It has been observed that the drain currents are effectively controlled by the gate voltages, thus confirming the transistor operation. Both devices operate with the normally off (enhancement-mode) function. Additionally, the maximum saturation source-drain current of the GaN-MOSFET fabricated using the regrowth method is higher than that of the implantation technique, revealing the low on-state resistance and high electron mobility.

Results and Discussion
According to the previous studies, interface state densities (D it ) of approximately 10 12 cm −2 eV −1 and higher are observed in the GaN-MOS capacitors without the surface treatment [29,30]. Because GaN cannot be formed with an oxides-free pristine interface, pre-deposition surface treatments are crucial for a good nucleation of dielectric layers. An erratic nucleation can lead to the formation of such defects as vacancies, vacancy-complexes, interstitials, etc., resulting in high densities of interface traps and fixed charges. By using the proposed treatment process, a low D it can be obtained because of the removal of nitrogen vacancy (N v ), Ga dangling bonds, and damages on the surface of GaN layer. As a result, the surface trapped state density of approximately 10 11 cm −2 eV −1 is obtained in our previous work [31]. This value is low enough to satisfy the operation of general MOSFETs.
Two types of GaN-MOSFETs fabricated with different techniques are evaluated and compared. Figure 3 shows the output current-voltage (I d -V d ) characteristics of the GaN-MOSFETs with the channel length and channel width of 100 µm. It has been observed that the drain currents are effectively controlled by the gate voltages, thus confirming the transistor operation. Both devices operate with the normally off (enhancement-mode) function. Additionally, the maximum saturation source-drain current of the GaN-MOSFET fabricated using the regrowth method is higher than that of the implantation technique, revealing the low on-state resistance and high electron mobility. Materials 2020, 13, x FOR PEER REVIEW 5 of 10 The logarithmic plots of the drain current -gate voltage (Id-Vg) transfer characteristics under the drain-to-source voltage of 50 mV at a room temperature are shown in Figure 4. The threshold voltages of the devices fabricated by the regrowth and ion implantation methods extracted from the gate bias intercept of the linear extrapolation Id are approximately 1.6 and 2.0 V, respectively. Additionally, the leakage current below the pinch-off voltage in the MOSFET fabricated using the regrowth method is roughly 4 orders of magnitude better than that of the ion implantation technique. This behavior might be explained as the influence of damages after the ion implantation process. During the implantation process, it is difficult to control defect states although the post deposition annealing (PDA) process can partly release this undesired behavior. According to the previous discussions, there is a possibility that defect states play a role of donors in p-GaN and thus dominating the off-state currents. The high leakage current might be caused by the defects, dislocation, and trapped electrons that create the sub-threshold channel in the off-region. Additionally, the subthreshold slope of device fabricated using the regrowth method is approximately 300 mV/dec, which is better than that of the device fabricated by the ion implantation technique (~ 500 mV/dec). This difference is also related to the drain leakage current of the implanted device as a previous discussion. It can be concluded that it is possible to reduce the damages on p-GaN layer during the fabrication process by using the fabrication process based on the regrowth method. Therefore, the off-state current is much lower than that of the device fabricated by the implantation technique. The performances of regrown devices in this work are better than the previous inversion-channel GaN MOSFETs using MgO and SiNx and other Al2O3 dielectrics [5,18,32,33]. According to our knowledge, the Ion/Ioff ratio of approximately 4 × 10 7 obtained in this work is one of the best results to date. The logarithmic plots of the drain current -gate voltage (I d -V g ) transfer characteristics under the drain-to-source voltage of 50 mV at a room temperature are shown in Figure 4. The threshold voltages of the devices fabricated by the regrowth and ion implantation methods extracted from the gate bias intercept of the linear extrapolation I d are approximately 1.6 and 2.0 V, respectively. Additionally, the leakage current below the pinch-off voltage in the MOSFET fabricated using the regrowth method is roughly 4 orders of magnitude better than that of the ion implantation technique. This behavior might be explained as the influence of damages after the ion implantation process. During the implantation process, it is difficult to control defect states although the post deposition annealing (PDA) process can partly release this undesired behavior. According to the previous discussions, there is a possibility that defect states play a role of donors in p-GaN and thus dominating the off-state currents. The high leakage current might be caused by the defects, dislocation, and trapped electrons that create the sub-threshold channel in the off-region. Additionally, the subthreshold slope of device fabricated using the regrowth method is approximately 300 mV/dec, which is better than that of the device fabricated by the ion implantation technique (~500 mV/dec). This difference is also related to the drain leakage current of the implanted device as a previous discussion. It can be concluded that it is possible to reduce the damages on p-GaN layer during the fabrication process by using the fabrication process based on the regrowth method. Therefore, the off-state current is much lower than that of the device fabricated by the implantation technique. The performances of regrown devices in this work are better than the previous inversion-channel GaN MOSFETs using MgO and SiN x and other Al 2 O 3 dielectrics [5,18,32,33]. According to our knowledge, the I on /I off ratio of approximately 4 × 10 7 obtained in this work is one of the best results to date. Figure 5a,b shows the plots for the Y-function and transconductance of the MOSFETs fabricated using the implantation technique and regrowth method, respectively. The comparisons of the transconductance and Y-function of two devices are shown in Figure 6a,b, respectively. According to Figure 6a, the transconductance of the device fabricated by the regrowth method is larger than that of the implantation technique. Moreover, the threshold voltages of the implanted GaN-MOSFET and regrown GaN-MOSFET extracted from the Y-function are approximately 1.8 and 2.2 V, respectively, indicating a good p/n-GaN junction in the device fabricated by the regrowth method. These values are slightly higher than those extracted from the gate-bias intercept of the linear extrapolation of I d in the I d -V g characteristic. The minor difference of threshold voltages between two extraction methods is considered to be due to the fitting error. In general, the selectively etched and regrown p-GaN channel is expected to enhance the drain current, channel electron mobility, and reduce the series resistance by reducing the damages on p-GaN channels. Although the gate channel of the implanted MOSFET is fully covered by SiN x O y and photoresist during the Si-implantation process, it is suggested that some Si atoms still penetrate the p-GaN layer. Moreover, during the fabrication process, the p-GaN layer is exposed in the plasma environment, high temperature activation annealing (~1000 • C), resulting in many defects in the structure. Therefore, the channels of MOSFET fabricated using the regrowth method are expected to possess more extensive p/n junction than those of the MOSFET fabricated using the implantation technique. In contrast, because of the defects, electrons diffusing and/or contaminating in the p-GaN layer of the device fabricated by the implantation technique, the devices investigated in this work do not only utilize the channel inversion as usual inversion-mode MOSFETs but also the electron accumulation formed at the surface of the damaged p-GaN layer. Since there are defects and electrons trapped in the structure, the drain current is not only controlled by adjusting the gate bias and interface conditions, but also the amount of the subthreshold carriers. From above discussions, it is shown that the GaN-MOSFETs fabricated using the regrowth method perform superior characteristics of threshold voltage, on-state current, transconductance, and subthreshold behaviors over the other relative devices fabricated using the ion implantation technique. The comparison of I on /I off ratios obtained in this work and previous reports is shown in Figure 7 [32][33][34][35]. It is concluded that the I on /I off ratio of GaN-MOSFETs can be optimized using the regrowth and surface treatment techniques proposed in this work.
The logarithmic plots of the drain current -gate voltage (Id-Vg) transfer characteristics under the drain-to-source voltage of 50 mV at a room temperature are shown in Figure 4. The threshold voltages of the devices fabricated by the regrowth and ion implantation methods extracted from the gate bias intercept of the linear extrapolation Id are approximately 1.6 and 2.0 V, respectively. Additionally, the leakage current below the pinch-off voltage in the MOSFET fabricated using the regrowth method is roughly 4 orders of magnitude better than that of the ion implantation technique. This behavior might be explained as the influence of damages after the ion implantation process. During the implantation process, it is difficult to control defect states although the post deposition annealing (PDA) process can partly release this undesired behavior. According to the previous discussions, there is a possibility that defect states play a role of donors in p-GaN and thus dominating the off-state currents. The high leakage current might be caused by the defects, dislocation, and trapped electrons that create the sub-threshold channel in the off-region. Additionally, the subthreshold slope of device fabricated using the regrowth method is approximately 300 mV/dec, which is better than that of the device fabricated by the ion implantation technique (~ 500 mV/dec). This difference is also related to the drain leakage current of the implanted device as a previous discussion. It can be concluded that it is possible to reduce the damages on p-GaN layer during the fabrication process by using the fabrication process based on the regrowth method. Therefore, the off-state current is much lower than that of the device fabricated by the implantation technique. The performances of regrown devices in this work are better than the previous inversion-channel GaN MOSFETs using MgO and SiNx and other Al2O3 dielectrics [5,18,32,33]. According to our knowledge, the Ion/Ioff ratio of approximately 4 × 10 7 obtained in this work is one of the best results to date.  Figure 5a,b shows the plots for the Y-function and transconductance of the MOSFETs fabricated using the implantation technique and regrowth method, respectively. The comparisons of the transconductance and Y-function of two devices are shown in Figure 6a,b, respectively. According to Figure 6a, the transconductance of the device fabricated by the regrowth method is larger than that of the implantation technique. Moreover, the threshold voltages of the implanted GaN-MOSFET and regrown GaN-MOSFET extracted from the Y-function are approximately 1.8 and 2.2 V, respectively, indicating a good p/n-GaN junction in the device fabricated by the regrowth method. These values are slightly higher than those extracted from the gate-bias intercept of the linear extrapolation of Id in the Id-Vg characteristic. The minor difference of threshold voltages between two extraction methods is considered to be due to the fitting error. In general, the selectively etched and regrown p-GaN channel is expected to enhance the drain current, channel electron mobility, and reduce the series resistance by reducing the damages on p-GaN channels. Although the gate channel of the implanted MOSFET is fully covered by SiNxOy and photoresist during the Si-implantation process, it is suggested that some Si atoms still penetrate the p-GaN layer. Moreover, during the fabrication process, the p-GaN layer is exposed in the plasma environment, high temperature activation annealing (~ 1000 °C), resulting in many defects in the structure. Therefore, the channels of MOSFET fabricated using the regrowth method are expected to possess more extensive p/n junction than those of the MOSFET fabricated using the implantation technique. In contrast, because of the defects, electrons diffusing and/or contaminating in the p-GaN layer of the device fabricated by the implantation technique, the devices investigated in this work do not only utilize the channel inversion as usual inversion-mode MOSFETs but also the electron accumulation formed at the surface of the damaged p-GaN layer. Since there are defects and electrons trapped in the structure, the drain current is not only controlled by adjusting the gate bias and interface conditions, but also the amount of the subthreshold carriers. From above discussions, it is shown that the GaN-MOSFETs fabricated using the regrowth method perform superior characteristics of threshold voltage, on-state current, transconductance, and subthreshold behaviors over the other relative devices fabricated using the ion implantation technique. The comparison of Ion/Ioff ratios obtained in this work and previous reports is shown in Figure 7. It is concluded that the Ion/Ioff ratio of GaN-MOSFETs can be optimized using the regrowth and surface treatment techniques proposed in this work [34,35].     Figure 8 shows the effective channel-electron mobility of fabricated GaN-MOSFETs. The effective electron mobilities are extracted from the Id-Vg characteristics measured in the dark room. The electron mobilities obtain the maximum values at the specific applied bias gate voltages before decreasing with the increase of carriers density because of the increase of the applied gate voltages. This is the evidence of the appearance of the Coulomb scattering centers. Additionally, the maximum mobility of 120 cm 2 /V·s in the regrown MOSFET is higher than that (100 cm 2 /V·s) of the implanted MOSFET. Because of the damages caused by the implantation and other fabrication steps, the p-GaN layer can contain defects, trapped electrons, ionized impurities, etc. Impurity scattering derived from the charged particles caused by those undesired behaviors would make the electron mobility in the channel formed at the GaN-surface considerably lower than that of a normal bulk GaN. Matthiessen's rule has shown many factors deciding the channel mobility, such as Coulomb scattering mobility, surface phonon mobility, bulk mobility, and surface roughness mobility. Regarding the influence of interface charges near the MOS interface on the channel electron mobility, a significant mobility degradation is observed in Si-MOSFETs with the interface state density of over 10 12 cm −2 eV −1 [36]. According to the Terman method, the interface state density for the fabricated devices is approximately 10 11 cm −2 eV −1 . Therefore, it is expected that the mobility of the MOS channel region will be comparable to the bulk GaN's mobility. A bulk mobility of approximately 600 cm 2 /V·s at room temperature has been reported for n-doped bulk GaN with Nd = 3 × 10 17 cm −3 [37]. However, although   The electron mobilities obtain the maximum values at the specific applied bias gate voltages before decreasing with the increase of carriers density because of the increase of the applied gate voltages. This is the evidence of the appearance of the Coulomb scattering centers. Additionally, the maximum mobility of 120 cm 2 /V·s in the regrown MOSFET is higher than that (100 cm 2 /V·s) of the implanted MOSFET. Because of the damages caused by the implantation and other fabrication steps, the p-GaN layer can contain defects, trapped electrons, ionized impurities, etc. Impurity scattering derived from the charged particles caused by those undesired behaviors would make the electron mobility in the channel formed at the GaN-surface considerably lower than that of a normal bulk GaN. Matthiessen's rule has shown many factors deciding the channel mobility, such as Coulomb scattering mobility, surface phonon mobility, bulk mobility, and surface roughness mobility. Regarding the influence of interface charges near the MOS interface on the channel electron mobility, a significant mobility degradation is observed in Si-MOSFETs with the interface state density of over 10 12 cm −2 eV −1 [36]. According to the Terman method, the interface state density for the fabricated devices is approximately 10 11 cm −2 eV −1 . Therefore, it is expected that the mobility of the MOS channel region will be comparable to the bulk GaN's mobility. A bulk mobility of approximately 600 cm 2 /V·s at room temperature has been reported for n-doped bulk GaN with Nd = 3 × 10 17 cm −3 [37]. However, although  Figure 8 shows the effective channel-electron mobility of fabricated GaN-MOSFETs. The effective electron mobilities are extracted from the Id-Vg characteristics measured in the dark room. The electron mobilities obtain the maximum values at the specific applied bias gate voltages before decreasing with the increase of carriers density because of the increase of the applied gate voltages. This is the evidence of the appearance of the Coulomb scattering centers. Additionally, the maximum mobility of 120 cm 2 /V·s in the regrown MOSFET is higher than that (100 cm 2 /V·s) of the implanted MOSFET. Because of the damages caused by the implantation and other fabrication steps, the p-GaN layer can contain defects, trapped electrons, ionized impurities, etc. Impurity scattering derived from the charged particles caused by those undesired behaviors would make the electron mobility in the channel formed at the GaN-surface considerably lower than that of a normal bulk GaN. Matthiessen's rule has shown many factors deciding the channel mobility, such as Coulomb scattering mobility, surface phonon mobility, bulk mobility, and surface roughness mobility. Regarding the influence of interface charges near the MOS interface on the channel electron mobility, a significant mobility degradation is observed in Si-MOSFETs with the interface state density of over 10 12 cm −2 eV −1 [36]. According to the Terman method, the interface state density for the fabricated devices is approximately 10 11 cm −2 eV −1 . Therefore, it is expected that the mobility of the MOS channel region will be comparable to the bulk GaN's mobility. A bulk mobility of approximately 600 cm 2 /V·s at room temperature has been reported for n-doped bulk GaN with N d = 3 × 10 17 cm −3 [37]. However, although the interface trapped density obtained in this work is low enough for general MOSFETs, the maximum inversion electron mobility is five times lower than that of the bulk GaN. Therefore, it seems that the low channel mobility in GaN-MOSFETs is mainly attributed by GaN crystallinity and/or coexistence of carriers originated from defect states rather than the oxide and/or interface trapped states. It is expected that higher hole mobilities can be achieved by further improvement of the MOSFETs processing and p-GaN quality.
Materials 2020, 13, x FOR PEER REVIEW 8 of 10 the interface trapped density obtained in this work is low enough for general MOSFETs, the maximum inversion electron mobility is five times lower than that of the bulk GaN. Therefore, it seems that the low channel mobility in GaN-MOSFETs is mainly attributed by GaN crystallinity and/or coexistence of carriers originated from defect states rather than the oxide and/or interface trapped states. It is expected that higher hole mobilities can be achieved by further improvement of the MOSFETs processing and p-GaN quality.

Conclusions
In this work, we have fabricated and evaluated many MOSFET devices based on homoepitaxial GaN using two methods of the selective area regrowth and ion implantation. For the implantation method, the source and drain regions are implanted with Si atoms with 10 nm-thick SiOxNy and photoresist protection layer on the gate regions. For the regrown method, the gate is completely removed and regrown after making the source and drain regions to minimize damages on the gate. Moreover, the semiconductor surface treatments using the combination of physical and chemical treatments prior to the dielectric deposition have been proposed for the GaN-MOSFET's fabrication to reduce the trapped charge density. As a result, all characteristics of MOSFETs fabricated using the regrowth method are better than those of the relative devices fabricated using the ion implantation technique. The electron mobility, transconductance, and subthreshold values in GaN-MOSFETs based on implantation technique are 100 cm 2 /V·s, 14 μs/mm, 500 mV/dec, respectively. Meanwhile, the GaN-MOSFETs fabricated using the regrowth method perform the electron mobility, transconductance, and subthreshold of 120 cm 2 /V·s, 18 μs/mm, 300 mV/dec, respectively. The MOSFETs with the regrown p-GaN gate body show the Ion/Ioff ratio of approximately 4 × 10 7 , which is, to our knowledge, among the best results of GaN-MOSFETs to date. This investigation provides a valuable information for the future work on GaN-MOSFETs for applications of high-power switching devices.