Random Voids Generation and Effect of Thermal Shock Load on Mechanical Reliability of Light-Emitting Diode Flip Chip Solder Joints

To make the light-emitting diode (LED) more compact and effective, the flip chip solder joint is recommended in LED chip-scale packaging (CSP) with critical functions in mechanical support, heat dissipation, and electrical conductivity. However, the generation of voids always challenges the mechanical strength, thermal stability, and reliability of solder joints. This paper models the 3D random voids generation in the LED flip chip Sn96.5–Ag3.0–Cu0.5 (SAC305) solder joint, and investigates the effect of thermal shock load on its mechanical reliability with both simulations and experiments referring to the JEDEC thermal shock test standard (JESD22-A106B). The results reveal the following: (1) the void rate of the solder joint increases after thermal shock ageing, and its shear strength exponentially degrades; (2) the first principal stress of the solder joint is not obviously increased, however, if the through-hole voids emerged in the corner of solder joints, it will dramatically increase; (3) modelling of the fatigue failure of solder joint with randomly distributed voids utilizes the approximate model to estimate the lifetime, and the experimental results confirm that the absolute prediction error can be controlled around 2.84%.


Introduction
As it has advantages of high light efficiency [1], small volume [2], long lifetime [3], rapid response, and being environmentally friendly [4], light emitting diodes (LEDs) have become one of the most popular optoelectronic light sources and have been widely applied in the field of general lighting, displays, and communications, among others [5,6]. To fulfill the requirement of high efficacy, high color rendering, and small size, LED chip-scale packaging (CSP) with the flip chip solder joints has been proposed in recent years [7]. The LED CSP is composed of an GaN-based blue LED chip and a thin phosphor/silicone film adhered to the LED chip by the hot-pressing approach. Compared with traditional LED packaging, the CSP technology helps to shorten the packaging process time and accurately control the film thickness and color consistency [8]. Because the operation

Anand Constitutive Model
The Anand model is mainly used to describe the constitutive relationship of materials at high temperatures. The model uses a single internal variable, which is related to dislocation density, solid solution strengthening, and grain size effect, to describe the macro impedance of plastic flow in the material. It can reflect the deformation behavior that relates to the strain rate and the temperature of viscoplastic materials, the historical effect of strain rate, strain hardening, dynamic recovery, and other characteristics [20,21].
The Anand model uses both the flow function (Equation (1)) and the evolution function (Equation (2)) to unify the creep and rate independent plastic behavior of solder joint, and its flow function is as follows: where . ε p is inelastic strain rate, ξ is stress multiplier, A is pre-exponential factor, Q is activation energy, R is universal gas constant (gas constant is 8.314J/(mol·K)), T is absolute temperature, m is strain rate sensitivity index, s is internal variable, h is strain hardening parameter, and σ is effective stress.
The evolution function is as follows: .
where h 0 is hardening/softening constant; a is strain rate sensitivity of hardening/softening; and B is a transient creep parameter, and its value is as follows: where s * is the saturation value of s at a given temperature and strain rate, which can be expressed as Equation (4): whereŝ and n are the coefficient for saturation value of deformation resistance and strain rate sensitivity, respectively. The deformation impedance is proportional to the equivalent stress: where c is material parameter and can be expressed at a constant strain rate: At a constant temperature and constant strain rate, the material will appear steady state, and saturated stress will appear at this time. The saturated stress can be obtained according to Formulas (4)-(6) and σ * = cs * : At the same time, it can be converted to the stress value as follows: As shown, the Anand constitutive model contains nine parameters, which can be directly entered into the finite element software to characterize the viscoplasticity of the material and carry out stress and strain analysis. The Anand constitutive model parameters of the SAC305 solder joint used in this paper are shown in Table 1.

Fatigue Failure Prediction Model
In this paper, the fatigue failure of a LED flip chip solder joint is predicted using the model proposed by Engelmaier [11]. This model was developed on the basis of the Coffin-Manson equation, mainly considering the influence of temperature parameters and thermal cycling frequency. The formula is shown as follows: In the equation, N f is the failure times of samples, γ is shear strain range of the solder joint ( γ = √ 3 ε, ε is the plastic strain range of the solder joint), ε ' f is the fatigue ductility coefficient, and c is the fatigue ductility index.
where T S is the average temperature of solder joints at each cycle. f is the cycles for thermal shock per day, 1 ≤ f ≤ 1000 cycles/day.

Thermal Shock Test
Owing to the mismatch of thermal expansion coefficients (CTE) between the chip, solder joint, and substrate, the thermal stress will be generated under the thermal cycle loading condition, which results in different deformation behaviors of different materials. As known, the thermal stress in the solder joint changes with the thermal cycling, and the cyclic thermal stress is considered as the fundamental reason for the fatigue failure occurring in the solder joint.
In this study, the blue LED CSPs were selected as research samples in which the blue LED chip was soldered on an aluminum Printed Circuit Board (PCB) substrate through the flip chip technology. As shown in Figure 1a, the chip specification is 2040 type. In the Figure 1b, the electrode pad material of the test sample is gold, the substrate material of the LED chip is sapphire, the solder pad material on the aluminum PCB substrate is copper, and the surface treatment is nickel-plated gold leaching. Figure 1c,d presents the 2D void distribution and 3D morphology of LED CSP solder joints after reflow soldering processing. Referring to the JEDEC thermal shock test standard (JESD22-A106B), the thermal shock test condition selected in this paper is shown in Table 2. The temperature range is −40~150 • C, the conversion time from high temperature to low temperature is 60 s, and the conversion speed is around 38 • C/s. The specific operation procedure of the designed thermal shock ageing test is described as follows: Step I: X-ray imaging was firstly used to detect the void rate and void distribution of all thirty-four samples. Then, six of them, marked as a29-34, were randomly selected and their shear strength of solder joints was measured by the DAGE4000 bond tester. The shear velocity was set as 0.3 mm/s. The remaining twenty-eight samples, numbered as a1-a28, were aged in the thermal shock test chamber (Mode: ESPEC TSG-201S).
Step II: after 400 cycles of aging, the aged samples were checked as to whether they could be lightened or not. If the sample could not be lightened, it would be judged as failed. Otherwise, the crack propagation in solder joints of all test samples was also checked by the X-ray imaging. Then, the shear strengths of seven samples, numbered as a1-a7, were measured.
Step III: the remaining test samples were aged continually and the measurement procedure was the same as the above step II. Figure 2a shows the void rate in solder joints of blue LED CSPs under the −40~150 • C thermal shock ageing test. As shown, the averaged void rates at 0, 400, 800, 1200, and 1600 cycles were recorded as 3.73%, 3.88%, 4.65%, 4.73%, and 5.64%, respectively. Both the mean and variance of void rates grow with increasing of aging cycles, which can be related to the crack propagation occurring during the thermal shock ageing test.  As shown, the averaged shear strength of solder joint decreases with the increase of thermal shock cycles. In this study, an exponential function was assumed to fit the curve of the solder joint's averaged shear strengths versus ageing cycles. As the uncertainties in both voids measurement and shear force measurement are large, the relationship between the void ratio increase and shear force decrease is not clearly matched. According to some previous studies [29][30][31], the intermetallic compounds (IMCs) at the interfaces between the solder joint with electrode pad and substrate can determine the shear strength of the solder joint. A complicated competition between voids and IMC is assumed to occur during the thermal shock ageing test, in which the voids generation will limit the growth of the IMC layer [31], and the growth of the IMC layer can change the composition of the solder joint, resulting in cracks and more voids [29]. In addition, when the shear strength dropped to 15% of the initial value, the samples were assumed as failed in this study. According to the fitting results of measurement shear force data, the fatigue failure lifetime of the solder joint in this experiment, t f , can be estimated to be 5347 cycles.

Three-Dimensional (3D) Modeling
In this section, the CATIA 3D modeling software was firstly used for the modeling of LED CSP, as described in Figure 1. In the simplified model, the solder pad and surface coating of LED chip were neglected. The simplified LED model includes the LED chip, SAC305 solder joint, and substrate, whose materials are considered as isotropic. The LED chip and substrate are considered as homogeneous bodies, and the model is a centrally symmetric structure. Figure 3a is the 3D model of the LED blue light chip with solder joints and Figure 3b is the X-ray image of the solder joints.
The geometric dimensions of components in the 3D model are listed in Table 3. Among them, the chip size is 1 × 0.5 × 0.14 mm. The origin of modeling and simulation is located in Figure 3a, the XY plane of coordinate system is coplanar with the bottom surface of solder joints, the XZ plane of coordinate system is coplanar with the front surface of LED chip, and the solder joint is symmetrical in the YZ plane of coordinate system.  According to the X-ray image of the solder joint shown in Figure 3b, the void diameters and the void center coordinates X and Y can be extracted. Table 4 shows the numbers of test sample measured at each test cycle and the averaged void numbers and void rates corresponding to each solder joint. Herein, the right solder joint in Figure 3b is selected to explain the statistical method used in accounting the location and the diameter of voids. In this study, the statistical functions were used to describe the distributions of void diameter and void center position coordinates. Specifically, the lognormal distribution and normal distribution were used to fit the void diameters and X-Y coordinates, respectively. Figure 4 shows the statistical curve fitting results of void diameters and locations after 800 test cycles.  On the basis of the above statistical information collected from the experiment, this section establishes the random voids in the 3D model of solder joints; the procedure is described as follows: Step I: generate a random void diameter in the XY plane using the lognormal distribution extracted in Figure 4a; then, set the boundary condition R < X < 0.425-R; R < Y < 0.5-R to limit the range of X and Y; next, randomly generate the value of X and Y according to the fitted normal distribution curves shown in Figure 4b,c. Then, the first void is established.
Step II: the idea of generating the second void is the same as the first one, but the bound condition, in which the sum of radius of the two voids must be larger than the distance between the two centers, should be satisfied.
Step III: the third void is generated to ensure no interference with the above generated two voids until the total voids in the XY plane are generated.
Step IV: consider the void position in the Z axis. As the X-ray image of voids used in this study is a 2D image, the Z coordinates cannot be determined. Considering that the thickness of solder joint is thin, the void position in Z axis is assumed to be randomly distributed within solder joints.
Step V: Python program was finally used to achieve the above process. The constraint condition is that the average error of each void rate between modeling and X-ray measurements should be controlled within ±0.1.

Mechanical Strength Analysis
After completing the construction of the 3D model for LED CSP considering random voids, this section investigates the mechanical strength of solder joints based on the finite element simulation. The first principal stress distribution was simulated to characterize the mechanical strength of solder joints. In the simulation process, the fixed constraint was imposed on the bottom surface of the substrate, and a shear force with 20 N was applied to the side surface of the LED chip with the size of 1 × 0.14 mm. The finite element model was constructed using the SOLID185 element. Table 5 lists the material properties of components used in the 3D model. According to the 3D modeling procedure, five sets of random voids were simulated in the 3D models at each test cycle. Figure 5 shows one of the first principal stress distributions of solder joints at 0 cycle, which indicates that the stress is always concentrated near the random void in solder joints. Table 6 summarizes the simulated first principal stresses in solder joints and their mean values at each thermal cycle. Figure 6 shows the simulated first principle stress of solder joints after the thermal shock test. As indicated, the first principal stress of the solder joint decreases sharply in the interval of 0~400 cycles and remains relatively constant after that.   Next, we analyzed the effect of void size and location on the first principal stress distribution of the solder layer. As shown in Figure 5, there is a large void located in the right solder joint; its coordinates of X and Y are 0.4623 mm and 0.0966 mm, respectively, and its radius is 0.0449 mm. As shown in Figure 7, when its location changes from X = 0.4623 mm to 0.36 mm, the simulated first principal stress decreases from 882.7 MPa to 264 MPa. This result indicates that, when the void diameter is larger than the solder joint's thickness (0.05 mm), which means it is a through-hole in solder joints, the first principle stress of the solder joint can be obviously influenced by the void position.

Heat Dissipation Analysis
This section investigates the heat dissipation performance of a solder joint with randomly distributed voids using the finite element simulation. The 3D simulation model is the same as the above mechanical simulation model. The finite element model was constructed by SOLID90 element and the intelligent grid division method. The convection coefficient between the model and air is set as 10 W/(m 2 · • C), the ambient temperature is 25 • C, and the lower surface of the substrate is controlled at 30 • C. The electric power of the LED blue light chip is 0.6 W and the volume of the chip is 0.07 mm 3 . The thermal power of the chip is estimated as 0.5334 W and the heat power of the unit volume is calculated as 7.62 (K/mm 3 ). As required for the simulation of heat dissipation, Table 7 lists the thermal conductivities of all components used in the 3D model.  Figure 8a displays the temperature distribution of solder joints in the one LED CSPs at the 0 cycle condition. It is shown that the highest temperature of the solder joint is always located in the middle upper surface of solder joints and the lowest temperature is located at the outer corner of their bottom surfaces. Figure 8b is a Z axis cross section of the solder joints shown in Figure 8a, where the Z coordinate value of this plane is 0.025 mm; it also shows the temperature decreases from inside to outside of the solder joints. To investigate the void effect on the heat dissipation of solder joints, the temperature distributions of solder joints under each thermal shock test condition were simulated by taking the void rates into consideration, and then the thermal resistances of solder joints during thermal shock test were estimated according to Equation (11). Table 8 lists the temperature difference (T max − T min ) of each solder joint and their averaged values at different ageing times. The thermal resistance can be expressed as follows: where T max and T min is the lowest temperature and highest temperature of the solder joint, respectively, and P is the thermal power. On the basis of Equation (11), the averaged thermal resistances at different ageing times are obtained and shown in Table 9. The simulated thermal resistances are demonstrated in Figure 9, in which we can see that, as the void rates grow with the increasing of aging cycles, the mean and variance of thermal resistances of the solder joint show the same increasing trend as void rates.

Fatigue Lifetime Estimation
By using the Anand and Coffin-Manson models described in Section 2.2., the fatigue failure simulation and lifetime prediction for solder joints of LED CSPs under thermal shock test are studied in this part.
Firstly, the a22-a28 samples that undergo the 1600 cycles thermal shock test were selected as the research objects. The diameter of voids and the X and Y coordinates in samples were calculated based on the measurements at the 0 cycle condition. The void measurement results are list in Table 10. The statistical curve-fitting and random void generation were kept consistent with the above methods used in the mechanical and thermal performance analysis. The lognormal distribution curve-fitting of void diameters and the normal distribution curve-fittings of X and Y coordinates are shown in Figure 10.
Then, the finite element model of the solder joint was constructed by the VISCO107 element and the finite element models of PCB substrate and LED chip were constructed by the SOLID95 element. Table 11 shows the material parameters of the PCB substrate and LED chip. Considering that the thermal shock has little effect on the PCB substrate and LED chip, the material parameters used in the finite element simulation were assumed as constant. However, the temperature-dependent material parameters of the solder joint are shown in Table 12. The zero displacement constraint in the XYZ three directions was applied to the bottom surface of the PCB substrate. The thermal cycling load remained consistent with the ambient temperature. The reference temperature was set at 300 K.  Next, the fatigue failure simulation of solder joints without voids was firstly conducted with the Anand constitutive model. The simulation result is shown in Figure 11a, in which the maximum Von Mises plastic strain was generated at the bottom outer corner of the solder joint, which is close to the PCB substrate. The time history curve of the Von Mises plastic strain at the maximum strain node is shown in Figure 11b. The plastic strain range ε of solder joints without voids can be estimated as 0.006128. When it was inserted into the Coffin-Manson model (Equation (9)), the fatigue failure cycle of solder joints without voids, N f , was calculated as 6307 cycles. The fatigue ductility index of SAC305, ε ' f , used in the Coffin-Manson model, is 0.24 [11]. The average temperature under thermal shock test was estimated as follows: where T max and T min represent the maximum and minimum temperature, respectively. The frequency of the thermal cycle f = 65.45 (cycle/d), so c = −0.40366. Moreover, the Von Mises plastic strain was also simulated for the solder joints with randomly distributed voids. The Von Mises plastic strain simulation result from one of the test samples is shown in Figure 12a. The strain range was extracted from the same node of the solder joint model without void, and its Von Mises plastic strain time history curve is plotted in Figure 12b. Herein, according to the statistical curve-fitting results shown in Figure 1, we modeled 20 solder joints with the same void rate, but randomly generated voids. Their fatigue failure cycles were estimated using the Coffin-Manson model and then fitted by a two-parameter Weibull distribution (Equation (13)), as shown in Figure 13. According to Equation (14), the mean fatigue failure cycle of solder joints with randomly distributed voids, Mean Time to Failure (MTTF), was estimated to be around 5499 cycles.
where shape parameter β = 7.225 and scale parameter η = 5872.52 cycles were estimated with the maximum likelihood (ML) estimation. Г is the gamma function.  In a short summary, firstly, compared with the experiment result shown in Figure 3, the fatigue lifetime prediction absolute error, e %, is calculated based on Equation (15), around 2.84%, which means a high accuracy of fatigue failure prediction by inserting the 3D randomly distributed void model into the Anand and Coffin-Manson models can be achieved in this study. Secondly, by comparing the fatigue life estimation results for two cases with and without voids, it is found that the void will decrease the lifetime of solder joints. Therefore, improving the soldering process of LED CSP technology to reduce voids in solder joint is necessary for guaranteeing its high reliability.

Conclusions
To investigate the reliability of the SAC305 solder joint used in a LED CSP, the 3D modeling of solder joints with randomly distributed voids was firstly established in this study with statistical methods. The mechanical strength and heat dissipation performance of solder joints considering the effect of random voids were then investigated with finite element simulations. Finally, the thermal shock experiment and simulation were designed to evaluate the fatigue failure of solder joints in LED CSP. The results indicate the following: (1) after a long-term thermal shock test, the void rate of solder joints increases and its shear strength degenerates with an exponential trend; (2) as stress is always concentrated near the voids, the first principle stress of a solder joint is obviously influenced by the void position, especially when the through-hole voids are formed at the corner of solder joints; (3) when the void rate grows during the thermal shock aging test, the thermal resistance of solder joint also increases at the same time; (4) the formation of voids in solder joints always affects their reliability. The proposed lifetime estimation method by inserting the 3D randomly distributed void model into the Anand and Coffin-Manson models can increase the accuracy of fatigue failure prediction for solder joints in LED CSP.