One-Volt, Solution-Processed Organic Transistors with Self-Assembled Monolayer-Ta2O5 Gate Dielectrics

Low-voltage, solution-processed organic thin-film transistors (OTFTs) have tremendous potential to be key components in low-cost, flexible and large-area electronics. However, for these devices to operate at low voltage, robust and high capacitance gate dielectrics are urgently needed. Herein, the fabrication of OTFTs that operate at 1 V is reported. These devices comprise a solution-processed, self-assembled monolayer (SAM) modified tantalum pentoxide (Ta2O5) as the gate dielectric. The morphology and dielectric properties of the anodized Ta2O5 films with and without n-octadecyltrichlorosilane (OTS) SAM treatment have been studied. The thickness of the Ta2O5 film was optimized by varying the anodization voltage. The results show that organic TFTs gated with OTS-modified tantalum pentoxide anodized at 3 V (d ~7 nm) exhibit the best performance. The devices operate at 1 V with a saturation field-effect mobility larger than 0.2 cm2 V−1 s−1, threshold voltage −0.55 V, subthreshold swing 120 mV/dec, and current on/off ratio in excess of 5 × 103. As a result, the demonstrated OTFTs display a promising performance for applications in low-voltage, portable electronics.


Introduction
Organic thin-film transistors (OTFTs) have been attracting interest owing to their developing applications in low-cost, light-weight, and flexible electronic devices such as active-matrix displays [1], radio frequency identification tags [2], and bio and chemical sensors [3]. Over the years, progress in semiconducting materials and fabrication techniques has dramatically increased the charge mobility in these devices to well above 1 cm 2 V −1 s −1 [4,5]. However, in general, these devices operate with relatively high gate voltages (V G ≥ 3 V) which hinders their integration in low-voltage, portable applications [6]. In order to enable organic TFTs that operate below 3 V and deliver high output current, the use of ultra-thin, high dielectric constant (high-κ) materials such as HfO 2 , Ta 2 O 5 , TiO 2 , ZrO 2 , Al 2 O 3 , Y 2 O 3 , CeO 2 [7][8][9] is required. In particular, tantalum pentoxide (Ta 2 O 5 ) is a very promising candidate due to the high dielectric constant in the bulk (κ bulk~2 7) and as a thin-film (κ thin-film~2 0). These values are at least two times larger than that of Al 2 O 3 (κ bulk~9 ) [10] and five times larger than that of SiO 2 (κ bulk~3 .9). As a result, Ta 2 O 5 has been abundantly used in electrolytic capacitors, DRAM devices,

Experimental Section
To optimise the dielectric performance of Ta 2 O 5 and Ta 2 O 5 /OTS films, metal-insulator-metal (MIM) capacitors were fabricated. First, a 100 nm of Ta layer was deposited through a shadow mask by radio frequency (r.f.) magnetron sputtering to serve as the gate electrode. Sputtering was achieved by using a 2-inch diameter Ta target (99.99%) in Ar with a total pressure of 0.5 Pa. Next, samples were anodized in 1 mM of citric acid (≥ 99.5%, Sigma-Aldrich, St. Louis, MO, USA) using 99.99% pure Au wire as the cathode electrode as shown in Figure 1a. To form tantalum oxide films of various thicknesses, anodization voltages (V A ) of 40, 30, 20, 10, 5 and 3 V with constant current density (0.01 mA/cm 2 ) were applied to the anode by Keithley 2400 Source Meter. The process was continued until the ionic current density dropped to 0.005 mA/cm 2 . The variation of anodization voltage and current vs. time is depicted in Figure 1b. Based on the anodization ratio of Ta reported in the literature [19] ([c] Ta = 2.2 nm/V), a 3 V anodized Ta should result in an approximately~6.6 nm thick Ta 2 O 5 layer. Some of the as-prepared Ta/Ta 2 O 5 substrates were treated with O 2 plasma for 2 min and then immersed in a freshly prepared 1 mM solution of OTS in anhydrous toluene at room temperature for 30 min. Afterwards, the substrates were removed from the solution and rinsed thoroughly and without interruption with pure toluene in order to get rid of the excess of unreacted OTS. The treated substrates were thereafter annealed on a hot plate at 120 • C for 1 h under a flow of dry N 2 . To obtain MIM capacitors, 50 nm thick Au electrodes were deposited onto the prepared Ta/Ta 2 O 5 and Ta/Ta 2 O 5 /OTS films. The electrical characterization of the fabricated capacitors was carried out using an Agilent E4980A LCR meter. For the duration of the measurements, 1 V bias was applied to the bottom Ta electrode and the top Au electrode was grounded. Organic TFTs were fabricated in the bottom gate, top contact structure on an ultra-flat, quartz-coated glass substrate (S151, Ossila, Sheffield, UK). Poly(3,6-di(2-thien-5-yl)-2,5-di (2-octyldodecyl)-pyrrolo [3,4-c] pyrrole-1,4-dione) thieno [3,2-b] thiophene) (DPPDTT) and poly(methyl methacrylate) (PMMA) and their blend solutions were prepared according to the procedures reported elsewhere [20]. In short, the DPPDTT-PMMA blend solution was prepared by separately dissolving 0.5 wt% DPPDTT and 0.5 wt% of PMMA in 1,2-dichlorobenzene (DCB) and subsequently mixed in a 7:3 ratio. Afterwards, the blend was stirred until completely mixed. The blend was then spin-coated at 2000 rpm for 2 min on substrates pre-heated at 100 • C. Subsequently, the deposited films were annealed at 100 • C for 30 min to 1 h under N 2 flow. Finally, a 100 nm thick layer of 99.99% Au was thermally evaporated through shadow masks to serve as a source and drain electrodes. Some of the as-prepared Ta/Ta2O5 substrates were treated with O2 plasma for 2 minutes and then immersed in a freshly prepared 1 mM solution of OTS in anhydrous toluene at room temperature for 30 minutes. Afterwards, the substrates were removed from the solution and rinsed thoroughly and without interruption with pure toluene in order to get rid of the excess of unreacted OTS. The treated substrates were thereafter annealed on a hot plate at 120 °C for 1 h under a flow of dry N2. To obtain MIM capacitors, 50 nm thick Au electrodes were deposited onto the prepared Ta/Ta2O5 and Ta/Ta2O5/OTS films. The electrical characterization of the fabricated capacitors was carried out using an Agilent E4980A LCR meter. For the duration of the measurements, 1 V bias was applied to the bottom Ta electrode and the top Au electrode was grounded. Organic TFTs were fabricated in the bottom gate, top contact structure on an ultra-flat, quartz-coated glass substrate (S151, Ossila, Sheffield, UK). Poly(3,6-di(2-thien-5-yl)-2,5-di (2-octyldodecyl)-pyrrolo [3,4-c] pyrrole-1,4-dione) thieno [3,2-b] thiophene) (DPPDTT) and poly(methyl methacrylate) (PMMA) and their blend solutions were prepared according to the procedures reported elsewhere [20]. In short, the DPPDTT-PMMA blend solution was prepared by separately dissolving 0.5 wt% DPPDTT and 0.5 wt% of PMMA in 1,2-dichlorobenzene (DCB) and subsequently mixed in a 7:3 ratio. Afterwards, the blend was stirred until completely mixed. The blend was then spin-coated at 2000 rpm for 2 min on substrates pre-heated at 100 °C. Subsequently, the deposited films were annealed at 100 °C for 30 min to 1 h under N2 flow. Finally, a 100 nm thick layer of 99.99% Au was thermally evaporated through shadow masks to serve as a source and drain electrodes. The channel width (W) and length (L) were 1 mm and 30 μm, respectively. The electrical characterization of the fabricated OTFTs was carried out using an Agilent E5270B semiconductor analyser (Santa Clara, CA, USA) and E4980A LCR meter (Keysight, Santa Rosa, CA, USA) at room temperature. The field-effect mobility is calculated by applying a linear fit to ID 1/2 vs VG in the saturation regime using Equation (1): where VG is the gate voltage, VT is the threshold voltage, Ci is the gate capacitance density, is saturation field-effect mobility, and W and L are channel width and length, respectively. All electrical measurements were done in ambient conditions in an electrically shielded, dark box. The channel width (W) and length (L) were 1 mm and 30 µm, respectively. The electrical characterization of the fabricated OTFTs was carried out using an Agilent E5270B semiconductor analyser (Santa Clara, CA, USA) and E4980A LCR meter (Keysight, Santa Rosa, CA, USA) at room temperature. The field-effect mobility is calculated by applying a linear fit to I D 1/2 vs V G in the saturation regime using Equation (1):

Results and Discussions
where V G is the gate voltage, V T is the threshold voltage, C i is the gate capacitance density, µ SAT is saturation field-effect mobility, and W and L are channel width and length, respectively. All electrical measurements were done in ambient conditions in an electrically shielded, dark box.

Results and Discussions
The presence of anodized tantalum oxide films was confirmed by X-ray photoelectron spectroscopy (XPS, Axis Ultra Hybrid, Kratos Analytical, Manchester, UK). A thick, i.e., thicker than the sampling depth of XPS, oxide was observed on the anodized region of the samples (see Figure 2a and Figures S1-S3 in the Supplementary Materials). By analysing the area of the Ta 4f and O 1s peaks, the Ta and O ratio was found to be nearly 2:5 confirming that tantalum pentoxide (Ta 2 O 5 ) was successfully prepared through anodization. Also, as shown in Figure 2a, the normalized O 1s peak fit indicates that the oxide formation on the anodized regions is consistent with the peak fitting analysis of the Ta 4f regions. To investigate the surface morphology of the anodized Ta 2 O 5 , atomic force microscope (AFM, Multimode, Bruker UK, Coventry, UK) images of the fabricated films have been taken. Figure 2b,c show surface topography of both untreated and OTS-treated Ta 2 O 5 films, respectively. The RMS roughness of untreated Ta 2 O 5 film is 2.5 nm and the OTS-treated Ta 2 O 5 1.3 nm. The tantalum oxide grown by anodization appears to be homogenous, uniform and fairly smooth. However, a more detailed AFM topographical analysis shows that OTS surface modification has made the oxide surface somewhat smoother when compared with as-prepared Ta 2 O 5 films. The presence of anodized tantalum oxide films was confirmed by X-ray photoelectron spectroscopy (XPS, Axis Ultra Hybrid, Kratos Analytical, Manchester, UK). A thick, i.e., thicker than the sampling depth of XPS, oxide was observed on the anodized region of the samples (see Figure 2a and Figures S1-S3 in the Supplementary Materials). By analysing the area of the Ta 4f and O 1s peaks, the Ta and O ratio was found to be nearly 2:5 confirming that tantalum pentoxide (Ta2O5) was successfully prepared through anodization. Also, as shown in Figure 2a, the normalized O 1s peak fit indicates that the oxide formation on the anodized regions is consistent with the peak fitting analysis of the Ta 4f regions. To investigate the surface morphology of the anodized Ta2O5, atomic force microscope (AFM, Multimode, Bruker UK, Coventry, UK) images of the fabricated films have been taken. Figure 2b,c show surface topography of both untreated and OTS-treated Ta2O5 films, respectively. The RMS roughness of untreated Ta2O5 film is 2.5 nm and the OTS-treated Ta2O5 1.3 nm. The tantalum oxide grown by anodization appears to be homogenous, uniform and fairly smooth. However, a more detailed AFM topographical analysis shows that OTS surface modification has made the oxide surface somewhat smoother when compared with as-prepared Ta2O5 films.  Figure 3 illustrates capacitance density, dielectric loss, leakage current and capacitance-voltage curves of anodized Ta2O5 films that were obtained at different anodization voltages, i.e., 40, 30, 20, 10, 5 and 3 V. In order to verify the measured values and test the devices' fabrication reproducibility, all measurements were carried out on 20 randomly chosen devices out of the 100 different capacitors with Ta/Ta2O5/Au structure (cf. inset of Figure 3a). Figure 3 shows the response of one typical device out of the 20 studied devices. Figure 3a depicts the capacitance density vs. frequency from 100 Hz to 100 kHz for the corresponding anodization voltages. As can be seen, for the dielectric thicknesses  illustrates capacitance density, dielectric loss, leakage current and capacitance-voltage curves of anodized Ta 2 O 5 films that were obtained at different anodization voltages, i.e., 40, 30, 20, 10, 5 and 3 V. In order to verify the measured values and test the devices' fabrication reproducibility, all measurements were carried out on 20 randomly chosen devices out of the 100 different capacitors with Ta/Ta 2 O 5 /Au structure (cf. inset of Figure 3a). Figure 3 shows the response of one typical device out of the 20 studied devices. Figure 3a depicts the capacitance density vs. frequency from 100 Hz to 100 kHz for the corresponding anodization voltages. As can be seen, for the dielectric thicknesses greater thañ 22 nm (V A = 10 V), capacitance density is relatively constant across the studied frequency range. As the Ta 2 O 5 thickness decreases, it appears that the capacitors become unstable at both ends of the chosen frequency spectrum. Capacitors fabricated with Ta 2 O 5 anodized at 40, 30, and 20 V exhibited an average capacitance density of 380, 450, and 700 nF/cm 2 at 1 kHz, respectively. The maximum standard deviation of the measured capacitance values for these capacitors was ±20 nF/cm 2 .  On the other hand, the capacitors with anodic Ta2O5 prepared at 10, 5 and 3 V show much higher capacitances but also significantly higher leakage currents and dielectric losses, especially for VA ≤ 5 V. As a result, we conclude that the pristine Ta2O5 films anodized at or below 10 V (d ~ 22 nm) are unsuitable for practical applications. Correspondingly, the dissipation factor (DF) measured on capacitors using Ta2O5 anodized at various voltages is depicted in Figure 3b. For the simplest actual model, i.e., equivalent series resistance in series with the capacitance that neglects equivalent series inductance and insulation resistance, DF is the ratio of equivalent series resistance (ESR) and capacitive reactance (Xc), as written in Equation (2) [21]: Ideally, for a given capacitor DF should be zero, but practically it consists of a negligible loss due to resistive characteristics. As shown in Figure 3b, the capacitors with 40, 30, and 20 V anodized On the other hand, the capacitors with anodic Ta 2 O 5 prepared at 10, 5 and 3 V show much higher capacitances but also significantly higher leakage currents and dielectric losses, especially for V A ≤ 5 V. As a result, we conclude that the pristine Ta 2 O 5 films anodized at or below 10 V (d~22 nm) are unsuitable for practical applications. Correspondingly, the dissipation factor (DF) measured on capacitors using Ta 2 O 5 anodized at various voltages is depicted in Figure 3b. For the simplest actual model, i.e., equivalent series resistance in series with the capacitance that neglects equivalent series inductance and insulation resistance, DF is the ratio of equivalent series resistance (ESR) and capacitive reactance (Xc), as written in Equation (2) [21]: Ideally, for a given capacitor DF should be zero, but practically it consists of a negligible loss due to resistive characteristics. As shown in Figure 3b, the capacitors with 40, 30, and 20 V anodized Ta 2 O 5 display a minimal DF that is close to zero. However, as the anodization voltage decreases below 20 V, DF becomes larger and the leakage currents through the anodic dielectric layer start to be appreciable (cf. Figure 3b,c). Accordingly, as the Ta 2 O 5 dielectric thickness decreases even further (V A = 5 and 3 V) the leakage current through the dielectric becomes very large. In particular, capacitors with the thinnest anodic Ta 2 O 5 , i.e., anodized at 3 V, exhibit the largest leakage current density (J L ) 10 −3 A/cm 2 at 1 V. The same electronic behaviour of the anodized Ta 2 O 5 can also be seen in the C-V characteristics of the corresponding capacitors shown in Figure 3d, where high leakage currents reduce the voltage across the capacitors resulting in a lower electric field and lower capacitance at the positive end of the C-V curves. This is in contradiction with an ideal case, where a capacitor shows a flat capacitance-voltage characteristic which guarantees reliable and stable device performance. Nevertheless, thicker layers of Ta 2 O 5 show flat and stable electrical behaviour across the chosen voltage characterization range. Based on the abovementioned dielectric characteristics, it appears that the minimum anodization voltage of tantalum for capacitor and TFT applications is 20 V, which corresponds to approximately 45 nm of Ta 2 O 5 . Indeed, the J L for capacitors with 45 nm Ta 2 O 5 layers is well below the maximum allowable value for TFT leakage current density (i.e., 10 −6 A/cm 2 ) and is measured to be 10 −7 A/cm 2 at 1 V. Figure 4a shows the structure of the fabricated bottom-gate, top-contact Ta/(45 nm Ta 2 O 5 )/DPPDTT-PMMA/Au TFTs on a glass substrate (V A = 20 V). Typical output and transfer characteristics of the fabricated transistors are shown in Figure 4b, c, respectively. As can be seen in Figure 4b, the drain current displays clear linear, pinch-off and saturation regions for all applied gate voltages.
The devices operate at 1 V with a saturation field-effect mobility of 0.02 cm 2 V −1 s −1 , threshold voltage −0.35 V, subthreshold swing 210 mV/dec, and current on/off ratio~10 3 . This transistor performance is comparable to the previously reported organic TFTs that used SAM-modified, anodized Al 2 O 3 [22].
To see if the dielectric SAM modification strategy also results in improved transistor characteristics of the TFTs with anodized Ta 2 O 5 , DPPDTT-PMMA TFTs with OTS-modified tantalum pentoxide have been fabricated. OTS is one of the most used SAMs in organic transistors. It has been shown that OTS significantly improves dielectric/semiconductor interface by passivating the gate insulator surface that leads to the reduction of charge carrier traps, and as result, to higher charge carrier mobility [23,24]. During silanization, OTS molecules are attached to the dielectric surface through the chemical reaction of -SiCl with -OH groups on the metal oxide surface. This results in -Si-O-M structures. The other two -SiCl bonds of the OTS molecule react with proximate OTS molecules which forms a cross-linked monolayer. The OTS-treatment of the Ta 2 O 5 layer inevitably results in a thicker overall dielectric layer, and hence decreases the overall areal capacitance of the dielectric film. The anodized Ta 2 O 5 layer should be thin enough to provide the minimum required capacitance and leakage to operate the OTFTs at low voltage. Taking into account that the Ta native oxide thickness is about 3.5 nm [25], it is believed that to suppress the effect of the native oxide on the dielectric properties of Ta 2 O 5 the thickness of the anodized Ta should be at least 3.5 nm thick. As shown in Figure 3a,c, an untreated Ta 2 O 5 layer anodized at 3 V (d~7 nm) exhibits a large enough areal capacitance to be able to operate DPPDTT-PMMA TFTs at 1 V. However, the very high leakage current density of these thin layers would lead to poor field-effect transistor characteristics if used as prepared. and is measured to be 10 -7 A/cm 2 at 1 V. Figure 4a shows the structure of the fabricated bottom-gate, top-contact Ta/(45 nm Ta2O5)/DPPDTT-PMMA/Au TFTs on a glass substrate (VA = 20 V). Typical output and transfer characteristics of the fabricated transistors are shown in Figure 4b, c, respectively. As can be seen in Figure 4b, the drain current displays clear linear, pinch-off and saturation regions for all applied gate voltages.    Figure 5a, the capacitance density of OTS-treated Ta 2 O 5 is notably reduced from 2700 nF/cm 2 for bare Ta 2 O 5 film to approximately 680 nF/cm 2 . This is due to the addition of the OTS layer which leads to a thicker dielectric film and correspondingly smaller overall capacitance density because of two dielectric layers in series. Nonetheless, capacitance density curves for OTS-treated Ta 2 O 5 are highly stable over a wide range of frequencies. The dielectric loss (Figure 5b) for OTS-treated Ta 2 O 5 shows negligible variation (less than 0.1) confirming a low defect density in the OTS-treated Ta 2 O 5 films. As shown in Figure 5c, leakage current density for OTS-treated Ta 2 O 5 is approximately 2 × 10 −7 A/cm 2 at ±1 V; this is reduced by circa five orders of magnitude at −1 V and circa one order of magnitude at +1 V when compared to films of untreated Ta 2 O 5 of comparable thickness. The leakage current of the OTS-treated Ta 2 O 5 is somewhat asymmetric and slightly lower for negative voltages. This is very likely caused by the use of electrodes with different work functions and differences in the roughness of the Ta/Ta 2 O 5 and Ta 2 O 5 /OTS interfaces [26]. In addition, as illustrated in Figure 5d, in contrast to untreated Ta 2 O 5 , OTS surface modification has improved the stability of the capacitance density over the studied voltage range (−1 V to 1 V) and led to almost ideally flat C-V curves. To test if the optimized, OTS-modified Ta2O5 layers result in well-working 1 V devices, glass/Ta/(7 nm Ta2O5)/OTS/DPPDTT-PMMA/Au OTFTs have been fabricated (VA = 3 V). Typical output and transfer characteristics of the fabricated transistors are shown in Figure 6b, c, respectively. The optimized devices operate at 1 V with virtually no hysteresis, the saturation field-effect mobility is 0.22 cm 2 V −1 s −1 , the threshold voltage −0.55 V, subthreshold swing 120 mV/dec, and the current on/off ratio is in excess of 5 x 10 3 . Additionally, the leakage current at −1 V is measured to be less than 1 nA at all applied biases. The calculated field-effect mobility for these devices is > 0.2 cm 2 V −1 s −1 , ten times larger than the analogous DPPDTT-PMMA TFTs fabricated on bare Ta2O5. It is believed that charge carrier mobility in TFTs is directly affected by the interfacial trap density [27]. Trap density in thin-film transistors can be calculated using Equation (3): where CG is the gate capacitance density, q is the electron charge, k is the Boltzmann's constant, T is the temperature, and SS is subthreshold swing. Nit is calculated to be 1.09 × 10 13 cm −2 and 4.2 × 10 12 cm −2 for OTFTs using 20 V, untreated Ta2O5 and 3 V, OTS-treated Ta2O5, respectively. The reduction of trap density confirms that the OTS layers shield the active layer from traps at the anodic Ta2O5/DPPDTT-PMMA interface. Table 1 compares the key figures-of-merit of the 1 V OTFTs fabricated in this work in comparison with one-volt organic TFTs we reported previously [22,28,29]. As can be seen, the gate capacitance density of the developed OTS-treated Ta2O5 dielectric layer used  Figure 6b,c, respectively. The optimized devices operate at 1 V with virtually no hysteresis, the saturation field-effect mobility is 0.22 cm 2 V −1 s −1 , the threshold voltage −0.55 V, subthreshold swing 120 mV/dec, and the current on/off ratio is in excess of 5 × 10 3 . Additionally, the leakage current at −1 V is measured to be less than 1 nA at all applied biases. The calculated field-effect mobility for these devices is > 0.2 cm 2 V −1 s −1 , ten times larger than the analogous DPPDTT-PMMA TFTs fabricated on bare Ta 2 O 5 . It is believed that charge carrier mobility in TFTs is directly affected by the interfacial trap density [27]. Trap density in thin-film transistors can be calculated using Equation (3):

Conclusions
In conclusion, solution-processed, low threshold voltage organic thin-film transistors that can be operated at 1 V have been demonstrated. The low operational voltage was achieved by using extremely thin (7 nm), anodized Ta 2 O 5 films that were modified by the application of an OTS SAM. The optimized DPPDTT-PMMA TFTs display threshold voltages around −0.55 V, low subthreshold slopes 120 mV/dec, operate with negligible hysteresis and possess average saturated field-effect mobility in excess of 0.2 cm 2 V −1 s −1 at 1 V. This approach has a high potential to enable the design of stable, ultra-low voltage organic semiconductor circuitry in a highly reproducible manner.
Supplementary Materials: The following are available online at http://www.mdpi.com/1996-1944/12/16/2563/s1, Figure S1: Normalized peak fitted Ta 4d spectra for both control and anodized regions of the sample showing only Ta oxide in the anodized region relative to a metal/oxide mixture in the control region. Figure S2: Normalized O 1s spectra for both control and anodized regions. Figure S3: Normalized Ta 4f spectra for both control and anodized regions.