Ge2Sb2Te5 p-Type Thin-Film Transistors on Flexible Plastic Foil

In this work, we show the performance improvement of p-type thin-film transistors (TFTs) with Ge2Sb2Te5 (GST) semiconductor layers on flexible polyimide substrates, achieved by downscaling of the GST thickness. Prior works on GST TFTs have typically shown poor current modulation capabilities with ON/OFF ratios ≤20 and non-saturating output characteristics. By reducing the GST thickness to 5 nm, we achieve ON/OFF ratios up to ≈300 and a channel pinch-off leading to drain current saturation. We compare the GST TFTs in their amorphous (as deposited) state and in their crystalline (annealed at 200 °C) state. The highest effective field-effect mobility of 6.7 cm2/Vs is achieved for 10-nm-thick crystalline GST TFTs, which have an ON/OFF ratio of ≈16. The highest effective field-effect mobility in amorphous GST TFTs is 0.04 cm2/Vs, which is obtained in devices with a GST thickness of 5 nm. The devices remain fully operational upon bending to a radius of 6 mm. Furthermore, we find that the TFTs with amorphous channels are more sensitive to bias stress than the ones with crystallized channels. These results show that GST semiconductors are compatible with flexible electronics technology, where high-performance p-type TFTs are strongly needed for the realization of hybrid complementary metal-oxide-semiconductor (CMOS) technology in conjunction with popular n-type oxide semiconductor materials.


Introduction
Flexible electronics have received increased attention in the last years, promising great innovations in emerging display technology [1], healthcare [2][3][4], human-machine interfaces [4,5], textiles [6] and flexible sensor systems for Internet-of-Things (IoT) applications [7]. Especially, the latter requires high-frequency operation (13.56 MHz) to enable wireless data transmission via radio frequency identification (RFID) and near-field communication (NFC). Oxide semiconductor based thin-film transistors (TFTs) offer large carrier mobilities (>10 cm 2 /Vs), which enable these high frequencies, and additionally provide low off-currents and large area uniformity [8][9][10][11]. Thus, recent reports have shown that unipolar circuit technology based on oxide semiconductors can be employed for NFC and RFID applications [12,13]. However, the use of complementary metal-oxide-semiconductor (CMOS) technology could dramatically improve the power consumption, gain, noise immunity and circuit design of these systems [14].
In this work, we study GST TFTs on a flexible substrate and demonstrate performance improvements through downscaling of the GST thickness to 5 nm. For this GST thickness, we find ON/OFF ratios up to ≈300, which represents a 15-fold improvement compared to prior work. The thickness reduction also leads to a pinch-off of the semiconductor channel, resulting in a saturating I D in TFT output characteristics. Furthermore, we compare the device characteristics before and after thermal annealing above the crystallization temperature, which leads to an increased conductivity and mobility for GST thin-films ≥10 nm.

Device Fabrication
The bottom gate TFTs were processed on a flexible 50 µm thick polyimide substrate. First, the substrate was cleaned in isopropanol and acetone by sonication, followed by a baking at 200 • C in an air oven for 24 h. Then, a SiN X buffer layer was applied on both sides of the substrate by plasma-enhanced chemical vapor deposition at 150 • C. The Ti/Au/Ti (5/30/5 nm) gate electrode was deposited by electron-beam evaporation and structured by lift-off. The surface was cleaned by 1 min of ultraviolet (UV) ozone treatment and subsequently a 20-nm-thick Al 2 O 3 gate dielectric was deposited by thermal atomic-layer deposition at 150 • C. The amorphous GST p-type semiconductor layer was direct-current (dc) magnetron sputtered from a Ge 2 Sb 2 Te 5 target at room temperature (see reference [31]) and structured by lift-off. To avoid damage to the Al 2 O 3 , this lift-off was executed using Poly(methyl methacrylate) (PMMA) photoresist and deep-ultraviolet lithography. Afterwards, via holes were wet chemically etched into Al 2 O 3 . Finally, the Ge/Ni/Au (5/5/30 nm) source/drain electrodes were electron-beam evaporated and patterned by lift-off. The post-fabrication crystallization was performed in a vacuum oven at a pressure p = 200 mbar and 200 • C for 1 h.
The Hall measurements were done on a Nanometrics HL5500 Hall System at ambient temperature at a magnetic field of 0.32 Tesla. The GST thin-films had Ge/Ni/Au (5/5/30 nm) contacts and were simultaneously fabricated with the TFTs. The current for 10 nm, 20 nm and 50-nm-thick crystallized GST films was set to 0.01 mA, 0.5 mA and 1 mA, respectively. The amorphous films were too resistive to perform Hall measurements.

Thin-Film Transistor Characterization
All electrical measurements were performed on a probe station (Rucker Kolls, Inc., Milpitas, CA, USA) at ambient conditions with a B1500A semiconductor device analyzer (Agilent Technologies, Santa Clara, CA, USA). Bias stress was applied on the TFTs with a constant gate-source voltage V GS = −5 V and a constant drain-source voltage V DS = −100 mV, immediately followed by a double-sweep measurement of the transfer characteristic.

Results and Discussion
The GST TFTs have been fabricated on a free-standing flexible 50 µm thick polyimide foil as described above. Here, different GST thicknesses between 5 and 50 nm are studied. A schematic cross-section of the TFTs is shown in Figure 1a. A micrograph of a fully fabricated TFT with 5-nm-thick GST (as deposited) is displayed in Figure 1b. Figure 1c shows a photograph of the flexible polyimide substrate after the device fabrication. The device performance is tested in the amorphous (as deposited) state and after annealing at 200 • C in a vacuum oven. To confirm the phase-change of GST upon annealing, we performed XRD measurements. Figure 2 reveals a mixed face-centered cubic (fcc) and hexagonal close-packed (hcp) crystal structure of GST after annealing [32,33]. In Figure 3, the electrical characteristics of 5-50-nm-thick GST TFTs are compared. All TFTs display the expected p-type behavior with increasing |I D | for negative V GS . The transfer characteristics of 50 nm and 20-nm-thick GST TFTs show the desired |I D | increase upon annealing, however, nearly all I D modulation capabilities are lost (see Figure 3a,b). With decreasing GST thickness, the I D ON/OFF modulation is improved (Figure 3a-d). Furthermore, the significantly increased |I D | at V GS = −5 V for 5-nm-thick amorphous GST TFTs (≈20x compared to thicker amorphous layers) leads to the largest ON/OFF ratio of ≈300 at this GST thickness. The annealing of these ultra-thin GST films results in an |I D | decrease, which can be attributed to a degradation of the channel and contact area as discussed later. The output characteristics of amorphous GST TFTs (Figure 3e-h) show an increasingly saturating behavior for reduced GST thicknesses. The strongly saturated characteristics for 5-nm-thick amorphous GST TFTs indicate that the channel pinch-off is successfully obtained. After annealing, the thick GST films ≥20 nm are highly conductive and the TFTs show ohmic behavior with large |I D | (Figure 3i,j). We found that large V DS lead to a breakdown of the these devices and thus the maximum V DS was set to 1 V. Nevertheless, the TFTs with GST thicknesses ≤10 nm after annealing can sustain larger V DS (Figure 3k,l). A fully saturating I D was only obtained for 5-nm-thick annealed GST semiconductor layers, which is similar to the findings in the as deposited state.  In Table 1, the threshold voltages (V Th ) and subthreshold swings (SS) of the devices are presented. Both measures monotonously rise with increasing GST thickness. It has to be noted that due to the low ON/OFF ratio, which is further evaluated below, the values for TFTs with 50-nm-thick amorphous (as deposited) GST channels are impractical. For the same reason, no V Th or SS could be extracted for TFTs with GST thicknesses ≥20 nm after annealing. In Figure 4a, we compare the TFT ON-currents (|I D,ON | at V GS = −5 V) and OFF-currents (|I D,OFF | at V GS = +5 V) for different GST thicknesses. For amorphous (as deposited) GST, the |I D,OFF | can be reduced when scaling the thickness to ≤10 nm and the |I D,ON | exhibits an increase between 10 nm and 5 nm of GST. As shown in Table 2, the effective field-effect mobilities µ FE,eff agree with these trends and have values in the expected range [27,34,35]. The annealing provides the desired |I D | increase only down to 10 nm of GST below which the post-annealing |I D | deteriorates. The µ FE,eff values for 20 and 50 nm of annealed GST cannot be extracted due to the low ON/OFF ratio, and for 10-nm-thick GST TFTs we obtain µ FE,eff = 6.7 cm 2 /Vs. Further, we performed Hall measurements on the crystallized GST films (see Table 2). The amorphous films were too resistive for the Hall measurements. We obtained Hall mobilities around ≈3 cm 2 /Vs and carrier concentrations in the order of 10 20 cm −3 , which is in agreement with prior findings for fcc-GST [34,35]. Figure 4b displays the ON/OFF ratio for different GST thicknesses with a literature comparison. Other works have so far not investigated GST TFTs with active layer thicknesses below 10 nm. In contrast to prior work, we find a clear trend indicating an increasing ON/OFF ratio with reduced GST film thickness. Our maximum ON/OFF ratio of 316 for 5-nm-thick annealed GST results in a ≈15-fold improvement compared to prior reports. The strong thickness dependence of the ON/OFF ratio and the significant improvement for ultra-thin GST layers can be attributed to the electronic energetics of GST in both the amorphous and crystalline phases. For both situations, the gate electric field has a limited penetration depth into the GST layer. For the amorphous phase, GST exhibits a large number of acceptor-like and donor-like traps, which compensate each other leading to strong Fermi-level pinning in the middle of the band gap [36][37][38]. Additionally, there are Te lone-pairs, which could also be responsible for the observed hysteresis in the transfer characteristics (Figure 3a-d) [36,37]. In the crystalline phase, mainly acceptor-type vacancy defects are present [36,37], which results in strong p-type doping and a Fermi-level shift into the valence band forming a degenerate semiconductor [35,38]. In this case, the depletion width for the gate electric field is strongly limited [39] and a fully-depleted TFT can only be achieved for ultra-thin semiconductor layers. Thus, the OFF-current of GST TFTs is a strong function of GST thickness and can be reduced with thinner GST layers. In the following, the dependence of the ON-current on the GST thickness is discussed.    For that, we analyze TFTs with different channel lengths between 7 µm and 100 µm to extract the resistivity ρ (Figure 5a) and contact resistance R C (Figure 5b). For the amorphous case, we find that the ρ and R C are strongly reduced for 5-nm-thick GST compared to thicker layers. This can be attributed to a parasitic resistance of the highly resistive GST film [40,41], due to the limited penetration depth of the gate electric field forming a very thin conductive accumulation region (see Figure 5c, top-left) [42,43]. Thus, the ON-current in TFTs with amorphous GST channels can be improved by thickness downscaling due to a reduction of the parasitic series resistances. In contrast, the annealed GST thin-film exhibits a significant decrease in ρ and R C for GST thicknesses ≥10 nm, which is related to the large conductivity of the crystalline phase. We attribute the unsuccessful reduction of ρ and R C upon annealing for 5-nm-thick GST to a degradation of the contact and surface area, which could be caused by an oxidation during annealing and migration effects in the source/drain contact area. We believe that these effects should certainly have an increased impact for thinner GST channels as indicated in dark gray in Figure 5c (bottom). To confirm that the device oxidation is responsible for the degradation of ρ, future work should address different annealing parameters and environment such as higher vacuum level or nitrogen atmosphere.  From the above described measurements and analysis, we conclude that among the amorphous (as deposited) and crystallized (annealed) devices the TFTs with 5-nm-thick GST and 10-nm-thick GST show the highest performance, respectively. Thus, we performed bending tests with these devices by wrapping the polyimide substrates around a metallic rod with a radius R = 6 mm. Figure 6a,b show the results of the bending tests for TFTs with 5-nm-thick amorphous GST channels and 10-nm-thick crystallized GST channels, respectively. Both devices remain fully operational during the bending experiments. The former (a) shows a reduction of |I D,ON | and µ FE,eff [44] while the latter (b) remains almost unaltered with a small |I D,ON | increase. From prior findings, we know that, typically, devices on 50 µm thick polyimide sustain bending to R = 5-6 mm without any significant alterations in their characteristics [45][46][47]. However, the here observed |I D,ON | reduction by ≈25 % for TFTs with 5-nm-thick amorphous GST channels indicates that not the bending, but the preceding electrical characterization may have caused this change. Thus, we investigated the changes in |I D,ON | upon bias stress measurements (see Figure 6c). After a cumulative bias stress time of 1100 s, the TFT with a 5-nm-thick amorphous GST channel has an |I D,ON |, which is reduced to less than 10 % of its initial value, which is then partially recovered to about 60 % after a sweep to positive V GS . In contrast, the changes for the TFT with a 10-nm-thick crystallized GST channel are significantly smaller. A reason for the strong bias stress dependence of the TFTs with amorphous channels could be intrinsic defects such as Te lone-pairs [36,37], which we also attributed to the observed hysteresis in the transfer characteristics. These defects are not expected to be present in the crystalline phase of GST. Consequently, we see less bias stress dependence in the crystallized films. However, due to the mixed crystalline phase of GST (see Figure 2) after annealing, there could still be Te lone-pairs present e.g., at grain boundaries. An additional effect, which needs to be taken into account, is the known resistance drift over time in amorphous GST, which could also partially cause the |I D,ON | reduction [48,49].

Conclusions and Outlook
We have reported a significant performance improvement for GST TFTs by lowering the semiconductor thickness down to 5 nm. The ON/OFF-ratio was improved by a factor of ≈15 and saturating output characteristics were obtained. Although a µ FE,eff of 6.7 cm 2 /Vs for 10-nm-thick crystalline GST TFTs was observed, the abovementioned performance improvements could only be achieved at a GST thickness of 5 nm, where the maximum µ FE,eff was found to be 0.04 cm 2 /Vs. This work shows that GST is a promising p-semiconductor for flexible electronics. Thus, we recently demonstrated the integration of such TFTs with n-type InGaZnO 4 to form flexible CMOS circuits [44]. Therein, we showed a bending stability of these circuits to a tensile radius of 6 mm.
However, several aspects still need to be addressed in the future. The crystallization process for 5-nm-thick GST films needs improvement, which could be achieved by changing the crystallization temperature, atmosphere and time, and by applying appropriate passivation layers to GST prior to the crystallization. In addition, different source/drain contact materials could be studied to investigate their impact on R C before and after annealing. Furthermore, other material compositions could be investigated. The electronic properties of crystalline GST could be altered by increasing the Ge content, which could reduce the number of Ge vacancies responsible for the p-type doping [50]. The resulting reduction of free carriers could then increase the minimum GST thickness required for the improved TFT performance, and thus the crystallization process could be simplified. Furthermore, a significant increase of the Sb content has resulted in reduced resistivities in the amorphous phase of GST [51], which could be a path for improvements of TFTs with amorphous GST channels.