Drain Current Stress-Induced Instability in Amorphous InGaZnO Thin-Film Transistors with Different Active Layer Thicknesses

In this study, the initial electrical properties, positive gate bias stress (PBS), and drain current stress (DCS)-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with various active layer thicknesses (TIGZO) are investigated. As the TIGZO increased, the turn-on voltage (Von) decreased, while the subthreshold swing slightly increased. Furthermore, the mobility of over 13 cm2·V−1·s−1 and the negligible hysteresis of ~0.5 V are obtained in all of the a-IGZO TFTs, regardless of the TIGZO. The PBS results exhibit that the Von shift is aggravated as the TIGZO decreases. In addition, the DCS-induced instability in the a-IGZO TFTs with various TIGZO values is revealed using current–voltage and capacitance–voltage (C–V) measurements. An anomalous hump phenomenon is only observed in the off state of the gate-to-source (Cgs) curve for all of the a-IGZO TFTs. This is due to the impact ionization that occurs near the drain side of the channel and the generated holes that flow towards the source side along the back-channel interface under the lateral electric field, which cause a lowered potential barrier near the source side. As the TIGZO value increased, the hump in the off state of the Cgs curve was gradually weakened.


Introduction
Recently, amorphous indium gallium zinc oxide (a-IGZO), as a representative of an amorphous metal oxide-based semiconductor, has been widely investigated for use in the active layer of thin-film transistors (TFTs) due to its high electron mobility, good transparency in visible light, chemical and thermal stability, low temperature processing, and smooth surface [1][2][3][4]. The a-IGZO TFT with excellent electrical properties, such as high mobility (µ) of over 10 cm 2 ·V −1 ·s −1 and low values of subthreshold swing, has become one of the research hotspots for the advanced display application in next-generation active-matrix liquid crystal displays (AM-LCDs) and active-matrix organic light-emitting diodes (AM-OLEDs) [5][6][7][8]. Hitherto, AM-OLEDs driven by the a-IGZO TFTs involve two or three transistors and one capacitor current-biased voltage-programmed pixel circuit. Therefore, the stability of the a-IGZO TFTs under long-term current-bias is a critical issue for these circuits in AM-OLEDs. However, the a-IGZO TFTs inevitably suffer gate and drain bias stresses during practical operation conditions, leading to device instability and hindering their development for commercial products [9,10]. Fujii et al. [11] have investigated the increase in internal temperature of the IGZO TFTs when the device was operated in the saturation region. Choi et al. [12] have reported that the electron-hole pair generation by impact ionization near the drain side contributed to the negative shift of the threshold voltage of IGZO TFTs with wide channel width under a high gate and drain bias stress. Valdinoci et al. [13] have reported that the electron-hole pair generation by impact ionization near the drain region caused the floating body effect in high µ poly-Si TFTs. Consequently, the electrical stability under drain current stress was considered to be an important issue, especially for high-µ oxide TFTs.
Moreover, the active layer thickness is an important parameter to adjust device electrical properties, such as on/off ratio, threshold voltage, and field effect mobility [14][15][16]. As reported in previous publications, the device performance is significantly influenced by the semiconductor/gate insulator (GI) interfacial density [17,18] and the active layer trap density [19], indicating that the total trap density increases with the increase in the active layer thickness [20], which can effectively modify the threshold voltage and field effect mobility. Therefore, the impact of the active layer thickness (T IGZO ) on the instability induced by the positive gate bias stress (PBS) and the drain current stress (DCS) in a-IGZO TFTs should be well investigated.
In this study, the initial electrical properties and PBS and DCS-induced instabilities of a-IGZO TFTs with various T IGZO are investigated. Moreover, the DCS-induced instability in the a-IGZO TFTs with various T IGZO is revealed by the combination of current-voltage (I-V) and capacitance-voltage (C-V) measurements.

Experimental
A schematic cross-sectional view and fabrication process of the bottom-gate IGZO TFT are shown in Figure 1. The fabrication procedure for the a-IGZO TFT is as follows. A chromium (Cr) gate electrode is firstly formed on a glass substrate. A SiO x gate insulator (GI) with a thickness of 150 nm is then deposited at 350 • C by plasma-enhanced chemical vapor deposition (PECVD). The a-IGZO layer with thicknesses of 25 nm, 45 nm, 75 nm, and 100 nm are deposited at 160 • C from a sintered IGZO ceramic target by direct current (DC) magnetron sputtering with a mixed gas of Ar/O 2 = 29.4/0.6 sccm at a deposition pressure of 1 Pa. After patterning the IGZO film as an active channel, a SiO x film (200 nm) as an etch stopper is deposited by PECVD. Source and drain electrodes are formed using indium tin oxide (ITO) via contact holes. A 200-nm thick SiO x passivation layer is also deposited by PECVD. Finally, the IGZO TFTs are annealed in N 2 ambient at 350 • C for 1 h before electrical measurements. The channel width (W) and length (L) the IGZO TFTs are 50 µm and 20 µm, respectively. All of the I-V characteristics are measured using an Agilent 4156C precision semiconductor parameter analyzer. The C-V measurements, the channel capacitance (C gc ), the gate-to-source capacitance (C gs ), and the gate-to-drain capacitance (C gd ), are measured at 1 kHz and an alternating current (AC) level of 100 mV. All of the measurements are carried out at room temperature in ambient air.

Results and Discussion
To investigate the thickness impact on the chemical properties and bonding states of the IGZO films, an X-ray photoelectron spectroscopy (XPS, ESCALAB250Xi, Thermo Fisher Scientific, Waltham, MA, USA) measurement is performed. Figure 2 shows the O 1s XPS spectra of the IGZO films with various thicknesses. The O 1s spectra can be resolved into three nearly Gaussian distribution peaks approximately centered at 530.7 eV, 531.4 eV, and 532.6 eV. The peaks at the binding energy of 530.7 eV (labeled as O M ), 531.4 eV (labeled as O V ), and 532.6 eV (labeled as O H ) are attributed to the O 2− ions combined with the metal atoms, oxygen deficiency, and hydroxyl groups in a stoichiometric IGZO structure, respectively [21]. The positions, areas, and area ratios of the O 1s three peaks for the IGZO films with various thicknesses are summarized in Table 1 Figure 3 illustrates the C-V plot as a function of the thickness of IGZO in the ITO/IGZO/SiO 2 /Cr stack structure. It is noted that the increase in the IGZO thickness induces a negative shift of the flat band voltage (V FB ). The variation of the V FB in the negative direction implies that the threshold voltage (V th ) of the ITO/IGZO/SiO 2 /Cr stack structure-based TFTs can be adjusted by using the IGZO layer with various thicknesses. In addition, the maximum negative shift of V FB is observed for the IGZO film with the thickness of 100 nm, which contributes to the largest negative shift of the V th .   Table 2.  The saturation mobility µ sat is calculated by fitting a straight line to the plot of the square root of I DS versus V GS based on the following equation [22]: where W and L are the channel width and length, respectively, and C SiOx is the capacitance per unit area of the GI. When the T IGZO is increased from 25 nm to 100 nm, the µ sat is slightly degraded from 14.17 cm 2 ·V −1 ·s −1 to 13.04 cm 2 ·V −1 ·s −1 . The µ sat is affected by the quality of the active layer and the a-IGZO/GI interface. To confirm the influence of the T IGZO on the quality of the a-IGZO/GI interface, the hysteresis behaviors of the IGZO TFT with various T IGZO are extracted, as listed in Table 1. The identically negligible clockwise hysteresis is obtained regardless of the T IGZO , indicating that the good quality of the IGZO/GI interface is well kept during the fabrication processes for all of the IGZO TFTs. Moreover, the V on and SS values are significantly changed from 2.32 V and 323 mV/dec. in the 25-nm thick IGZO TFT to −0.33 V and 475 mV/dec. in the 100-nm thick IGZO TFT, respectively. The degraded SS value and the shifted V on in the negative V GS direction can be commonly interpreted as consequences of the total defect states and free carrier numbers being increased as the T IGZO values increased, which is consistent with previous publications [23,24] and in agreement with the C-V measurements in Figure 3. Generally, the SS value is an indicator of the maximum area density of state (N t ), including the interfacial (D it ) and the semiconductor bulk traps (N bulk ). The N t value can be extracted from following equation [25]: where q is the electron charge, and k is the Boltzmann constant. The N t values were 6.53 × 10 11 , 7.62 × 10 11 , 8.83 × 10 11 , and 1.03 × 10 12 cm -2 ·eV -1 for the IGZO TFTs with the T IGZO values of 25 nm, 45 nm, 75 nm, and 100 nm, respectively. Obviously, the N t is increased with the increase in the T IGZO value, which is consistent with the XPS results. The results exhibit that the change in the N t mainly originated from the N bulk , owing to the similar a-IGZO/GI interfacial quality.
To confirm the uniformity and reproducibility of the a-IGZO TFTs with various T IGZO , the I DS -V GS curves of the 13 individual devices measured at V DS of 20.1 V are shown in Figure 5, respectively. The corresponding electrical properties, such as µ sat , V on , SS, and hysteresis, are listed in Table 3. Notably, the statistical distribution of all of the parameters has the same tendency as described in Table 1 and small standard deviations, thereby indicating very good reproducibility in the fabricated a-IGZO TFTs.  To investigate the impact of the T IGZO on the stability of a-IGZO TFTs, the positive bias stress (PBS) is carried out. Figure 6a-d shows the variation in the transfer characteristics of the a-IGZO with various T IGZO under PBS with a V GS value of 20 V. The variation in V on (∆V on ) as a function of PBS duration for the a-IGZO TFTs with various T IGZO values is shown in Figure 5e. It is found that the transfer characteristics for all of the TFTs under PBS shift parallel in the positive V GS direction without SS degradation, indicating that the electrons are trapped at the interface of the a-IGZO or in the GI without introducing any defects. When the T IGZO is decreased from 100 nm to 25 nm, the ∆V on is remarkably increased from 0.52 V to 1.85 V after the stress duration of 10 4 s. The obtained results can be explained by the vertical electrical field distribution. Generally, the electric potential exponentially declines inside the active layer, and has a maximum transfer length called the Debye length. For the a-IGZO TFT, the calculated Debye length was~40 nm [19]. When the T IGZO is less than Debye transfer length (T IGZO = 25 nm), the surface potential will exponentially decline into the whole active layer. Therefore, with the decrease in the T IGZO value, the electrical field will be enhanced. Under PBS, the electrons in the thinner T IGZO will be accelerated by the enhanced surface field, which are accumulated by electrical field energy and are trapped at the interface of the a-IGZO/GI or in the GI under the positive bias, leading to the large positive V GS shift. When the T IGZO increased to more than the Debye length of 40 nm, the electric field at the front-interface becomes lower, contributing to the few electrons that are trapped at the front-interface, which exhibits the small ∆V on with the increase in the T IGZO value.  To clarify the mechanism of the DCS-induced instability in the a-IGZO TFTs with various T IGZO , the C-V analyses of C gc , C gs , and C gd before and after DCS duration of 10 4 s are carried out, as shown in Figure 8. Compared with the C gc curves of the a-IGZO TFTs with various T IGZO values in the initial stage and after DCS duration, all of the C gc curves exhibited a positive V GS shift with distortion in the off state of the C-V curves. The shift of the C-V curves is weakened as the T IGZO value increases, which has a similar tendency to the I-V curves, as shown in Figure 7. However, the shift amplitude of the C-V curves is smaller than that of the I-V curves, indicating that the less free carriers are trapped, or the trapped carriers are partly de-trapped during the C-V measurement after the DCS. Furthermore, the hump phenomenon in the off state of the C-V curves becomes weakened as the T IGZO values increase, which is hardly observed in the I-V curves. To further investigate the origin of the hump phenomenon in the off state of the C-V curves, the C gs and C gd values before and after the DCS are measured. Note that the both C gs and C gd curves exhibit a parallel shift in the positive V GS direction. However, the hump phenomenon is only observed in the C gs curve rather than the C gd curve during the DCS.
In terms of the a-IGZO TFT with a T IGZO of 25 nm under the DCS (V DS = V GS ), the electrons are transported from the source to drain side along the front-channel interface, which contributes to a depletion region near the drain side. Combined with the case of 25-nm thick IGZO TFT under the PBS, in the initial stage of DCS (<100 s), the electrons are accelerated to the front-channel under the high vertical electric field. Then, they are trapped at the interface of the a-IGZO/GI or injected into the GI, resulting in a significantly positive V GS shift of the transfer curve. Simultaneously, the electrons are accelerated from the source to the drain side under the lateral electric field, resulting in the impact ionization occurring at the drain side of the channel [12]. Subsequently, the electron-hole pairs are generated by impact ionization near the drain side. The generated electrons and holes are collected at the front-channel and the etch-stopper/IGZO (back-channel) interfaces, respectively. The generated holes flow towards the source side along the back-channel interface and cause a lowered potential barrier near the source side, leading to the additional charge response in the C-V measurement, which contributes to the hump in the off state of the C gs curve. The schematic diagram of DCS-induced degradation in the IGZO TFT with the T IGZO of 25 nm is illustrated in Figure 9a. In the subsequent stage (>100 s), with the extension of DCS duration, the more generated holes are accumulated near the source side, which contributes to the increase in the body potential. Therefore, the ∆V on of the transfer curve is weakened with the DCS duration. When the T IGZO value is increased to 45 nm, a similar phenomenon is observed in the a-IGZO TFT under the DCS of 10 4 s. Due to the reduction of the vertical electric field, the amount of the trapped electrons are decreased at the interface of the channel/GI or into the GI, leading to the smaller ∆V on of the transfer curves compared with the 25-nm thick IGZO TFT, which is in agreement with the I-V and C-V results. Meanwhile, the impact ionization occurs near the drain side under the lateral electric field. The electrons are accelerated from the source to the drain side, which induces the generation of the electron-hole pair near the drain side. The generated holes drift towards the source side along the back-channel interface. Due to the amount of free electrons that increase with the increase in the T IGZO , the recombination probability of the holes and electrons are enlarged during the hole drifting. The number of the collected holes at the source side is reduced, contributing to the small hump in the off state of the C gs curve. When the T IGZO is further increased to 75 nm or 100 nm, the positive V GS shift of the transfer curves is significantly decreased due to the weaker vertical electric field with the increase in the T IGZO value, contributing to the slightly positive V GS shift of the I-V and C-V curves. The schematic diagram of the mechanism of DCS-induced instability in the IGZO TFT with the thicker T IGZO is illustrated in Figure 9b. The generated holes induced by the impact ionization in the drain region are drifted from the drain to the source side along the back-channel under the vertical and lateral electric fields. The holes would suffer easily from the recombination with the more free electrons in the thicker IGZO layer. Therefore, the slight hump in the off state of the C gs curve is attributed to the few holes that are accumulated at the back-channel near the source side.
Besides the T IGZO value, the architecture of devices also plays a critical role in the DCS-induced instability of the TFTs. On the basis of our previous publication [26], the role of impact ionization is strongly dependent on channel scale, and exhibits two types of dependences on channel length and width. When the DCS is applied to the TFTs with a fixed channel length and different channel widths, the stronger impact ionization can be observed for the wider channel width TFT, leading to the high heating temperature. On the other hand, when the DCS is carried out on the devices with a fixed channel width and different channel lengths, the stronger impact ionization can be obtained for the shorter channel length TFT. Therefore, besides the proper T IGZO , the a-IGZO TFTs with the relatively long length and short width may effectively minimize the impact ionization effect, improving the DCS-induced stability of the a-IGZO TFTs.

Conclusions
In this study, the initial electrical properties, PBS, and DCS-induced instabilities of a-IGZO TFTs with various T IGZO are investigated. As the T IGZO values increased, the V on decreased, while the SS slightly increased because the total defect states and free carrier numbers were increased as the increase in the T IGZO . It is found that the ∆V on under PBS is aggravated as the decrease in the T IGZO , which is due to the enhancement of the vertical electrical field in the channel. In addition, the DCS-induced instability in the a-IGZO TFTs with various T IGZO values is revealed by the combination of I-V and C-V measurements. The C-V results indicate that an anomalous hump phenomenon is only observed in the off state of the C gs curve for all of the a-IGZO TFTs. This is because the impact ionization occurs near the drain side of the channel and the generated holes flow towards the source side along the back-channel interface under the lateral electric field, which causes a lowered potential barrier near the source side. Since the amount of free electrons increase with the increase in the T IGZO values, the recombination probability of the generated holes and electrons are enlarged during the hole drifting, leading to the weakened hump phenomenon as the the T IGZO values increased. This study points out that material and fabrication engineering in the drain region should be well considered, even for the high-performance oxide TFTs.