A High-Precision Control for a ZVT PWM Soft-Switching Inverter to Eliminate the Dead-Time Effect

Abstract: Attributing to the advantages of high efficiency, low electromagnetic interference (EMI) noise and closest to the pulse-width-modulation (PWM) converter counterpart, zero-voltage-transition (ZVT) PWM soft-switching inverters are very suitable for high-performance applications. However, the conventional control algorithms intended for high efficiency generally results in voltage distortion. Thus, this paper, for the first time, proposes a high-precision control method to eliminate the dead-time effect through controlling the auxiliary current in the auxiliary resonant snubber inverter (ARSI), which is a typical ZVT PWM inverter. The dead-time effect of ARSI is analyzed, which is distinguished from hard-switching inverters. The proposed high-precision control is introduced based on the investigation of dead-time effect. A prototype was developed to verify the effectiveness of the proposed control. The experimental results shows that the total harmonic distortion (THD) of the output current of the ARSI can be reduced compared with that of the hard-switching inverter, because the blanking delay error is eliminated. The quality of the output current and voltage can be further improved by utilizing the proposed control method.


Introduction
In high-performance applications, the high switching frequency is the least requirement for power inverters to achieve high dynamical response and high precision [1]. However, hard-switching power inverters suffer from large switching loss and severe electromagnetic interference (EMI) as the switching frequency increases [2,3].
In order to solve the problems of large switching loss and severe EMI in a power inverter with high switching frequency, the use of the soft-switching technique is one of the best options. It utilizes auxiliary components to limit the di/dt or dv/dt during the commutation period, and thus reduces the overlap between the voltage and current of semiconductor switches. To date, a variety of soft-switching DC-AC topologies have been proposed [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Among them, the zero-voltage transition (ZVT) pulse-width-modulation (PWM) inverters is a typical soft-switching inverters. An auxiliary circuit connected in parallel with the main power path is employed in ZVT PWM inverters, which only operate for a short interval before and after the commutation period of the main switches. This makes ZVT inverters the closest to the PWM converter counterpart. In addition, ZVT PWM inverters have the advantages of operating with soft switching within a wide load range and low voltage and current stresses over other types of soft-switching inverters.
Several topologies of the ZVT PWM inverters have been proposed. The auxiliary resonant commutated pole inverter (ARCPI) has been proposed with two auxiliary switches per phase [4,5]. Figure 1 depicts the single-phase ARSI topology analyzed in this paper, which consists of a standard H-bridge inverter, resonant capacitors and an auxiliary circuit. The proper operation of the auxiliary switches S r1 and S r2 can create zero-voltage-switching (ZVS) condition for the main switches S 1 -S 4 . Meanwhile, the auxiliary switches can realize zero-current switching (ZCS).

Commutation of the Auxiliary Resonant Snubber Inverter
Energies 2016, 9,579 2 of 18 the major drawback is the existence of the split capacitors, which cause the problems of capacitor charge balance. The auxiliary resonant snubber inverter (ARSI) has been proposed to eliminate the split capacitors, but the three-phase topology cannot utilize the conventional space-vector-pulsewidth modulation (SVPWM) [6,7]. Thus, they are more suitable for permanent magnet brushless DC motors instead of all types of motors. The single-phase topology is very attractive with only two auxiliary switches and well fit to the conventional PWM. Meanwhile, the ZVT inverter using coupled magnetics has been proposed to eliminate the split capacitors [8][9][10]. However, these topologies need coupled inductors and a large number of auxiliary switches, which increase the cost and difficulty of the circuit realization. The ZVT PWM converter has been synthesized and summarized in [11,12].
Although each topology has its drawbacks, the ZVT inverters are widely adopted due to its high efficiency, low EMI noise, available to utilize PWM and low voltage and current stresses. However, the main problem in high-performance applications is the dead-time effect, which brings about distortion and nonlinear voltage error. Extensive studies have been completed on the elimination [13,14] and compensation [15][16][17] of the dead-time effect, but they are focused on hard-switching inverters. With the additional auxiliary circuit, the auxiliary current is a new controllable variable in the ZVT PWM inverters compared with hard-switching inverters. Just as the DC-link soft-switching inverter, the zero-voltage notches can influence the output and increase the nonlinearity [18]. The auxiliary current can also affect the output voltage and current of ZVT PWM inverters, which makes the dead-time effect quite different from that of hard-switching inverters. Besides, the conventional control of ZVT PWM inverters including the fix-timing control [19,20] and variable-timing control [20][21][22] aim to improve the efficiency and leads to voltage distortion in turn.
Motivated by the dead-effect elimination of hard-switching inverters and lack of studies about the impact of auxiliary current on linearity of a ZVT PWM soft-switching inverter, this paper analyzes the dead-time effect of a typical example of ZVT PWM soft-switching inverters-ARSI. A highprecision control by controlling the auxiliary current to eliminate the dead-time effect is proposed. A prototype was developed to verify the effectiveness of the proposed control method. Figure 1 depicts the single-phase ARSI topology analyzed in this paper, which consists of a standard H-bridge inverter, resonant capacitors and an auxiliary circuit. The proper operation of the auxiliary switches Sr1 and Sr2 can create zero-voltage-switching (ZVS) condition for the main switches S1-S4. Meanwhile, the auxiliary switches can realize zero-current switching (ZCS). The detailed circuit operation will be analyzed in the case of positive output current. In the following, we assume that: 1) All components and devices are ideal;

Commutation of the Auxiliary Resonant Snubber Inverter
2) The gate signals of the MOSFETs are ideal square-wave; 3) The load Lo is large enough to maintain the load current constant during each switching cycle. The detailed circuit operation will be analyzed in the case of positive output current. In the following, we assume that: All components and devices are ideal; 2) The gate signals of the MOSFETs are ideal square-wave; 3) The load L o is large enough to maintain the load current constant during each switching cycle.
One switching cycle of the operating stages and the operating waveforms are, respectively, shown in Figures 2 and 3, where v ds is the drain-source voltage of a MOSFET, i d is the drain current of a MOSFET, v g is the practical gate signal with dead-time, v g,id is the ideal gate signal, i Lr is the resonant inductor current, v ab is the practical pole voltage across the load with dead-time, v ab,id is the ideal pole voltage across the load and v err is the voltage error between v ab and v ab,id .
Energies 2016, 9,579 3 of 18 One switching cycle of the operating stages and the operating waveforms are, respectively, shown in Figures 2 and 3, where vds is the drain-source voltage of a MOSFET, id is the drain current of a MOSFET, vg is the practical gate signal with dead-time, vg,id is the ideal gate signal, iLr is the resonant inductor current, vab is the practical pole voltage across the load with dead-time, vab,id is the ideal pole voltage across the load and verr is the voltage error between vab and vab,id.   1) Stage A (t0-t1): The main switches S1 and S4 fully conducts the load current and S2 and S3 are in the off state. Therefore, the pole voltage vab is expressed as follows: 2) Stage B (t1-t2): Due to the existence of the resonant capacitors Cr1 and Cr4, vds1 and vds4 increase very slowly. Therefore, S1 and S4 are turned off at ZVS at t1. Then, the load begins resonating with four resonant capacitors. Cr2 and Cr3 are discharged and Cr1 and Cr4 are charged due to the positive load current. The drain-source voltages of MOSFETs can be calculated as follows: The pole voltage can be obtained as follows: 1) Stage A (t 0 -t 1 ): The main switches S 1 and S 4 fully conducts the load current and S 2 and S 3 are in the off state. Therefore, the pole voltage v ab is expressed as follows: 2) Stage B (t 1 -t 2 ): Due to the existence of the resonant capacitors C r1 and C r4 , v ds1 and v ds4 increase very slowly. Therefore, S 1 and S 4 are turned off at ZVS at t 1 . Then, the load begins resonating with four resonant capacitors. C r2 and C r3 are discharged and C r1 and C r4 are charged due to the positive load current. The drain-source voltages of MOSFETs can be calculated as follows: The pole voltage can be obtained as follows: When v ds2 and v ds3 decrease to zero at t 2 , the resonant period is over. The resonant time is calculated as follows: 3) Stage C and D (t 2 -t 4 ): After the v ds2 and v ds3 decrease to zero, the current freewheels through the body diodes D 2 and D 3 and v ds2 and v ds3 are clamped to zero. Therefore, S 2 and S 3 are turned on at ZVS condition at t 3 . After t 3 , the current is diverted from D 2 and D 3 to the channels of S 2 and S 3 . During these stages, the pole voltage v ab can be written as follows: v ab ptq "´V s 4) Stage E and F (t 4 -t 6 ): S r1 is turned on at t 4 at ZCS condition, resulting in charging the resonant inductor with voltage V s . The resonant inductor current can be calculated as follows: At t 5 , the resonant inductor current i Lr equals the load current i o . After t 5 , S 2 and S 3 work from third quadrant to first quadrant because i Lr is larger than i o . To obtain the resonant inductor current I Lrm , the charging time can be obtained according to Equation (7).
During this stage, the pole voltage is as follows: v ab ptq "´V s 5) Stage G (t 6 -t 7 ): The resonant inductor is charged to I Lrm at t 6 . Meanwhile, S 2 and S 3 are turned off at ZVS condition at t 6 . Thus, the resonant inductor begins resonating with four resonant capacitors. C r1 and C r4 are discharged and C r2 and C r3 are charged. The equations during this resonant period can be written as follows.
v ds1 ptq`v ds3 ptq " V s (10) Therefore, the inductor current and drain-source voltages of the main MOSFETs can be obtained as follows according to Equations (10)- (14).
b L r C r , and I Lrm is the initial resonant inductor current. The pole voltage can be obtained as follows: v ab ptq " v ds3 ptq´v ds4 ptq " Z A pI Lrm´io q sinω A pt´t 6 q´V s cosω A pt´t 6 q For v ds1 (t) = 0, the resonant time can be calculated as: At the end of the resonant time t 7 , i Lr can be obtained from Equations (15) and (19).
6) Stage H-J (t 7 -t 10 ): After the voltages v ds1 and v ds4 decrease to zero, the body diodes D 1 and D 4 conduct the current so that v ds1 and v ds4 are clamped to zero. Therefore, S 1 and S 4 are turned on at the ZVS condition at t 8 and take over the load current. During these stages, the pole voltage can be obtained.
v ab ptq " V s (21) Owing to the positive pole voltage, the resonant inductor is discharged. During the discharging period, i Lr can be calculated as follows: After the current i Lr decreases to zero, S r1 are turned off at ZCS condition. The discharging time can be obtained as follows according to Equation (22).

Dead-Time Effect and Voltage Error
The duty ratio and output voltage are respectively the direct input and output of the inverters. Thus, the linearity of inverters is related the relationship duty ratio and output voltage.
The voltage error v err between the practical pole voltage and the ideal pole voltage can be obtained as follows: The average voltage error in a switching cycle can be obtained as follows: The average output voltage can be calculated as follows: The output voltage is related to not only the duty ratio but also the commutation times according to Equation (27). The nonlinearity of the ARSI is caused by the dead-time effect. Figure 4 shows when the output current is positive, the dead-time effect of the hard-switching inverter and the ARSI without considering the turn-on and turn-off delay. Due to the finite rise-and fall-times of voltage caused by the output capacitors of MOSFETs, the rise-and fall-errors occur in the hard-switching inverter. Additionally, the dead-time effect also causes the blanking delay error which is the main error source in the hard-switching inverter [16]. As for the ARSI, only the commutation stages (t 1 -t 2 ) and (t 6 -t 7 ) lead to the voltage errors according to Equation (25). Although the riseand fall-errors are enlarged in the ARSI due to the additional resonant capacitors compared with the hard-switching inverter, the blanking delay error that caused by the blanking delay times (t 2 -t 3 ) and (t 6 -t 7 ) is eliminated, because the body diodes of the next turn-on MOSFETs conduct the current during the blanking delay time. Therefore, the dead-time effect is reduced in the ARSI.
The average voltage error in a switching cycle can be obtained as follows: The average output voltage can be calculated as follows: The output voltage is related to not only the duty ratio but also the commutation times according to Equation (27). The nonlinearity of the ARSI is caused by the dead-time effect. Figure 4 shows when the output current is positive, the dead-time effect of the hard-switching inverter and the ARSI without considering the turn-on and turn-off delay. Due to the finite rise-and fall-times of voltage caused by the output capacitors of MOSFETs, the rise-and fall-errors occur in the hard-switching inverter. Additionally, the dead-time effect also causes the blanking delay error which is the main error source in the hard-switching inverter [16]. As for the ARSI, only the commutation stages (t1-t2) and (t6-t7) lead to the voltage errors according to Equation (25). Although the rise-and fall-errors are enlarged in the ARSI due to the additional resonant capacitors compared with the hard-switching inverter, the blanking delay error that caused by the blanking delay times (t2-t3) and (t6-t7) is eliminated, because the body diodes of the next turn-on MOSFETs conduct the current during the blanking delay time. Therefore, the dead-time effect is reduced in the ARSI.  In one switching cycle, there are two commutations among the main switches. The PTN (positive to negative) commutation is the commutation that the current is diverted from positive switches (S1 and S4) to negative switches (S2 and S3), while the NTP (negative to positive) commutation is the commutation that the current is diverted from negative switches (S2 and S3) to positive switches. In Figure 3, (t1-t2) is PTN commutation and (t6-t7) is NTP commutation.
According to Equation (25), the average voltage error of each commutation in a switching cycle can be obtained as follows: In one switching cycle, there are two commutations among the main switches. The PTN (positive to negative) commutation is the commutation that the current is diverted from positive switches (S 1 and S 4 ) to negative switches (S 2 and S 3 ), while the NTP (negative to positive) commutation is the commutation that the current is diverted from negative switches (S 2 and S 3 ) to positive switches. In Figure 3, (t 1 -t 2 ) is PTN commutation and (t 6 -t 7 ) is NTP commutation.
According to Equation (25), the average voltage error of each commutation in a switching cycle can be obtained as follows: where t rf,PTN is the commutation time of PTN commutation and t rf,NTP is the commutation time of NTP commutation. When the output current is positive, the S 2 and S 3 realize natural ZVS (NZVS) without the operation of auxiliary circuit during the PTN commutation, while S 1 and S 4 realize auxiliary ZVS (NZVS) with the proper operation of auxiliary circuit during the NTP commutation. According to Equations (28) and (29), the PTN commutation introduce positive voltage error and the NTP commutation create negative voltage error in conclusion. The magnitude of the voltage error is proportional to the commutation time t rf regardless of whether the main switches realize NZVS or AZVS. Table 1 shows the average voltage errors of the PTN and NTP commutations. The analysis above is discussed in the case of positive output current, but the conclusion can also be used in the condition of negative output current.
The commutation time t rf is related to the realization of the ZVS type. If the main switches achieve NZVS, the commutation time can be obtained according to Equation (5).
To achieve AZVS with the proper operation of the auxiliary circuit, the commutation time can be obtained according to Equation (19).
where I boost is the initial resonant current which is the current to charge and discharge the resonant capacitors I boost = I Lrm´io and I Lrm is the auxiliary current at the beginning of the resonant time.
According to Equations (30) and (31), the commutation time can be summarized in Table 2. To achieve NZVS, the commutation time is related to the load current. To achieve AZVS, the commutation time is related to the initial resonant current I boost .

Type NZVS AZVS
Commutation time t rfˇ2 n a switching cycle, one commutation aims to realize NZVS of the main switches, while the other commutation aims to achieve AZVS. When the output current is positive, NZVS of the main switches can be achieved during the PTN commutation. When output current is negative, NZVS can only be achieved during the NTP commutation. The voltage error can be obtained according to Tables 1 and 2.

Proposed Control Strategy
The dead-time effect causes the nonlinearity of the ARSI, which results in nonlinear relationship between the output voltage and the duty ratio. This leads to voltage error. As in the analysis in Section 2, the voltage error is proportional to the commutation time. To achieve NZVS, the commutation time related to the load current is uncontrollable. However, to achieve AZVS, the commutation time related to the initial resonant current can be controlled by the auxiliary current. Therefore, the voltage error of AZVS can be controlled. Under the realization of "AZVS + NZVS" in a switching cycle, the voltage error is shown in Equation (32). For V err (t) = 0 in Equation (32), the initial resonant current I boost can be obtained as follows.
If the initial resonant current can be controlled to meet the requirement of Equation (33), the voltage error caused by the dead time can be eliminated. The output voltage can be obtained as follows.
The output voltage is proportional to the duty ratio when the current I boost meet Equation (33). However, when the load current is small enough, the commutation time of NZVS may be longer than the dead time t dead according to Equation (30). The NZVS of the main switches fails, which is shown in Figure 6. This leads to incorrectness of Equation (32). Thus, the initial resonant current meeting Equation (33) cannot eliminate the voltage error when the output current is small enough. The output voltage is proportional to the duty ratio when the current Iboost meet Equation (33). However, when the load current is small enough, the commutation time of NZVS may be longer than the dead time tdead according to Equation (30). The NZVS of the main switches fails, which is shown in Figure 6. This leads to incorrectness of Equation (32). Thus, the initial resonant current meeting Equation (33) cannot eliminate the voltage error when the output current is small enough. To achieve ZVS from zero load to full load and eliminate the dead-time effect, the realization of "AZVS + AZVS", which means all the main switches realize AZVS in a switching cycle, is adopted. According to Tables 1 and 2, the voltage error can be obtained as follows: To achieve ZVS from zero load to full load and eliminate the dead-time effect, the realization of "AZVS + AZVS", which means all the main switches realize AZVS in a switching cycle, is adopted. According to Tables 1 and 2, the voltage error can be obtained as follows: For V err = 0 in Equation (35), the initial resonant current can be obtained as follows: If the initial resonant current meets Equation (36), the voltage error caused by the dead time can also be eliminated with the realization of "AZVS + AZVS". Table 3 shows the realization type of ZVS from zero load to full load. When |i o | > I th , "AZVS + NZVS" is adopted. The initial resonant current is controlled to meet Equation (33). When |i o | ď I th , "AZVS + AZVS" is adopted. The initial resonant current must meet the Equation (36). In this case, the voltage error caused by the dead-time effect can be eliminated from zero load to full load, resulting in a linear relationship between the output voltage and the duty ratio according to Equation (34). Table 3. The realization type of ZVS from zero load to full load.

Type PTN Commutation NTP Commutation
Meanwhile, to ensure the success of NZVS, threshold current I th should meet the requirement as follows so that the ZVS can succeed from zero load to full load.

Conventional Control Strategy
The conventional control involves two methods, fix-timing control and variable-timing control. Although fix-timing control is simple to be implemented, it has the difficulties of achieving ZVS at every load current and it also leads large conduction loss [19,20]. These disadvantages limit the application of fixed-timing control in ZVT inverters. The variable-timing control utilizes the instantaneous load current to generate the gate signal of the auxiliary switches, which can achieve soft-switching for a wide load range and reduce the conduction loss [20][21][22]. These advantages make variable-timing control be widely used. Therefore, only the variable-timing control is discussed below.
The initial resonant current I boost is selected to be as low as possible over the entire load range and I boost is kept constant in variable-timing control. Therefore, the voltage error of the variable-timing control can be obtained as follows. Due to constant I boost , the error occurs in the output voltage. Figure 7 shows the voltage error according to Equation (38) with the parameters in Table 4. The voltage error only occurs when "AZVS + NZVS" is adopted. A large voltage error about 1.2 V occurs at the threshold current 3 A. As the output current increases, the voltage error decreases first and then increases.
Due to constant Iboost, the error occurs in the output voltage. Figure 7 shows the voltage error according to Equation (38) with the parameters in Table 4. The voltage error only occurs when "AZVS + NZVS" is adopted. A large voltage error about 1.2 V occurs at the threshold current 3 A. As the output current increases, the voltage error decreases first and then increases.

Realization of the Proposed Control Strategy
In the proposed control strategy of Section IV, the initial resonant current Iboost can be controlled to eliminate the voltage error caused by the dead-time effect. With the proper conduction of the auxiliary switches Sr1 and Sr2, the initial resonant inductor current ILrm can be controlled to obtain the required Iboost. During the conduction period of S2 and S3, Sr1 is turned on to obtain a positive Iboost to achieve AZVS of S1 and S4. Furthermore, during the conduction period of S1 and S4, Sr2 is turned on to obtain a negative Iboost to realize AZVS of S2 and S3. Thus, to obtain the required Iboost, the resonant inductor must be charged to ILrm at the beginning of the resonant time as follows.

Realization of the Proposed Control Strategy
In the proposed control strategy of Section IV, the initial resonant current I boost can be controlled to eliminate the voltage error caused by the dead-time effect. With the proper conduction of the auxiliary switches S r1 and S r2 , the initial resonant inductor current I Lrm can be controlled to obtain the required I boost . During the conduction period of S 2 and S 3 , S r1 is turned on to obtain a positive I boost to achieve AZVS of S 1 and S 4 . Furthermore, during the conduction period of S 1 and S 4 , S r2 is turned on to obtain a negative I boost to realize AZVS of S 2 and S 3 . Thus, to obtain the required I boost , the resonant inductor must be charged to I Lrm at the beginning of the resonant time as follows. where I boost and I Lrm is always positive without including the direction. Figure 8 shows the auxiliary current during the charging time t ch , commutation time t rf and discharging time t dch . The charging time determines the initial resonant inductor current I Lrm .
During the charging period, as in stages E and F in Figure 3, the inductor current is charged with the DC voltage V s . According to Equation (8), the charging time can be obtained as follows. discharging time tdch. The charging time determines the initial resonant inductor current ILrm. During the charging period, as in stages E and F in Figure 3, the inductor current is charged with the DC voltage Vs. According to Equation (8), the charging time can be obtained as follows. The charging time tch determines the turn-on moment of the auxiliary switches. According to Equations (8) and (23), the discharging time tdch equals tch. Therefore, the on-time of the auxiliary switches can be obtained as follows: 2 Due to tdead > trf, the on-time tA in Equation (39) is larger than the required tA with some margin to ensure that the auxiliary switches is turned off after the auxiliary current drops to zero. Figure 9 shows the open-loop realization diagram of the proposed control. The proposed control method is implemented in the FPGA of a digitally controlled ARSI prototype. FPGA samples the load current every switching cycle. Then the mode judgment is done according to Table 3. If the "AZVS + NZVS" is adopted when |io| ≥ Ith, the initial resonant current is calculated from Equation (33). If the "AZVS + AZVS" is adopted when |io| < Ith, Iboost is fixed at IB. Then, ILrm, tch and tA are calculated from Equations (39)-(41). The gate signal of the auxiliary switches can be generated by tch and tA. The charging time t ch determines the turn-on moment of the auxiliary switches. According to Equations (8) and (23), the discharging time t dch equals t ch . Therefore, the on-time of the auxiliary switches can be obtained as follows: Due to t dead > t rf , the on-time t A in Equation (39) is larger than the required t A with some margin to ensure that the auxiliary switches is turned off after the auxiliary current drops to zero. Figure 9 shows the open-loop realization diagram of the proposed control. The proposed control method is implemented in the FPGA of a digitally controlled ARSI prototype. FPGA samples the load current every switching cycle. Then the mode judgment is done according to Table 3. If the "AZVS + NZVS" is adopted when |i o | ě I th , the initial resonant current is calculated from Equation (33). If the "AZVS + AZVS" is adopted when |i o | < I th , I boost is fixed at I B . Then, I Lrm , t ch and t A are calculated from Equations (39)-(41). The gate signal of the auxiliary switches can be generated by t ch and t A .

Experiment
The proposed method was implemented in the Altera Cyclone IV FPGA with parameters in Table 4. Figure 10 shows the photograph of the prototype. It consists of FPGA (Altera Corporation EP4CE22E22C7N, the USA) control board, switching power supply, MOSFET driver and the power circuit.
Switching mode power supply FPGA board

Experiment
The proposed method was implemented in the Altera Cyclone IV FPGA with parameters in Table 4. Figure 10 shows the photograph of the prototype. It consists of FPGA (Altera Corporation EP4CE22E22C7N, the USA) control board, switching power supply, MOSFET driver and the power circuit.

Experiment
The proposed method was implemented in the Altera Cyclone IV FPGA with parameters in Table 4. Figure 10 shows the photograph of the prototype. It consists of FPGA (Altera Corporation EP4CE22E22C7N, the USA) control board, switching power supply, MOSFET driver and the power circuit. The dead-time effect leads to the nonlinearity of inverter, which introduces the baseband harmonics in the output voltage and current. In the experiment, the total harmonic distortion (THD) of output current and output voltage with different methods are compared to verify the effectiveness of the proposed control method. The oscilloscope MSO4034B with the probes TCP0030, TPP0500 and P5025 is used to measure the voltages and currents. The power analysis module DPO4PWR is used to analyze the THD of the current and voltage. Figure 11 shows the voltage and current waveforms of ARSI with conventional variable-timing control and proposed control when the modulation index is 0.4 in an open-loop configuration. The auxiliary circuit is operated twice with bidirectional current in a switching cycle to realize the "AZVS + AZVS". However, a single direction current occurs in the auxiliary circuit with realization of "NZVS + AZVS". To measure the output voltage v o , a filter is added to attenuate the carrier harmonics of the pole voltage v ab . Figure 11a shows that a large voltage error occurs in the output voltage with conventional control due to the unequal commutation times. The distortion is obvious especially at the mode switching point between the "AZVS + AZVS" and "NZVS + AZVS". The quality of the output voltage is improved with the proposed control in Figure 11b. The voltage error with proposed control should be zero in theory. However, the voltage error exists in the experimental results due to the limited PWM resolution of 8 bit and current detecting error. pole voltage vab. Figure 11a shows that a large voltage error occurs in the output voltage with conventional control due to the unequal commutation times. The distortion is obvious especially at the mode switching point between the "AZVS + AZVS" and "NZVS + AZVS". The quality of the output voltage is improved with the proposed control in Figure 11b. The voltage error with proposed control should be zero in theory. However, the voltage error exists in the experimental results due to the limited PWM resolution of 8 bit and current detecting error.   Figure 12. THD-F of the output voltage with proposed control is 3.21%, which is less than 6.29% with conventional control. The magnitudes of the baseband harmonics are reduced by using the proposed control.   Figure 12. THD-F of the output voltage with proposed control is 3.21%, which is less than 6.29% with conventional control. The magnitudes of the baseband harmonics are reduced by using the proposed control.  Figure 13 shows the magnitudes of the 2nd-10th harmonic voltages with respect to the fundamental voltage. The magnitudes of the harmonic voltages are reduced obviously with the proposed control, except the 6th, 8th and 10th harmonic currents.    Figure 13 shows the magnitudes of the 2nd-10th harmonic voltages with respect to the fundamental voltage. The magnitudes of the harmonic voltages are reduced obviously with the proposed control, except the 6th, 8th and 10th harmonic currents.   Figure 14a. The RMS of the current is only 2A, which is much lower than the RMS of the soft-switching inverters with the modulation index 0.4. The THD-F of the hard-switching inverter is 4.36%. As for the ARSI, the THD-F is reduced to 1.57% and the RSM of the current is improved with conventional control, because the blanking delay error is eliminated which is the main error source   Figure 14a. The RMS of the current is only 2A, which is much lower than the RMS of the soft-switching inverters with the modulation index 0.4. The THD-F of the hard-switching inverter is 4.36%. As for the ARSI, the THD-F is reduced to 1.57% and the RSM of the current is improved with conventional control, because the blanking delay error is eliminated which is the main error source in the hard-switching inverter. The THD-F of the output current is further improved to 0.607% by using the proposed control.   Figure 15 shows the magnitudes of the 2nd-10th harmonic currents of the ARSI respect to the fundamental current. The magnitudes of the harmonic currents are reduced obviously with the proposed control, except the 6th, 8th and 10th harmonic currents. The current results are in good agreement with the voltage results in Figure 13.  Figure 15 shows the magnitudes of the 2nd-10th harmonic currents of the ARSI respect to the fundamental current. The magnitudes of the harmonic currents are reduced obviously with the proposed control, except the 6th, 8th and 10th harmonic currents. The current results are in good agreement with the voltage results in Figure 13.

Conclusions
This paper analyzed the dead-time effect of ARSI, which is a typical example of ZVT PWM inverters. The blanking delay error that is the main error source of the hard-switching inverter is eliminated in the ARSI. Only the error caused by the rise-and fall-times exist in the ARSI. For the dead-time effect, the PTN and NTP commutations, respectively, cause the positive and negative voltage errors that are proportional to the commutation time, regardless whether NZVS or AZVS of the main switches is realized. NZVS and AZVS determine the commutation time of the ARSI. Based on the analysis, a high-precision control has been proposed to eliminate the voltage error. In the experiment, the THD of the output current and voltage are greatly reduced from 1.57% and 6.29% to 0.607% and 3.21%, respectively, by using the proposed control. In conclusion, the output quality can be improved with the high-precision control method.
However, objectively speaking, there are still some disadvantages in the proposed control. This novel method improves the precision at the expense of efficiency, because of relatively higher auxiliary current compared with that of the traditional control. Besides, the current Iboost should be calculated online, resulting higher calculation effort.
Anyway, the proposed control is very attractive in the high-precision applications to improve the output quality. Despite the fact that the analysis and proposed control is based on the ARSI, they can be used similarly to other types of the ZVT PWM inverters to eliminate the dead-time effect.

Conventional Control
Proposed Control Figure 15. The magnitudes of the 2nd-10th harmonic currents of the ARSI respect to the fundamental current.

Conclusions
This paper analyzed the dead-time effect of ARSI, which is a typical example of ZVT PWM inverters. The blanking delay error that is the main error source of the hard-switching inverter is eliminated in the ARSI. Only the error caused by the rise-and fall-times exist in the ARSI. For the dead-time effect, the PTN and NTP commutations, respectively, cause the positive and negative voltage errors that are proportional to the commutation time, regardless whether NZVS or AZVS of the main switches is realized. NZVS and AZVS determine the commutation time of the ARSI. Based on the analysis, a high-precision control has been proposed to eliminate the voltage error. In the experiment, the THD of the output current and voltage are greatly reduced from 1.57% and 6.29% to 0.607% and 3.21%, respectively, by using the proposed control. In conclusion, the output quality can be improved with the high-precision control method.
However, objectively speaking, there are still some disadvantages in the proposed control. This novel method improves the precision at the expense of efficiency, because of relatively higher auxiliary current compared with that of the traditional control. Besides, the current I boost should be calculated online, resulting higher calculation effort.
Anyway, the proposed control is very attractive in the high-precision applications to improve the output quality. Despite the fact that the analysis and proposed control is based on the ARSI, they can be used similarly to other types of the ZVT PWM inverters to eliminate the dead-time effect.