A Hybrid Modular Multilevel Converter with Partial Embedded Energy Storage

Georgios Konstantinou 1,*, Josep Pou 2, Daniel Pagano 3 and Salvador Ceballos 4 1 School of Electrical Engineering and Telecommunications, University of New South Wales (UNSW) Australia, Sydney, NSW 2052, Australia 2 School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore; j.pou@ntu.edu.sg 3 Federal University of Santa Catarina, Florianópolis 88040-900, Brazil; daniel.pagano@ufsc.br 4 Tecnalia, Energy and Environment Division, 48160 Derio, Spain; salvador.ceballos@tecnalia.com * Correspondence: g.konstantinou@unsw.edu.au; Tel.: +61-2-9385-7405


Introduction
The large growth in grid-connected renewable energy resources, experienced globally, has added to the existing challenges of maintaining a reliable and efficient electricity network.Energy storage systems (ESSs) provide a solution for balancing generation with consumption and addressing issues caused by the intermittency and variability of both wind and solar photo-voltaic (PV) systems at a central and distributed level [1][2][3].The additional functions that can be provided by ESSs, including voltage support, frequency regulation, power quality and reliability services, mean that they will become more of a necessity than a "luxury" in the future power system.
Power electronics converters are an important element in the integration of ESSs to the networks.Currently, two-and three-level topologies are predominantly used in grid-connected ESSs [4].However, as the power and energy levels of installed systems are expected to increase, multilevel topologies will become more competitive solutions.Distributed energy storage can also facilitate integration with renewable energy systems, such as PV converters.The main advantages of multilevel converters are their lower semiconductor losses, higher conversion efficiency, high quality output voltages and currents, as well as the potential for fault-tolerant operation [5].
In ESS applications, cascaded and modular multilevel solutions, such as the cascaded H-bridge converter (CHB) or the modular multilevel converter (MMC) [6], offer the additional advantage of reducing the size of the battery string, offering an improved configuration and the capacity for better control of the state of charge (SoC) for each of these strings.Both of these topologies have attracted research interest over the last couple of years [7].An evaluation between the two topologies [7][8][9][10][11][12][13][14][15][16][17][18][19] in terms of conversion efficiency shows that MMC-based solutions perform slightly better compared to the CHB counterparts [4].However, the high semiconductor and capacitance requirements, as well as more complicated voltage and energy balancing of MMCs [8,9] make the CHB a more competitive and practical application in dedicated ESS applications [10,11].
A defining characteristic of MMC-based solutions, compared to the CHB ones, is that they provide, in addition to the lower voltage DC-links of the SMs, a high voltage DC-link terminal.This means that the MMC topology can be potentially used in systems that require a combination of DC-AC power flow with integrated energy storage.The operation of the MMC with SMs that could integrate batteries together with the required voltage control was demonstrated in [12,13], while [14] extended the concept of energy storage in MMCs for traction applications.
The addition of any kind of energy storage elements in the SMs of the MMC necessitates additional controllers for energy balancing between the SMs, the arms, phase-legs and ESS within the converter [15][16][17], as well as considerations for the SoC of the integrated batteries [18,19].Operational aspects of MMC-based ESSs have also been investigated in the current literature, with [20] demonstrating the fault-ride through (FRT) capabilities of the converter and [21] investigating its fault-tolerant capacity and the limitations in real and reactive power capabilities with faulty or isolated ESS SMs.In the latter, the authors calculate a limit of 33% for faulty ESSs within the SMs of the MMC.In [22], it is demonstrated that the converter can operate at even higher power imbalances for ESS within the arms and between the phases of the converter without impacting the output waveforms, if internal imbalances can be tolerated.
Based on the above, the interest for converter configurations that enable ESS integration within the MMC is high.This paper proposes (i) a hybrid modular multilevel converter (HMMC) topology with reduced capacitor voltage ripple in certain SMs and (ii) an HMMC with partial embedded ESS and multi-directional power flow.The novelty of the proposed HMMC lies in the combination of a three-phase, three-level cell with multiple half-bridge SMs (HB-SM) per arm.The advantages of the proposed approach are the partial integration of energy storage to a typical MMC and the elimination of the second harmonic voltage ripple from the SM with the ESS.The required control and limitations of the proposed approach are also discussed, and simulation results are presented for the different operating modes of the converter.
The article is structured as follows: Section 2 presents the fundamental aspects of the MMC that directly relate to the proposed HMMC, and Section 3 introduces the circuit configuration, operational aspects and control of the proposed HMMC.The integration of ESS in some of the SMs of the proposed HMMC is presented in Section 4, and Section 5 shows the simulation results of both configurations.Finally, the conclusions of the work are summarised in Section 6.

Modular Multilevel Converter
The MMC (Figure 1a) offers a modular power electronics solution for medium and high-voltage applications, based on SMs that are the building blocks of the converter phase-legs.The most common SM configuration in the literature is that of the HB-SM (Figure 1b), but other configurations, including the full-bridge (FB-SM), single-clamped (SC-SM), flying-capacitor (FC-SM) and cross-connected SM (CC-SM) (Figure 1c-f) and their combinations, can be used [23].
The converter consists of N series-connected SMs in the arms that behave as controllable voltage sources that, considering the fictitious mid-point of the DC-link voltage as a reference, generate the voltages v ux and v lx across the phase-leg inductors of phase x, where x ∈ [a, b, c].The inductors (L) enable the control of the currents within the upper and lower arms (i ux and i lx ).Looking into one of the phase-legs of Figure 1a, i ux and i lx can be written as the sum of two distinct current components, the common-mode current (i comm ) that is equal to half of the total output current and the differential-mode or circulating current (i circ,x ) that circulates within the phase-leg of the converter, so that: and: The differential (or circulating) current will naturally include a second-order harmonic that can be eliminated in order to increase converter efficiency or defined so that it achieves additional control objectives, such as reducing the ripple in the SM capacitor voltages.The injection of higher order harmonics can also be used to improve the operation of the MMC [24].
The current that flows through the arms of the converter causes a variation in the SM capacitor voltages and is one of the defining characteristics for the sizing (in terms of capacitance, size and weight) of each individual SM.One of the main challenges with the MMC is the reduction of the required capacitance, and consequently the total energy, within the arms of the converter.

Hybrid Modular Multilevel Converter
Partial reduction of SM capacitance for one SM in each of the converter arms in a three-phase system can be achieved by connecting the individual DC-link voltages of the upper-most SM in the upper arm and the lower-most SM in the lower arm of the MMC as analysed in [25].The common connection of the DC-link in the upper-most and lower-most SM transforms this particular set of SMs into a three-phase, two-level converter.As this connection can only be done for one SM per arm (extending to more is not possible due to short-circuits between SMs), it is apparent that the practical application and benefits of the method diminish with increasing number of SMs.Nonetheless, such concepts can be of interest in medium-voltage applications with a low number of SMs.

Circuit Configuration, Operation Principles and Model
In order to reduce the number of SMs that experience the relatively higher voltage ripple without impacting the number of output voltage levels, we propose the hybrid MMC of Figure 2. The topology comprises a three-phase, three-level flying capacitor (FC) converter for the upper and lower arms and a number (N) of series-connected HB-SMs.The three-level FC substitutes two HB-SMs in each of the arms, requiring the same number of semiconductor devices, one common capacitor for the outer stage C f c and a capacitor per-phase as the flying capacitors (C f c,x ).
Assuming N HB-SMs per arm, the number of levels generated by each arm with the additional two levels of the three-phase, three-level FC-SM is equal to N + 3. The total number of levels in the output of the converter is also equal to N + 3 if the SMs in the upper and lower arm switch concurrently or 2N + 5 in the case of interleaved operation of the MMC [26].The operation of the HB-SMs in the proposed HMMC is identical to the typical MMC, while the three-level FC cell has four switching combinations that generate three different voltage levels in the output (v SM ).The switching states of the three-phase, three-level FC cell are given in Table 1.
Table 1.Switching states and output voltage of the three-level FC cell.
A relative reduction in components is achieved, because fewer capacitors are required in the overall system.However, this is not the main objective of the proposed HMMC with benefits derived from the reduced capacitor voltage ripples.As the FC cell is connected across all three phases of the converter, the voltage oscillations cancel out between the three phases, reducing the voltage ripple to a minimum.Furthermore, the three-level FC converter offers redundant switching stages in generating the v C voltage level, as shown in Table 1.These redundancies can be utilised in the proposed HMMC in order to maintain the voltages of capacitors C f c,x to the reference voltage by selecting the appropriate switching state depending on both the deviation of the capacitor voltage and the direction of the arm current.
The behaviour of the proposed HMMC as seen from the output remains similar to the standard MMC topology.The output voltage of the converter ranges in the [−v DC /2, +v DC /2] interval, and the output voltage (v x ) and current (i x ) of phase x, x ∈ {a, b, c} are given by: where ).The controllable voltages generated by the upper and lower arm are given by: where v SM f c is the capacitor voltage of the SMs, s uj ∈ {0, 1} is the switching state of the HB-SMs and s u,l f c ∈ {0, 1, 2} is the switching state of the FC-cell.Based on Kirchoff's voltage law and ( 5) and ( 6), the equations for the upper and lower arm of phase x can be written as: By adding ( 7) and ( 8): and as i x = i ux + i lx , Equation ( 9) becomes: Substituting ( 5) and ( 6) in (10), By subtracting ( 7) and ( 8): Defining the circulating current based on (1) and ( 2): Equation ( 12) can be re-written as: Now, by substituting ( 5) and ( 6) in ( 14): Assuming that: and: where v cu and v cl are the averaged upper/lower voltage capacitor for one SM, ( 11)-( 15) become: The SM capacitor charging/discharging is modelled by: for the upper SMs and for the lower SMs.The FC-SM voltage is given by: and the internal dynamics of the flying capacitors C f c,x described by [27]: where m u f c and m l f c are the duty cycles corresponding to the FC-SM of the upper and the lower arms.The dynamics of the common capacitor in the three-phase FC C f c are defined by the currents in the upper and lower arms of all three phases as i C f c = i DC − s 1a i u a − s 1b i u b − s 1c i u c ≈ 0, so the dynamics of capacitor C f c can be omitted in an averaged model.Summarizing the prior analysis, the HMMC averaged model can be described by the following equations: The first equation models the output current dynamics, while the remaining equations represent the internal dynamics of the HMMC.The state variables are the control input variables m ux m lx m u f cx m l f cx and [v DC v x ] are considered as the perturbations of the system.

Circulating Current Control and Voltage Balancing
It was analysed in the previous section that it is necessary to control the circulating current of the MMC and eliminate the higher order harmonic components that are naturally present in i circ .The behaviour of the HMMC, with the exception of the voltage balancing for the FC-SM, is similar to the MMC, as analysed in Section 2. Control of the circulating current (i circ ) is achieved by modifying the upper and lower arm references (usually by adding and subtracting a reference voltage from an appropriate controller) in order to achieve the control objectives.This results in a variation of the voltages v ux and v lx that controls the current through the inductors L.
As control of the circulating current is a higher-level objective for the operation of the MMC and does not have a direct impact to the generation of the switching signals for the SMs, most of the current controllers that have been proposed for the MMC can be readily applied to the proposed HMMC.In the current work, a proportional-resonant controller with a DC-current reference [28] has been implemented.The circulating current controller is shown in Figure 3.A second requirement for the operation of the MMC is balancing of the SM capacitor voltages, which can be implemented either with the use of sorting algorithms or by making use of the natural balancing property of phase-shifted pulse-width modulation (PS-PWM).In the case of the proposed HMMC, the capacitors of the FC SM will exhibit significantly lower voltage oscillations requiring modifications to the existing sorting algorithms.On the other hand, PS-PWM can be implemented directly if individual reference signals are generated for each of the SMs, including the FC-cell, compensating appropriately for the voltage imbalances between the measured SM capacitor voltage (v Cu,j ) and the SM capacitor reference voltage (v C,re f ).The additional balancing component is multiplied with the sign of the arm current sgn{i ux } so that the SM capacitor voltages are regulated towards the reference depending on the direction and amplitude of the arm current.The combined voltage balancing and modulation stage of the converter, based on PS-PWM (Figure 4a), is shown in Figure 4b.

Hybrid Modular Multilevel Converter (HMMC) with Embedded Energy Storage
ESS can be directly connected to the DC-side of the SMs in the MMC and the proposed HMMC.However, the SM capacitor voltage ripple appears directly across the ESS, and the low order harmonic oscillations have a detrimental effect to the lifetime and reliability of the ESS, while the SM voltage is directly linked to the SoC of its ESS.It is, therefore, preferable to use a DC-DC converter as an interface between the ESS and the SM capacitors.

Circuit Configuration
The DC-DC stage present between the ESS and the SM capacitors in MMC-based converters should operate in a manner so that the voltage at the ESS side is kept constant and without low-order harmonics.This task is simplified if the ESS is connected to the three-level FC-SM, as the voltage of the capacitor does not have low-order oscillations.Integration of the ESS in the proposed HMMC is shown in Figure 5a, with a bidirectional boost converter used at the DC-DC stage of the topology.This stage is also drawn with two devices in series, as that part of the circuit needs to withstand double the voltage the devices in the FC-SM.Various other configurations can be used [12], including high-ratio boost DC-DC converters, interleaved (Figure 5b) and multilevel DC-DC converters.In the case that isolation between the ESS and the SMs is required, the dual-active bridge (DAB) of Figure 5c with a high-frequency transformer stage can also be utilised.With the configurations of Figure 5, one ESS, common between the three phases of the converter, can be connected at each arm of the HMMC.An additional advantage of the configuration is that the SoC is common between the three phases, simplifying the energy balancing and control of the system.
The possible operating modes of the HMMC with the partial embedded ESS are: (i) DC to AC mode and vice versa; (ii) DC to ESS and AC mode; (iii) DC and ESS to AC mode; (iv) AC to DC and ESS mode; and (v) AC and ESS to DC mode.The first mode represents a typical DC-AC converter operation as analysed in Section 3; however, in the remaining modes of operation, additional controllers are required in order to achieve simultaneous energy balancing between all of the SMs.These modes are illustrated in Figure 6.As ESS is not included in any of the remaining HB-SMs, power flow solely from the ESS to the AC system (such as the case of a dedicated ESS converter) is not possible with the partial ESS configuration, as the converter cannot generate sufficiently high voltage at the AC terminals.

Power and Energy Balancing
In the case of the proposed HMMC and other topologies with partially-embedded ESS, the circulating current cannot be used to directly control the power and energy balance between the DC-, the AC-side and the ESS.The active power injection from the FC-SM DC-side will introduce an imbalance with non-ESS SMs.In order to achieve the required voltage balancing, the reference signal of the FCSM with the embedded ESS is modified to compensate for the power flow in or out of the ESS.This means that the conduction period of the FCSM increases or decreases based on whether the ESS is charging or discharging, while the currents within the arms remain the same.The current of the ESS (i bat,meas ) is used in the control of both the DC-DC converter stage, as well as the voltage balancing of the HMMC, as shown in Figure 7.The variation of the conduction interval for the FCSM means that the voltage generated by the HMMC arm is no longer equal to the reference.In order to compensate for the imbalance, the references of the remaining SMs need to be appropriately scaled, as well, avoiding a distortion of the output waveforms (Figure 7).This requirement sets some additional limitations on the proposed converter, as the maximum power that can be extracted out of the ESS is a function of the operating point of the converter, so that none of the references saturate.

Results
In order to demonstrate the operation of the converter, three different sets of simulation results are provided, one for the typical DC-AC converter operation and two with the partial embedded ESS in both charging and discharging modes supplying an RL load.The simulated converter consists of one three-level FC-SM and four HB-SMs per arm, generating a seven-level output voltage.The parameters of the simulation are given in Table 2.

DC-AC Converter Operation
When there is no power exchange between the ESS and the HMMC, the converter operates as a typical MMC-like converter.The seven-level output voltages and corresponding load currents are shown in Figure 8a,b, respectively.As expected, the multilevel output of the converter provides high quality output currents with a total harmonic distortion (%THD) of approximately 2.6%.The capacitor voltage of the HB-SMs are regulated to the reference voltage, while the voltages of the FC-SM capacitors exhibit a very small voltage ripple, as shown in Figure 8c.The higher order harmonics are eliminated from the circulating current, which only has a DC component (Figure 8d).
To further illustrate the major difference of the proposed HMMC compared to a standard MMC, Figure 9a shows the voltage of the internal capacitor of the FC-SM compared to the voltage of a normal HB-SM, demonstrating the elimination of the fundamental frequency harmonic ripple in the FC-SM.Assuming a maximum of 10% ripple on each SM capacitor voltage, Figure 9b shows the average SM voltage ripple across all SMs as the number of SMs increases.It becomes apparent that the advantages of the proposed HMMC are more apparent for a low number of SMs with the average SM voltage ripple converging towards that of the MMC as the number of HB-SMs increases.
Figure 10 shows the low-order harmonics of the SM capacitor voltage for the FC-SM and the HB-SM of the proposed HMMC.The capacitors within the three-phase, three-level FC-SM do not have any low-order harmonic ripple, while the HB-SM have both a fundamental and a second-order harmonic ripple in their capacitor voltages as a result of the current (Figure 8d) that flows through the arm and contains a fundamental frequency component and the fundamental frequency switching function of the SM.

Embedded ESS 1
Charging and discharging of the ESS is regulated from the dc-dc controller that acts as an 2 interface between the ESS and the capacitor of the FC-SM.The voltage of the capacitor does not exhibit 3 any significant ripple and there is no need for the second harmonic ripple to be compensated by the 4 dc-dc converter.This is not the case when ESSs are connected to HB-SMs individually per-phase.

Embedded ESS
Charging and discharging of the ESS is regulated from the DC-DC controller that acts as an interface between the ESS and the capacitor of the FC-SM.The voltage of the capacitor does not exhibit any significant ripple, and there is no need for the second harmonic ripple to be compensated by the DC-DC converter.This is not the case when ESSs are connected to HB-SMs individually per-phase.
Figure 11a,c shows the instantaneous and average power flow into the ESS that is connected to the FC-SM when the ESS is charging (Figure 11a) or discharging (Figure 11c).These results correspond to the power flow from the ESS connected to the FC-SM of the upper arms, while the same reference is used for the ESS in the lower arms.Extraction of unequal power out of the upper and lower ESS is outside of the scope of this paper and left for future work.The reference signals for the SMs of the upper arm of phase a when the ESS is charging and discharging are given in Figure 11b,d, respectively.
The conduction time of the FC-SM is adjusted accordingly to compensate for the additional power flow from the ESS in order to maintain the voltage balancing of the FC and HB SMs.The variation in the reference signals, as shown in Figure 11b,d, has a small effect on the output voltage harmonics; however, this effect is negligible due to the relatively large number of levels the HMMC is capable of generating.Figure 12a,b shows the load voltages generated by the converter when the ESS is charging and discharging, respectively.Similarly, the load currents are shown in Figure 12c,d The capacitor voltages of the FC and HB-SMs of the HMMC are shown in Figure 12e,f.The voltage of the FC-SM that the ESS is connected to is regulated from the controllers that perform the energy and voltage balancing tasks of the MMC.This leads to a decoupling between the control of the FC-SM and the ESS; however, the different time constants of the two controllers need to be taken into consideration.
The DC component of the circulating current can be used to control the power flow from the DC to the AC side and vice versa, while the presence of the ESS does not have an effect in eliminating the higher order harmonics of i circ .As can be seen from Figure 12g,h, the circulating current only contains a DC component with all of the higher order harmonics not present.Similarly to the MMC with or without ESS, injection of higher-order harmonics can be used to achieve additional control functions.

Conclusions
This paper proposed an hybrid modular multilevel converter (HMMC) as a combination of a three-phase FC-SM with single-phase HB-SMs.The main advantages of the proposed HMMC are the elimination of low-frequency voltage ripple in the capacitors of the FC-SM without introducing any further complexity into the circuit.This reduces the overall energy variation within the arms of the converter, compared to a typical MMC with HB-SMs for the same number of output voltage levels.As the three-phase configurations can only be used in the uppermost and lowermost location in the upper and lower arm, respectively, the proposed HMMC is well suited in applications with a relatively low number of SMs per arm.
The proposed HMMC is then extended to include a common energy storage element within the three-phase FC-SM.It is shown that the converter can provide multi-directional power flows from and to the DC-side, AC-side and ESS.The placement of the ESS within the three-phase FC-SM means that the DC-DC converter that interfaces with the with the SM does not experience low-order voltage ripple.The power flow from and to the ESS is regulated from the DC-DC converter, while energy and power balancing within the arms is handled from the HMMC controllers.However, due to the partial embedded ESS in the converter, the operation of the HMMC without the DC-side (as an ESS system supporting the AC network) is not possible.

Figure 4 .
Figure 4. Modulation of the proposed hybrid modular multilevel converter (HMMC): (a) phase-shifted (PS)-PWM carriers and reference signal (v mx,uj ); (b) Generation of the references and switching signals.

Figure 5 .
Figure 5. (a) FC-SM with embedded energy storage; (b) interleaved DC-DC stage; (c) isolated DC-DC stage based on the dual-active bridge (DAB) converter.

Figure 6 .
Figure 6.Power flow modes of the proposed hybrid modular multilevel converter (HMMC): (a) DC to AC mode and vice versa; (b) DC to the energy storage system (ESS) and AC mode; (c) DC and ESS to AC mode; (d) AC to DC and ESS mode; and (e) AC and ESS to DC mode.

Figure 7 .
Figure 7. Energy control for the HMMC with embedded ESS.

Figure 8 .Figure 9 .
Figure 8.Output waveforms under Mode i: (a) three-phase load voltages; (b) three-phase load currents; (c) SM capacitor voltages of Phase A; (d) load, circulating and arm currents of Phase A.

Fig. 10 showsFigure 10 .
Fig.10shows the low-order harmonics of the SM capacitor voltage for the FC-SM and the HB-SM

Table 2 .
Parameters of the simulation.