A Varied VSVM Strategy for Balancing the Neutral-Point Voltage of DC-Link Capacitors in Three-Level NPC Converters

In the research field of multilevel converters, three-level NPC (neutral-point-clamped) converters, which unfortunately may cause the deviation of the neutral-point voltage of DC-link capacitors, are widely discussed. Theoretically, virtual space vector modulation (VSVM) could guarantee the balance control of the neutral-point voltage. However, there still exist some uncontrollable space vector regions. Based on VSVM, this paper proposes a varied virtual space vector modulation (VVSVM) method for three-level NPC converters. Under complete modulation conditions, this method can control the balance of the neutral-point voltage of DC-link capacitors by adjusting the duty cycle of small vectors and regulating the current generated by virtual medium vectors. Compared with commonly used VSVM methods and mixed modulation strategies, this method is simpler and more practical. The effectiveness and validity of this method are verified by simulations and experiments.


Introduction
Multilevel converter topologies are considered to be the best choice for medium and high voltage applications for their less output harmonic voltage and higher voltage level.Among the multilevel converter topologies, the three-level neutral-point clamped (NPC) converter, as shown in Figure 1a, is a widely-researched topology [1,2].Nevertheless, owing to its topology characteristics, the capacitor's neutral-point voltage sometimes fluctuates when the three-level NPC converter works, and this causes harmonic distortion of the three phase output voltage, which limits its wide use [3][4][5].In recent years, the balance control of neutral-point voltage has been a hot topic and some strategies have been proposed in [6][7][8][9].Among these strategies, space vector modulation (SVM) is one of the most commonly used modulation strategies, which has the advantages of low switching frequency and better output voltage quality [10,11].However, when SVM is applied, the medium vectors will affect the neutral-point voltage, which will cause low-frequency oscillations in the neutral-point voltage under high modulation conditions [12].The paper [13] proposed an improved SVM excluding medium vectors.It can solve the low-frequency voltage oscillation issue.However, without the medium vectors to synthesize the space vectors, this will increase the possibility of distortion of the output voltage and increase the harmonic content of the output voltage.The paper [14] proposed a new SVM, which can balance the neutral-point voltage of DC-link capacitors by modulating the conduction time of the switch tube.
Furthermore, the papers [15,16] proposed a VSVM method which has been theoretically proven not to cause oscillation on the neutral-point voltage.This strategy employs an optimized virtual space vector with less distortion of the output voltage.However, the criterion to design the controller for neutral-point balancing is not presented in these papers.In practice, the balance of neutral-point voltage of DC-link capacitors is not very satisfactory, owing to the asymmetric parameters of components, switching delay and asymmetry of DC-link capacitors.Based on VSVM, the paper [17] proposed a method to balance the neutral-point voltage according to the fact that positive and negative small vectors have opposite effects on the neutral-point voltage.Although this method combines the merits of VSVM and SVM, the neutral-point voltage can't be controlled in some space vector regions when the modulation index m is between 0.667 and 1 (0.667 < m < 1), because there is not a pair of positive and negative small vectors in some vector regions.The papers [18][19][20][21] proposed some mixed strategies switching between the method of VSVM and SVM in some space vector regions, but the above methods are quite complex to manipulate.The paper [22] proposed a method to restrict the fluctuation of the neutral-point voltage of DC-link capacitors by optimizing the switch tube order.Because the three-level NPC converter itself has many vectors, increasing the number of switch sequence choices makes it more complex to programme.
In this paper, a varied virtual space vector modulation (VVSVM) is proposed on the basis of VSVM not affecting the balance of DC-link capacitors voltage theoretically [15], and the proposed strategy is designed to keep the balance of the neutral-point voltage of DC-link capacitors through adjusting the duty cycle of small vectors and regulating the current generated by virtual medium vectors.Unlike the conventional VSVM, when the modulation index is between 0.667 and 1, this strategy can maintain the balance of the neutral-point voltage of DC-link capacitors in all vector regions where the conventional VSVM strategy cannot.Experiment and simulation have verified the effectiveness of the proposed strategy.

Varied Virtual Space Vector Modulation
In the typology of a three-level NPC converter, as shown in Figure 1a, P, O and N represent three output voltage values: Udc/2, 0, −Udc/2, where Udc is the DC-link voltage.Figure 1b is the distribution diagram of the voltage vectors, from which we can know that the NPC converter has 27 space vectors.According to the definition and distribution of virtual space vectors in VSVM [15,16], this paper designs a group of new varied virtual space vectors.Taking sextant I as an example, the virtual voltage vectors are established in sextant I, as shown in Figure 2a.

The Definition of Varied Virtual Space Vectors
(a) Definition of virtual small vectors: the virtual small vectors are built under the precondition that positive and negative small vectors have opposite interactions on the neutral-point voltage fluctuation.Taking the positive and negative small vectors (POO (−ia), ONN (ia)) for example, the virtual small vector (VVS1) is formed as follows (VVS2 is formed in a similar way): Assuming that the three phases current (ia, ib, ic) stay unchanged in a short switching period TS, during the duty cycle TVS1 of a virtual small vector VVS1, the three phase load current ia, ib, ic is connected to the neutral-point O, the charge flowing out from which is represented as: It is noted that when k = 1/2, the charge from the neutral-point O: qVS1 = 0, so during the duty cycle TVS1 of virtual small vector VVS1, the neutral-point voltage of DC-link capacitors is not affected.
(b) Definition of varied virtual medium vectors: assuming that during a switching period TS, the three-phase currents ia, ib, ic stay steady, and ia + ib + ic = 0.By combining the small vectors VPPO (ic) and VONN (ia) and the medium vectors VPON (ib), a virtual medium vector VM is synthesized as follows: From Equations (3) and (4), it can be seen that during the duty cycle Tm of virtual medium vector VM, the three phase load current will be connected to the neutral-point O respectively at a different time.The charge flowing out from the neutral-point (O) is described as follows, during the duty cycle Tm of the virtual medium vector: Equation ( 6) describes the relationship between the voltage of capacitors and the charge flowing out from the neutral-point: During the duty cycle Tm of varied virtual space vector, the following conclusions are drawn according to Equations ( 5) and ( 6): (1) When k1 = 2/3, the virtual medium vector locates at the point b, and the charge qTm flowing out from the neutral-point O is zero.This virtual medium vector will not cause a fluctuation of the neutral-point voltage, which is the same as the neutral-point voltage in the traditional VSVM (modulation index m = 0.667).Because the length of the virtual medium vector stays steady in the process of synthesizing the voltage space vector Vref, the traditional VSVM can't use the virtual medium vector to balance the neutral-point voltage of DC-link capacitors.
 If ib > 0, the charge flowing out from the neutral-point O: qTm < 0, and UC1 gets smaller; UC2 get larger. If ib < 0, the charge flowing from the neutral-point O: qTm > 0, and UC1 gets larger; UC2 get smaller.
 If ib > 0, the charge flowing from the neutral-point O: qTm > 0, and UC1 gets larger; UC2 get smaller. If ib < 0, the charge flowing out from the neutral-point O: qTm < 0, and UC1 gets smaller; UC2 get larger.
(c) Definition of virtual zero vectors: VV0 = VOOO.The virtual zero vectors don't affect the neutral-point voltage.

Judgment of Small Regions in 60° Sextant
As shown in Figure 2a, taking sextant I for example, it can be divided into five small regions (1)-( 5), according to the location of vectors (Udc denotes the DC-link voltage, Vref is the reference vector, θ is the reference vector angle, Ud denotes Udc/3 and the modulation index is defined as: ).
The length of varied virtual medium vector can be represented by Equation (7): As shown in Figure 2d, the following formula is derived as: where: As shown in Figure 2c, from Equations ( 8) and ( 9), the m1 is written as: Similarly, the calculation formulas of m0, m1, m2, m3, m4 are expressed as follows: The small region in which the reference vector locates is confirmed according to Equations ( 7) and (11), the modulation index and the regulation of judging small region (Table 1).Table 1.Judging the small region of the reference vector.

Synthesis of Vectors
From the divided small regions in sextant I above, three virtual voltage vectors are determined to synthesize the reference vector.To simplify the calculation, we choose 60° coordinate (g_h coordinate) to calculate the time of vector synthesis.Taking the space voltage vector Vref which locates at region (2) for example, the duty cycle of the relative vectors is calculated as follows.
As shown in Figure 2b, in the g_h coordinate, the reference voltage vector Vref can be represented as: According to the principle of vectors synthesis, the modulation rules of the nearest three vectors are established as follows: where (X = Ud(1 − k1/2) represents the projection of virtual medium vector on the g-axis and h-axis.) From Equations ( 12) and ( 13), we obtain the following equation: ( 2 ) Similarly, the duty cycle of other virtual vectors is calculated, and Table 2 shows the duty cycle of virtual vectors in sextant I.

The Amplitude of the NP Voltage Oscillations
In a switching period, the NP voltage ripple of the NPC converter is defined as: T is the duty cycle of the virtual medium vector, C is the value of the DC-link capacitors.Thus, increasing the value of the capacitors and the switching frequency is helpful for balancing the neutral-point voltage.

Neutral-Point Balancing Algorithm in Small Region (1)
Taking sextant I for example, we choose the small vectors to synthesize the reference vector when reference vector Vref locates in small region (1) in this paper.Assuming that the three phase output currents (ia, ib, ic) stay constant in a switching period TS, where dmin symbolizes the duty cycle of virtual small vector (V1), dmin_p and dmin_n respectively represents the duty cycle of the positive small vector (VPOO) and negative small vector (VONN), and dmin_p + dmin_n = dmin; imin_p(−ia) represents the neutral-point current of dc-link capacitors during the duty cycle of positive small vector; imin_n(ia) represents the neutral-point current of DC-link capacitors during the duty cycle of negative small vector.As shown in Figure 1a, the charge qout flowing out of the neutral-point O over a switching period TS can be represented as follows: ( 1) During the switching period TS, the relationship between the capacitors voltage and the charge flowing out of the neutral-point O can be represented as: From Equations ( 16) and ( 17), we can obtain the following equation: If the voltage transducer detects the deviation (ΔU) of neutral-point voltage, then during the next switching period the current of the positive and negative small vectors should generate voltage -ΔU to offset the deviation, and keep the balance of the neutral-point voltage of DC-link capacitors.Therefore, according to Equation (18), we could calculate the value of control factor k in the next sampling period.

Balancing Strategy for Neutral-Point Voltage in Small Regions (2)-(5)
The neutral-point current generated by the virtual medium vector is used to offset the voltage deviation of DC-link capacitors, which can realize the voltage balance in the small regions (2)-( 5).As a result, the balance of neutral-point voltage can be maintained in VVSVM, when the modulation index is between 0 and 1 (0 < m < 1).Taking sextant I for example, the location of virtual medium vector could be determined by detecting the fluctuation of neutral-point voltage in the next sampling period to maintain the balance of the neutral-point voltage.During the duty cycle of virtual medium vector, the following equation is obtained according to Equations ( 5) and ( 6): If the reference vector voltage Vref locates between small region (2) to ( 5) and the deviation ΔU of the neutral-point voltage is detected, the virtual medium vector current could generate −ΔU voltage to offset the deviation during the next switching period TS.According to Equation (19), the fluctuation of neutral-point voltage of DC-link capacitors can only judge whether the virtual medium vector locates at a-b or b-c as shown in Figure 2a.Because the neutral-point voltage doesn't change a lot in a sampling period, this paper uses Tm' of the previous sampling period to calculate the approximate value of k1.

Simulation and Experimental Verification
This section presents the simulation and experiment results of three level neutral-point NPC converter to verify the effectiveness of the proposed VVSVM strategy by comparing it with the VSVM strategy.Simulation and experiment environments are performed as follows: DC-link voltage: Udc = 400 V; three-phase resistance-inductance load: R = 15 Ω, L = 10 mH; DC-link capacitors: C1 = C2 = 2000 μF; sampling frequency: 8 kHz; fundamental frequency: 50 Hz.The dead time of the system is set as 3 μs and the modulation index is 0.83.

Simulation Results
To verify the balancing performance of the proposed modulation technique, the initial voltage of the DC-link capacitors is set as: UC1 = 230 V, UC2 = 170 V.In the simulation process, from 0 s to 0.02 s, the deviation of capacitors voltage is maintained at 60 V by VSVM and VVSVM, and after 0.02 s the deviation of capacitors voltage is controlled to be zero.
Figure 3a-c shows the simulation results of VSVM which uses small vectors to balance the neutral-point voltage.Figure 3d-f shows the simulation results of the proposed VVSVM.By comparison of Figure 3c,f, either the VSVM or VVSVM can balance the capacitors voltage, but the dynamic balancing process of the capacitors voltage in VVSVM is faster than that of the capacitors voltage in VSVM.
When the modulation index is 1 > m > 0.667 in VSVM strategy, the tip of reference vector (Vref) is bound to fall in the region (5) of sextants I-VI because there is no pair of positive and negative small vectors for synthesizing Vref in the small region (5).Thus, the VSVM strategy can't balance the deviation of capacitors voltage in this region.However, in the region (5), the proposed VVSVM strategy can control the balance of neutral-point voltage by regulating the current of the virtual medium vectors in region (5).So the balancing adjustment time of VVSVM is less than that of VSVM.From Figure 3a,d, it can be seen that line-line voltage waveform varies responding to the capacitors voltage varying through using VSVM and VVSVM.4b,d, it can be seen that the voltage of the DC-link capacitors barely changes responding to changing the load, using the VVSVM.However, in VSVM strategy the DC-link capacitors voltage fluctuates obviously.Figure 5 shows the simulation results of VSVM and VVSVM in the case of varying DC-link voltage.The DC-link capacitors voltage is initially set as UC1 = 175 V, UC2 = 175 V.The DC-link voltage increased from 350 to 400 V at 0.04 s.Owing to the currents amplitude varying little along with transformed DC-link voltage, it can be seen from Figure 5c,f that the balancing effectiveness of VVSVM is the same as that of VSVM from the simulation results.However, it can be concluded that the VVSVM can better control the voltage balancing of the DC-link capacitors under varying DC-link voltage conditions.

Experiment Results
To verify the effectiveness of the proposed VVSVM, three-level converter is made of six IGBT (Insulated Gate Bipolar Transistor) dual-modules 2MBI100U4H-170.The main processor is implemented with TMS320F28335 DSP (Digital Signal Processor) controller and EP3C10E144C8 FPGA (Field Programmable Gate Array) is used to generate and output pulse width modulation (PWM) signals for the converter.
Figure 6a,b shows the dynamic balancing of the DC-link capacitors voltage in VSVM and VVSVM, respectively.The voltage deviation is kept at a set value by subtracting a deviation value from the voltage difference of the DC-link capacitors, so the initial deviation between UC1 and UC2 can be controlled.In the initial conditions, the deviation of UC1 and UC2 is keep at 60 V, and then controlled to be 0 V. From Figure 6a,b, it can be seen that the balancing time of the proposed VVSVM is half of that of VSVM, which is significant to the application of the high power and large current.Thus it could be concluded that the proposed VVSVM has a good effectiveness of balancing the capacitors voltage.Figure 7 shows the balanced state waveforms of the line-to-line voltage and the DC-link capacitors voltage using VSVM and VVSVM.From Figure 7b, it can be seen that when conducting the proposed VVSVM, the line-to-line voltage is a steady three-level wave, that's to say, UC1 and UC2 stay steady.Comparing Figure 7c,d, the ripple amplitude of the capacitors voltage in VVSVM is smaller than that in VSVM.The FFT (Fast Fourier Transformation) analysis of the output line-to-line voltage with VSVM and VVSVM is illustrated in Figure 7e,f.THD of the VSVM is about 3.01% and the THD of VVSVM decreases to 2.96%.The 5th and 7th harmonics are included in three level wave of the line to line voltage in VSVM and VVSVM.Figure 8a,b shows the transient behavior of VSVM and VVSVM respectively, when the load varies abruptly.An asynchronous motor is used to verify the effectiveness of the proposed VVSVM in the case of varying load.A step change in the load is done, the asynchronous motor current varies from 7 to 20 A as shown in Figure 8.Since the asynchronous motor current can't vary abruptly in a very short time, thus, from Figure 8a,b, the balancing performance of the proposed VVSVM seems to be the same as that of VSVM.However, from the experimental results, the proposed VVSVM has better effectiveness of balancing voltage of DC-link capacitors compared to VSVM.It can be concluded that the capacitors voltage ripple is suppressed satisfactorily under the case of varying load when employing VVSVM.Figure 9a,b shows the experimental results of VSVM and VVSVM when the DC-link voltage is changed from 300 to 400 V.The figures show that the load current varies responding to changing DC-link voltage.From the analysis above, the neutral-point current flowing in/out of the capacitors is the only reason causing the capacitors' voltage unbalance, so the difference of balancing effectiveness in both VSVM and VVSVM is not very obvious in the case of varying DC-link voltage.However, from the experimental results, it can be seen that the proposed VVSVM is also able to maintain the neutral-point voltage balance in this case.

Conclusions
This paper proposed a VVSVM strategy for balancing the neutral-point voltage through adjusting the duty cycle of small vectors and regulating the current generated by virtual medium vectors.In the case of higher modulation index (m > 0.667), compared with VSVM which can't balance the neutral-point voltage in some vector regions (small region (5) in the paper), the proposed VVSVM can perfectly keep the balance of neutral-point voltage in all the vector regions.Simulation and experiment show that when employing VVSVM, the balance of neutral-point voltage can be effectively maintained with less distortion of the output voltage, thus providing an effective strategy for high voltage applications.

Figure 1 .
Figure 1.Schematic of a three-level NPC converter.(a) Topology structure of three-level NPC converter; (b) Distribution diagram of voltage vectors.

Figure 2 .
Figure 2. Distribution of varied virtual space voltage vectors in sextant I; (a) Definition and distribution of varied virtual space voltage vectors in sextant I; (b) Virtual space voltage vectors in g_h coordinate; (c) Distribution diagram of varied virtual vectors in Sextant I (60° Sextant); (d) The calculation of m1.

where 1 u
is the amplitude of the ripple on the neutral-point voltage, ave I is the average neutral-point current, m

Figure 3 .
Figure 3. Simulation results of balancing DC-link capacitors voltage; (a) balancing process of line-to-line voltage in VSVM; (b) three phase currents in VSVM; (c) balancing process of DC-link capacitors voltage in VSVM; (d) balancing process of line-to-line voltage in VVSVM; (e) three phase currents in VVSVM; (f) balancing process of DC-link capacitors voltage in VVSVM.

Figure
Figure 4a,b shows the simulation results of VSVM under the condition of varying load.Figure 4c,d shows the simulation results of VVSVM under the condition of varying load.The voltage of DC-link capacitors is initially set as UC1 = 200 V, UC2 = 200 V.The load resistance suddenly changes from 15 to 8 Ω at 0.02 s.It can be seen that the load currents vary from 12 to 21 A at 0.04 s.Comparing Figure 4b,d, it can be seen that the voltage of the DC-link capacitors barely changes responding to changing the load, using the VVSVM.However, in VSVM strategy the DC-link capacitors voltage fluctuates obviously.Figure 5 shows the simulation results of VSVM and VVSVM in the case of varying DC-link voltage.The DC-link capacitors voltage is initially set as UC1 = 175 V, UC2 = 175 V.The DC-link voltage increased from 350 to 400 V at 0.04 s.Owing to the currents amplitude varying little along with transformed DC-link voltage, it can be seen from Figure5c,f that the balancing effectiveness of VVSVM is the same as that of VSVM from the simulation results.However, it can be concluded that the VVSVM can better control the voltage balancing of the DC-link capacitors under varying DC-link voltage conditions.

Figure 5 .
Figure 5. Simulation results of varying DC-link capacitors voltage; (a) varying process of line-to-line voltage in VSVM; (b) three phase currents in VSVM; (c) varying process of DC-link capacitors voltage in VSVM; (d) varying process of line-to-line voltage in VVSVM; (e) three phase currents in VVSVM; (f) varying process of DC-link capacitors voltage in VVSVM.

Figure 7 .
Figure 7. Experimental results of VSVM and VVSVM; (a) the line to line voltage and the load current in VSVM; (b) the line to line voltage and the load current in VVSVM; (c) balanced steady state of UC1 and UC2 in VSVM; (d) balanced steady state of UC1 and UC2 in VVSVM; (e) FFT (Fast Fourier Transformation) analysis of line-to-line voltage in VSVM; (f) FFT analysis of line-to-line voltage in VVSVM.