Active Power Filtering Using the Zdpc Method under Unbalanced and Distorted Grid Voltage Conditions

In this paper, we propose a new Zero Direct Power Control (ZDPC) technique for active compensation of harmonics and reactive power, using shunt active power filter (SAPF), based on cancellation of instantaneous active and reactive power disturbances by comparison with their zero references. To separate harmonic and fundamental components of the line voltage and current a highly selective filter (HSF) has been used. Depending on the power errors and line voltage vector position, a switching table produces the appropriate control vectors leading to the active and reactive power variation required to reach the zero power references, even under grid voltage unbalanced and distorted conditions. The experimental validation of the proposed ZDPC has been performed. The results are compared to other recent techniques to demonstrate the superiority and feasibility of the proposed strategy.


Introduction
The harmonic pollution affects all domestic and industrial grids. No modern environment such as computers, servers, air conditioners, speed controllers etc. can escape this equipment pollution. All these so called "non-linear" loads seriously affect the quality of the grid current and voltage [1,2].
The different current disturbance identification methods can be classified into two families. The first one, in the frequency domain, is based on the use of a Fast Fourier Transform (FFT) to extract the current harmonics. This method is well suited for loads where the harmonic content varies slowly. It also offers the advantage of selecting individual harmonics and compensating the most dominant harmonic. It should be pointed out that this method is too time consuming because of all the required real-time transformations for the extraction of harmonics.
The second family, in the time domain, is based on the computation of instantaneous power. The method of instantaneous active and reactive power was developed in many applications [1][2][3][4]. But the disadvantage is that it gives correct results only for a healthy grid, i.e., balanced and undistorted voltage [5,6].
The principle of DPC for Pulse Width Modulation (PWM) converters was proposed for the first time in 1986 [7] and developed later for other many applications. The DPC purpose essentially was to remove both the PWM modulator and the internal regulation loops by replacing them by a predetermined switching table. The first DPC control type configuration has been proposed in [8], for the direct control of instantaneous active and reactive power of three-phase PWM rectifiers without grid voltage sensors. Based on this approach, many studies have been developed for different power topologies. The common objective of these studies was to ensure sinusoidal currents and a unity power factor with a decoupled control of active and reactive power [9].
The standard DPC requires zero reactive power reference, while the active power reference is calculated from the Direct Current (DC) bus controller output [10]. This paper proposes a DPC technique, which in contrast to standard implementation, requires zero active and reactive power disturbance references for rejecting any disturbance due to harmonics [11,12]. That is why it is called Zero DPC or ZDPC. This paper presents the proposed ZDPC method.
It is organized as follows; Section 2 presents the principle of the standard DPC. Section 3 deals with the detailed operation principle of the proposed ZDPC method. In Section 4, simulation results under different conditions (balanced, unbalanced, distorted grid voltage) are presented and compared to standard DPC [10]. Finally, in Section 5, we present the experimental validation of the proposed method. Then we conclude the paper.

Principle of Standard DPC
The block scheme in Figure 1 shows the standard DPC configuration where the zero reactive power qref and active power pref reference (delivered from the DC bus voltage controller) are compared with the calculated ps and qs values given respectively by Equations (1) and (2), by means of two level hysteresis controllers [9,[13][14][15]: where ps(t) and qs(t) are the instantaneous real and imaginary source power.

The Sector Choice
The digitized variables dps, dqs and grid voltage vector position θ (Equation (3)), form a digital word, for access to the address of switching table to select the appropriate control voltage vector: For this purpose, the stationary coordinates are divided into 12 sectors, as shown in Figure 2, and the sectors can be numerically expressed as [9,13,14,16]. The digitized signal errors dps, dqs and voltage phase θn are the inputs of switching table shown in Table 1 whose output is the switching state (Sa, Sb, Sc) of the converter. By using this switching table, the optimal state of the converter can be selected uniquely during each time interval according to combination of the table inputs. The selection of the optimal switching state is performed so that the power errors can be restricted within the hysteresis bands. ( − 2). π 6 ≤ θ ≤ ( − 1). π 6 = 1,2, … … . ,12

Hysteresis Controller
The main idea of the DPC method is to maintain the instantaneous active and reactive power within a desired band. This control is based on two hysteresis comparators whose input is the error between the reference and estimated values of the active and reactive power [9,13], given by Equations (5) and (6), respectively: The hysteresis comparators are used to provide two logic outputs dps and dqs. The state "1" corresponds to an increase of the controlled variable (ps and qs) while "0" corresponds to a decrease, following Equations (7) and (8):

PI Controller
The DPC method must provide regulation of the DC bus to maintain the capacitor voltage around the voltage reference (Vdcref). For this purpose a PI controller is generally used [13]. Figure 3 shows the simulation model of the controller.
where ξ: damping coefficient (ξ = 0.707), ω : natural pulsation and K: anti-windup gain. Figure 4 shows the structure of the proposed ZDPC. In this control strategy, the active and reactive power disturbance references are set to zero [11,12]. We note that in this structure the phase locked loop (PLL) is no longer needed. The HSF filter is used to separate the fundamental and harmonic components of the line currents and voltages to perform the power compensation ( Figure 5).

The HSF Filter
To improve the performance of the conventional instantaneous power method, the HSF has been implemented, for extracting the fundamental component of the current and voltage in the synchronous frame without phase shifting or amplitude errors [17]. The block diagram of HSF is shown in Figure 6. The transfer function of the filter can be expressed as follows [13]: From the transfer Equation (11), we get: where the quantities αβ x  and xαβ represent the output and input of the filter, respectively. They may be either vαβ or iαβ. We note that for pulsation ω = ωc, the phase shift introduced by the filter is zero and the gain is unity. We also observe that K value decrease improves the selectivity of HSF (Figure 7), we chose K = 20.  ̃=̂α ℎα +̂β ℎβ (14) with ihα and ihβ given respectively by Equations (15) and (16): where the terms ihα and ihβ are the harmonic components in αβ axis. Meanwhile, the instantaneous reactive power is defined by:

Generation of Control Vector
Adding the AC component ̃ of the instantaneous active power, related to both current and voltage disturbances, to the active power pc, necessary for the dc bus regulation, we obtain the active power disturbance pp which can be can be expressed as: To compensate the active and reactive power (pp and qs) disturbances, a comparison with their zero reference is done. The comparison results go through a hysteresis block that generates dps and dqs. Depending on the selected sector (θn) and (dps, dqs), the appropriate control vector (Sa, Sb, Sc) is produced by using the switching table (Table 1).

Simulation Results
To achieve the simulation of ZDPC technique, a model in Matlab/SIMULINK frame and SimPower-Systems Block set, R2008b, Mathworks, USA, 2008, is developed. To compare the results obtained to those given by [10], the same system parameters specified in [10] and in the Appendix have been used. The simulation is conducted for different grid voltage source conditions: Case A: balanced sinusoidal grid voltage. Case B: unbalanced sinusoidal grid voltage. Case C: balanced distorted grid voltage. Case D: unbalanced and distorted grid voltage.  Table 2. The results are shown in Figure 8, and summarized in Table 3. We observe a good compensation for the line current, with a THD is = 0.86% reduced below the standard IEEE-519.  For this case, the phase-b is unbalanced (va = 220 V, vb = 180 V, vc = 140 V), which gives a Total Unbalance (TUv = 22.2%). Figure 9 and Table 3 show the results; compensation of line currents is low (THDis = 12.48%, TUis = 4.20% and TUil = 10.37%). In this case the grid voltage is balanced but is distorted with a THDv = 12.83% as shown in Table 2. The simulation results are shown in Figure 10, where we observe a low compensation line current (THDis = 6.09%) for the three phases. Summary of the results is given in Table 3.

Case D: Unbalanced and Distorted Grid Voltage
This is the worst case, as it is shown in Figure 11 and Table 2. The simulation results are shown in Figure 11 and Table 3. Compensation of line current is low (THDis = 6.25%, TUis = 5.07% and TUil = 8.43%).  Figures 12-15 show the simulation results of the proposed ZDPC technique for the different conditions mentioned above and with parameters given in Table 2.

Case A: Balanced Sinusoidal Grid Voltage
The results are shown in Figure 12. It is observed that there is a good compensation for the line current, and the THD is reduced below the standard IEEE-519 (THDis = 0.65%). Table 3 presents the comparison between standard DPC and ZDPC. One can observe that both techniques give nearly the same results.

Case B: Unbalanced Sinusoidal Grid Voltage
The phase-b is unbalanced by 20% relatively to phase-a (vb = 180 V), while the phase-c is unbalanced by 40% relatively to phase-a (Vc = 140 V) with TUv = 22.2%. Based on results of Figure 13, we observe that unlike standard DPC, the proposed ZDPC shows its good performance for balancing and improving the line currents (TUis = 1.27% and THDis = 1.24%). Table 3 summarizes the comparison between standard DPC and ZDPC.

Case C: Balanced Distorted Grid Voltage
In this case the grid voltage is balanced but distorted with a THDv = 12.83% as shown in Table 2. The simulation results in Figure 14, prove the good performance of ZDPC (THDis = 0.72%) comparatively to standard DPC. Table 3 summarizes the main results comparison.

Case D: Unbalanced and Distorted Grid Voltage
This is the worst case. It corresponds together to unbalanced and distorted voltage as shown in Figure 15 and Table 2. The simulation results are shown in Figure 15 confirm the robustness of ZDPC. Comparatively to standard DPC we can observe that the grid current is quasi sinusoidal (THDis = 1.48%), balanced (TUis = 1.41%) and synchronized with the grid voltage. Table 3 summarizes the comparison results.

Comparison of ZDPC and HSF-DPC [10]
In this section we compare the ZDPC to HSF-DPC published recently in [10], with the same grid voltage conditions, Table 4, and parameters in Appendix. Table 5 shows the simulation results obtained by both the proposed ZDPC and HSF-DPC given in [10] for three cases (A, B, C). We observe that the proposed ZDPC leads to better results whatever the conditions, unlike HSF-DPC of [10] only suitable for the case of unbalanced and distorted grid voltage and in addition in [10] there are no experimental validation.

Experimental Results
To validate experimentally the proposed ZDPC, the experimental set up shown in Figure 16 has been used. The control technique is implemented in dSPACE DS1104 environment, with the parameters given in Appendix. Two different conditions are considered: -Case A, the grid voltage is balanced. -Case B, the grid voltage is unbalanced.

Case A: Balanced Sinusoidal Grid Voltage
The grid voltage is balanced (vs = 23 V rms). Figure 17a,b shows a good compensation of the line current (THDisa = 4.7%, THDisb = 3.7%, THDisc = 4.4%), which is less than the IEEE-519 standard, and with a power factor close to unity.

Case B: Unbalanced Sinusoidal Grid Voltage
The grid voltage is unbalanced for two phases (a and b) relatively to phase-c (Vsa = 19.5 V, Vsb = 17.6 V, Vsc = 22.6 V), with TUv = 7.5%). Figure 18b,c shows a good compensation of the line current (THDisa = 5.9%, THDisb = 4.4%, THDisc = 5.3%), and a balance (TUis = 0.7%), synchronized with grid voltages (Figure 18d,e). Balance of the line current is well observed in the vector diagram (equal 0.7%), Figure 18d. This can be further improved with the availability of the appropriate experimental parameters.

Conclusions
In this paper a new DPC technique called ZDPC, suitable for harmonic and reactive power compensation, has been proposed. Its effectiveness whatever the grid voltage conditions (unbalanced,