Design and Implementation of a High-Power-Density DC Power Supply Based on a Novel Integration of Z-Source and Isolated Full-Bridge DC–DC Converter Topologies

Abstract

High-voltage DC (HVDC) power supplies are essential for several advanced applications, including medical imaging, aerospace systems, and additive manufacturing. Traditional HVDC supplies often suffer from performance limitations due to high transformer turn ratios, which increased stray capacitance and degraded inverter performance. This paper proposes a novel two-stage HVDC power supply architecture that addresses these challenges by combining a Z-source converter with a full-bridge inverter, both enabled by high-performance Silicon Carbide (SiC) devices. The first stage boosts the rectified line voltage to 2 kV using a Z-source topology and inverts it at high frequency, while the second stage employs a high-voltage, high-frequency (HVHF) transformer and a voltage doubler to achieve a regulated 10 kV DC output. Simulation results using PLECS and experimental validation demonstrate the effectiveness of the proposed design in minimizing the reflected capacitance, enabling constant-frequency operation at the boundary of continuous conduction mode for improved efficiency, and providing high power density and compactness. This approach offers a promising solution for high-efficiency, high-voltage applications.

1. Introduction

High-Voltage DC (HVDC) power supplies are required for several applications across various areas, such as medicine, communication, and aerospace. Typical applications include X-ray systems, traveling wave tubes, magnetrons, and pulsed power. Some interesting applications may be found in [1] (Klystron amplifier for space applications), ref. [2] (X-ray generator, 200 kV, 80 kW, +50 kHz LCC), ref. [3] (Magnetron power supply; 750 V–2.5 kV, 100 kHz), ref. [4] (Ion pumps, 1.35 MHz, 49 V up to 7 kV, 80 W) and [5] (Electro-Aerodynamic Propulsion System for unmanned aerial vehicles 140 V to 40 kV, 600 W). Recently, they have been used in additive manufacturing applications. However, designing these supplies is not easy. The selection of a suitable topology for the voltage and power levels, the layout of the system, and the design of the transformer are critical to achieving high efficiency and performance, and ensuring safe and reliable operation. HVDC power supplies employ semiconductor switches and diodes, energy storage devices, and transformers, depending on the application, to step up the voltages. Switched capacitors, switched inductors, voltage doublers/multipliers, voltage lifters, and magnetic coupling circuits are the main technologies used in these supplies. Each technique has its own advantages and disadvantages in terms of efficiency, cost, power density, reliability, and ease of application. Although earlier HVDC supplies relied on voltage multipliers, topologies using power semiconductors have become the standard solution with advances in technology. A typical HVDC supply includes a pulse width modulated (PWM) inverter that switches the rectified line voltage, and a high-voltage, high-frequency (HVHF) transformer that steps up the inverter output. The frequency must be high to reduce the transformer size and increase the supply’s response speed. The secondary voltages of the transformers are usually increased by using one or more stages of diode voltage multipliers to reach the required levels. Although this structure is simple, it has some basic problems: Because the voltage difference between the primary and secondary windings of the transformer is high, there must be sufficient spacing between the secondary windings and their layers to keep the field below 5 kV/mm. This, in turn, increases the leakage inductance [6,7]. A more serious problem arises from the large turn ratio, because the secondary should have significantly more turns than the primary. Because the reflected value of the stray capacitance is proportional to the square of the turn ratio, a large capacitance appears across the primary, which deteriorates the inverter’s operation.

The most important factors that affect the stray capacitance are (a) the dielectric constant of the insulating material, (b) the geometry of the transformer, and (c) how the winding sections are connected and how the windings are arranged [8]. The voltage distribution induced by high-frequency eddy currents is also effective [9]. The total leakage inductance can be kept low by reducing the insulation distance between the primary and secondary windings and the number of primary turns [10]. Reducing the primary turn number increases the core size to maintain a low peak flux density. Stray capacitance can be minimized by segmenting secondary coils [11,12]. However, there is a limit to the number of segments that can be used when compactness is considered.

There are two different solutions proposed in the literature to avoid the negative effects of stray capacitances: (a) Utilizing LCC and similar resonance structures that incorporate the stray component in the resonance tank, and (b) utilizing modular systems.

The LCC topology provides good voltage gain with perfect open-circuit and short-circuit behavior [13,14]. Most solutions in the literature use this topology [7,13,14,15,16,17,18]. The most recent applications are [1] (200 V–70 kV, 5 kW, 50 kHz), ref. [2] ( 200 kV, 80 kW, 50 kHz), ref. [19] (400 V AC–160 kV DC, 200 W; 60–200 kHz), ref. [20] (25 V–1 kV, 0.9–1.5 MHz). A good survey on the applications of LCC converters is available in [21].

Modular structures allow the use of lower-rated switches and scale up. Transformers, power converters, and rectifiers may be built in modules in these structures. Eight modular structures were proposed for different voltage and power levels in [22]. Each structure differs in terms of insulation voltages, pulse sharpness, voltage drop, efficiency, and ease of packaging. The paper suggests selecting the most appropriate architecture to achieve either the overall system performance or the most critical performance. Another modular HVDC supply study was presented in [23], which used planar transformers with four different modular structures. If the voltage distribution in the modular structure is uneven, achieving transformer insulation becomes more difficult, thereby increasing the size. High-frequency AC stress is another parameter to consider, because it induces dielectric losses. Low AC frequency stress and even voltage distribution were achieved with a three-winding design, but this complicates the insulation design. An optimal design combining a proper modular structure with two-winding planar transformers was proposed in the study.

Topologies that utilize stray components in their resonance tanks provide a good solution; however, their design is challenging. LCC performance degrades owing to large circulating currents and switch turn-off losses when a wide voltage range is required [24]. In addition, the reflected capacitance may change during operation as the voltage varies, potentially degrading the performance [25]. Modular structures, on the other hand, do not suffer from variations in stray component values or circulating currents, but the number of components increases significantly, and gate-drive circuits require attention. Full-bridge converters are widely used for high-voltage DC power supplies but suffer from parasitic effects and switching losses [26].

The solution proposed in this paper is based on the following question: Is it possible to operate the inverter at high voltages so that the turn ratio of the HVHF transformer does not need to be high, eventually resulting in lower reflected capacitance and allowing constant frequency operation at the boundary of continuous conduction mode for better efficiency? A viable solution to this problem would require adequate switches and a proper topology to step up the voltage.

Silicon Carbide (SiC) devices have revolutionized power electronics and are now the natural choice for HVDC power supplies. (SiC) MOSFETS are used in the inverter at the input stage, while SiC diodes are used in the voltage multipliers in the secondary side [3,27]. SiC diodes do not suffer from the reverse recovery phenomenon. They also remain stable at high temperatures with respect to forward characteristics. There are also papers reporting HVDC power supplies operating at very high switching frequencies utilizing Gallium Nitride (GaN) devices, such as [28], which reports 1 MHz, 300 V to 5 kV power supply, and [29] reporting 1.33 MHz, 48 V–7 kV, 80 W. Considering the voltage and power range of the project, SiC devices were selected. Additionally, recent full-bridge designs using advanced magnetics and SiC devices enhance efficiency and power density in practical implementations [30].

Classical boost-type topologies cannot provide very high voltage step-up ratios. Their gain is limited by the internal resistance of the inductor. The voltage stresses are also very high for these converters. Flyback converters are a viable option because of their simple structure; however, the high-voltage stress on the switch remains a limiting factor. Some of these converters use coupled inductors to achieve higher voltage gain. Ref. [31] proposed using coupled inductors for voltage isolation, along with a zero-voltage transition interleaved boost converter to step up 40 V to 760 V at 1 kW. Ref. [32] used coupled inductors in a double boost flyback converter to step up 48 V to 800 V at 1 kW power. This topology can double the voltage gain while maintaining a low switch voltage. Ref. [33] proposed a high-gain converter utilizing coupled inductors and voltage multiplier cells with an interleaved structure. The converter produced 800 V from 48 V, with an output power of 1 kW. Ref. [34] has proposed a flyback converter to obtain 1089 V from 12 V; however, the power is very low (7.5 W).

Another class of high-gain DC–DC converter topology is the Z-source converter. They have received significant attention owing to their high voltage gains and lower switch stresses. The voltage gains of these converters are usually proportional to 1/(1–2d), where d is the duty cycle, limited to 50%. Impedance source converters, in general, combine the advantages of voltage and current source converters [35]. They can step up or step down the voltage by using a single switch. They can be short-circuited or open-circuited without any damage. Several Z-source topologies have been reported in the literature. Refs. [36,37] present a good review on these converters. However, most of the proposed applications are for renewable energy systems, where an input voltage of approximately 25 V is stepped up to approximately 400 V [38,39,40,41].

In this paper, an alternative solution that utilizes a two-stage converter is proposed. The block diagram of the proposed structure is shown in Figure 1. In the first stage, a Z-source converter steps up the input voltage (rectified line voltage of 350 V) to a medium voltage of 2 kV. A full-bridge inverter operating at the boundary of the continuous conduction mode is used to obtain a 100 kHz square-wave voltage waveform in the second stage, which is stepped up to 5 kV by an HVHF transformer. Finally, a voltage doubler at the secondary is used to obtain 10 kV DC. The availability of fast and high-voltage-rated SiC devices enables this solution. Previously, as a preliminary work, two Z-source DC–DC converters were used in a parallel-input, series-output configuration to generate a total of 2 kV (1 kV per converter) from 350 V at 2 kW [42]. A unique transformer design with windings composed of printed circuit board (PCB) stacks similar to the planar transformer concept was preferred for the proposed power supply due to its flexibility and ease of handling. Recent literature shows that transformers based on the planar coil concept have become increasingly popular. The issues to tackle in their design for HVDC power supplies are insulation stresses and voltage distribution. The insulation level provided by the standard PCB material FR-4 is one of the most important reasons for this interest [43]. They have also been proposed for use in solid-state transformer applications. A 15 kW planar transformer operated at 200 kHz is presented in [44]. Ref. [45] presents a transformer operating at 100 kW, 405 kHz.

The three-stage prototype converter, which was designed and built, demonstrated that the problems caused by stray capacitance reflected to the primary side of HVHF transformers, owing to high turn ratios, can be minimized. When the transformer turn ratio is kept low, the reflected capacitance is reduced, enabling pulse width modulation (PWM) regulation at a constant high switching frequency in the inverter, thereby increasing the power density. The methodology followed in this work incorporates analytical, simulation, and experimentation on the prototype, as usual. However, an extra step was taken here when it was observed that stray capacitances were causing the converter to deviate from expected operation. The device models were revised based on initial experimental results to account for these stray components, and the design was modified accordingly. This process enabled a better transformer design, a more precise controller design, and efficient and reliable operation.

Extensive simulation and experimental work were conducted, and the results were presented in the paper. Simulation and experimental results show that the proposed structure offers a viable alternative for HVDC power supplies.

The remainder of this paper is structured as follows: Section 2 describes the operation of the Z-source DC–DC converter. Section 3 explains the inverter’s operation and its control algorithm. The HVHF transformer is discussed in Section 4. The simulation results are presented in Section 5. Section 6 presents the controller and gate drive structures. The experimental results are presented in Section 7.

2. Analysis and Design of the DC–DC Converter Stage

The DC–DC converter used here is a Z-source (impedance-source) converter, first presented in [35]. Two coupled inductors and one switch make up the converter’s core. The circuit diagram is shown in Figure 2.

The primary-reflected magnetizing inductance and the input inductor of this circuit serve as energy storage devices. The coupled inductor provides galvanic isolation, whereas the diodes and capacitors on the secondary side provide an additional voltage boost. The reflected load current does not affect the input current ripple. This topology belongs to the quasi-impedance source converter (Q-ISC) structure described in [35]. In general, these converters offer lower current and voltage stresses, lower component counts, and simpler control circuits than classical ISC [46]. The voltage gain of this converter is given by

$$G={\displaystyle \frac{V_{C0}}{V_{in}}}=nk{\displaystyle \frac{(1+D)}{(1-2D)}}$$

(1)

where n is the turn ratio, and k is the coupling factor of the coupling inductor.

Equations (2)–(9) describe the voltage and current stresses of the converter:

$$V_{C1}={\displaystyle \frac{(1-D)V_{in}}{(1-2D)}}$$

(2)

$$V_{C2}={\displaystyle \frac{D{V}_{in}}{(1-2D)}}$$

(3)

$$V_{C3}=V_{C4}=nk{V}_{C2}$$

(4)

$$V_{sw}=V_{C1}+V_{C2}={\displaystyle \frac{V_{in}}{(1-2D)}}$$

(5)

$$V_{D0}=V_{D2}=V_{D3}={\displaystyle \frac{n{V}_{in}}{(1-2D)}}$$

(6)

$$V_{D1}={\displaystyle \frac{V_{in}}{(1-2D)}}$$

(7)

$$I_{in}={\displaystyle \frac{V_{C0}{I}_0}{n{V}_{in}}}$$

(8)

$$I_{Lm}={\displaystyle \frac{(2-D)}{(1+D)}}{I}_{in}$$

(9)

The duty cycle ratio is limited to 50%. Figure 3 shows the variation in voltage gain and normalized device stresses (with respect to the input source) as a function of the duty cycle, assuming k = 1 and n = 1. At high duty cycles, both the gain and the normalized device stress increase. Therefore, D = 0.3 seems to be a good choice, as the gain is 3.3 for this ratio, while the switch voltage is 2.5 times the source voltage and the diode voltage stress is 2.5n times the source voltage.

Table 1. Design parameters of the Z-source DC–DC converter.

Parameter	Value
Output voltage ($V_o$)	2 kV
Input voltage ($V_{in}$)	350 V
Output power ($P_o$)	2 kW
Switching frequency ($f_{sw}$)	50 kHz
Duty cycle ratio (D)	0.3
Coupling factor (k)	0.98
Peak-to-peak input current ripple	20%
Peak-to-peak magnetizing current ripple	90%
Peak-to-peak capacitor voltage ripple	4%
Peak-to-peak output voltage ripple	1%

lists all the design parameters of the Z-source DC–DC converter. To obtain 2 kV from a 350 V input, the turns ratio is n = 1.8. By using the parameters listed in Table 1 along with the D and n values in (2)–(9), all the voltage stresses can be calculated. The results are listed in

Table 2. Calculated circuit parameters of the Z-source DC–DC converter.

Parameter	Value
$V_{C1}$	612.5 V
$V_{C2}$	262.5 V
$V_{C3}=V_{C4}$	463 V
$V_{sw}=V_{D1}$	875 V
$V_{D0}=V_{D2}=V_{D3}$	1575 V
$I_{Lin}$	5.71 A
$I_{Lm}$	7.47 A
$I_{\mathrm{sw}-\mathrm{ave}}$	19.03 A
$I_{\mathrm{sw}-\max }$	21 A

. The inductor and capacitor values are calculated by using (10)–(15), which depend on the current ripples, on-state inductor voltages, voltage ripples, and capacitor current values.

Table 3. Calculated component values of the Z-source DC–DC converter.

Component	Value	Component	Value
$L_{in}$	1.25 mH	$C_1=C_2$	3.26 $\mathsf{\mu }$F
$L_m$	535 $\mathsf{\mu }$H	$C_3=C_4$	1.05 $\mathsf{\mu }$F
		$C_0$	676 nF

lists all the calculated values.

$$L_{in}={\displaystyle \frac{V_{Lin\text{-on}}D{T}_s}{\Delta I_{in}}}$$

(10)

$$L_m={\displaystyle \frac{V_{Lm\text{-on}}D{T}_s}{\Delta I_{Lm}}}$$

(11)

$$C_1={\displaystyle \frac{I_{C1\text{-on}}D{T}_s}{\Delta V_{C1}}}$$

(12)

$$C_2={\displaystyle \frac{I_{C2\text{-on}}D{T}_s}{\Delta V_{C2}}}$$

(13)

$$C_3=C_4={\displaystyle \frac{I_{C3,C4\text{-on}}D{T}_s}{\Delta V_{C3,C4}}}$$

(14)

$$C_0={\displaystyle \frac{I_{C0\text{-on}}D{T}_s}{\Delta V_{C0}}}$$

(15)

The Z-source DC–DC converter stage of the circuit was simulated in PLECS for the design parameters listed in Table 1. Based on the initial simulation results and design equations, the components were selected.

Table 4. Selected components and rated values of the Z-source converter.

Component	Max. Voltage	Max. Current	Selected Part	Rated Values
MOSFET	900 V	11 A RMS/21 A peak	G3R30MT12J	40 mΩ, SiC, 1200 V/60 A
Diode (D1)	900 V	7.7 A RMS/5.9 A mean	GD10MPS12A	SiC Schottky, 1200 V/10 A
Diode (D2–D5)	1600 V	1.2 A RMS/1 A mean	IDM05G120C5	SiC Schottky, 1200 V/5 A, 2 in series
Diode (D6, D7)	1600 V	2 A RMS/1 A mean	IDM05G120C5	SiC Schottky, 1200 V/5 A, 2 in series
$C_1$	270 V	4.7 A RMS	C4AQNBU4330M1YJ	Film capacitor, 3.3 $\mathsf{\mu }$F/1000 V
$C_2$	620 V	9 A RMS	C4AQNBU4330M1YJ	Film capacitor, 3.3 $\mathsf{\mu }$F/1000 V
$C_3$–$C_4$	475 V	2.4 A RMS	C4AQPBU4110M1WJ	Film capacitor, 1.1 $\mathsf{\mu }$F/1200 V
$C_o$	2000 V	1.7 A RMS	MKP1W041007K00KSSD	Film capacitor, 1 $\mathsf{\mu }$F/3000 V

lists the components selected for the Z-source converter. The circuit was simulated again, with device parasitics added, to estimate the converter’s efficiency under realistic conditions. This time, LTSPICE was chosen because it has detailed models for the chosen devices. Figure 4 shows the simulated circuit. The catalog data of the chosen semiconductors and capacitors were used in the simulation. The leakage inductance of the coupled windings was also included in the coupled inductor to provide a more realistic model.

Figure 5 shows the simulation results. Figure 5a shows the MOSFET voltage, current, and losses. The voltage waveform exhibits a very small transient spike. Figure 5b shows the output voltage, input current, and the voltage across the output diode. The diode voltage indicates no transient overshoots or ringing, and the maximum stress remains below the device ratings. All other diodes have the same voltage stress.

The LTSPICE simulation was also used to estimate the average losses in the components: 16 W for the MOSFET, 12 W for D1, and 12 W for the rectifier diodes. The copper and core losses were calculated as 3.77 W and 5 W, respectively, for the input inductor, and 7 W and 9.8 W for the coupled inductor. Therefore, the total loss in the Z-source converter is predicted as 65.57 W, yielding an efficiency of 96.82%.

3. Analysis and Design of the Isolated Full-Bridge DC/DC Converter

The second stage of the HVDC power supply circuit is shown in Figure 6. It includes a full-bridge converter operating at a constant switching frequency, an HVHF transformer, and a voltage doubler output. The derivation of the design equations and the discussion of the operating principles will initially assume an ideal converter. A more realistic model will be presented during the sizing stage once the components are selected. Owing to the converter’s topological structure, its operation occurs either at Critical Conduction Mode (CRM) or Discontinuous Conduction Mode (DCM), as shown in Figure 7. Continuous Conduction Mode (CCM) is not an option in this topology because there is no inductor in series with the output.

In Figure 7, the current ($i_{D5}$), which is the rectifier output current, represents the operation at CRM (assuming $n=1$). Although the DCM is acceptable, designing the converter at the CRM is preferred to achieve the highest efficiency. Note that operation in this mode almost eliminates reverse recovery losses in power diodes and helps reduce the size of filters for common-mode and electromagnetic immunity (EMI) [47,48]. Therefore, the primary step in the design is sizing the series inductance ($L_{\mathrm{series}}$) to ensure operation exactly at the CRM under full load. The average of the current ($i_{D5}$) equals the load current ($I_o$). Thus, (16) determines the maximum amplitude of the current flowing in the first winding of the transformer depending on the output power ($P_o$).

$$I_{1\max }=n{I}_{\max }=n\left(4I_o\right)=n\left({\displaystyle \frac{4P_o}{V_o}}\right)$$

(16)

Many designs neglect $i_m$, because it is typically negligible compared to the main current ($i_1$). However, this is not the case in this design, where high voltages result in a smaller main current and a relatively larger magnetizing current. Therefore, this aspect should be considered here. According to Figure 7, the main current $i_1$ is the difference between $i_{pri}$ and $i_m$. To account for the effect of $i_m$, its expression must first be derived. It can be observed that the voltage reflected from the output drives the magnetizing current, because all transformer leakage inductances are lumped into a series inductor on the primary side. While $D_5$ is conducting (during the positive half cycle of currents $i_2$ and $i_1$), the voltage ($v_m$) across the magnetizing inductance ($L_m$) becomes +$V_o/2n$. Similarly, when $D_6$ is conducting, $v_m$ becomes -$V_o/2n$. Consequently, the peak-to-peak magnetizing current ($\Delta I_m$) can be calculated using (17). The voltage across $L_m$ is a pure square wave with a 50% duty cycle and a magnitude of $V_o/2n$, as shown in Figure 7 (top trace: blue waveform).

$$\Delta I_m={\displaystyle \frac{{\displaystyle \frac{V_o}{2n}}}{2L_m{f}_{sw}}}$$

(17)

It is clear from Figure 7 that the slope of the primary current (bottom trace: red waveform) can be significantly modified based on the value of the magnetizing current. Moreover, the charging ($T_Q$) and resetting ($T_D$) stage times can be determined from the volt-second balance across $L_{\mathrm{series}}$, as given in (18) and (19).

$$\left(V_{in}-{\displaystyle \frac{V_o}{2n}}\right)T_Q=\left(V_{in}+{\displaystyle \frac{V_o}{2n}}\right)T_D$$

(18)

$$T_Q+T_D={\displaystyle \frac{T_S}{2}}$$

(19)

To derive the formula to calculate $L_{\mathrm{series}}$, a KCL equation can be written for the currents during the positive half cycle of the primary current, as in (20)–(22).

$$i_{\mathrm{pri}}=i_m+i_1$$

(20)

$$\Delta i_{\mathrm{pri}}=\Delta i_m+\Delta i_1$$

(21)

$${\displaystyle \frac{\left(V_{in}-{\displaystyle \frac{V_o}{2n}}\right)T_Q}{L_{\mathrm{series}}{f}_s}}={\displaystyle \frac{\left({\displaystyle \frac{V_o}{2n}}\right)T_Q}{L_m{f}_s}}+n{I}_{\max }$$

(22)

Therefore, based on the specified n, $V_{in}$, $V_o$, and $P_o$, all the unknown parameters defined in (16)–(22) can be calculated. It is worth noting that the series inductor can be incorporated into the transformer as the primary reflected leakage inductance. In this design, we use the transformer’s leakage inductance as the series inductor to achieve our low-cost, high-power-density converter objectives.

Moreover, having a large series inductor in combination with the magnetizing inductor facilitates zero-voltage switching (ZVS) at every turn-on and eliminates $C_{oss}$—related losses. On the other hand, the turn-off occurs under hard switching.

Finally, the turn ratio can be selected based on the expected converter efficiency given in (23).

$$n\ge {\displaystyle \frac{V_o/2}{\eta V_{in}}}$$

(23)

Using 0.9 for $\eta$, 2 kV for $V_{in}$, 10 kV for $V_o$, the minimum turn ratio n was found to be 2.78. For convenience, n was selected as 2.8125 (180/64). In addition, using 2 kW for $P_o$, 10 kV for $V_o$, and 2.8125 for n in Equation (16), the peak current reflected to the first winding ($n{I}_{\max }$) was found as 2.25 A. For small-sized magnetic components, the switching frequency was selected as 100 kHz and the peak-to-peak magnetizing current ripple as 0.4 A, which corresponds to approximately 18% of 2.25 A. Using these values in (17), $L_m$ was calculated as 22.22 mH. The simultaneous solution of (18) and (19) yields $T_Q/T_S$ a ratio of 0.47. Finally, using (22), $L_{\mathrm{series}}$ was found as 400 $\mathsf{\mu }$H. In theory, this value guarantees operation at CRM at full load.

Having determined the transformer parameters, the output capacitor can be sized. The following finds the capacitor value for a certain ripple voltage in a single section of the output.

$$C_{o1}=C_{o2}={\displaystyle \frac{\Delta Q}{\Delta V_{o1}}}={\displaystyle \frac{{(I_{\max }-I_o)}^2}{4(\Delta V_{o1})I_{\max }{f}_s}}$$

(24)

The natural 180° phase shift between the voltage doubler sections facilitates interleaving operation and reduces the ripple across the entire load by half. Therefore, the ripple specification for a single output can be taken as twice the final one. The ripple was set to 0.25% for this design, corresponding to 25 V peak-to-peak across the load and 50 V per section. Therefore, using 0.2 A for $I_o$, 0.8 for $I_{\max }$, and 50 V for ($\Delta V_{o1}$) in (24), $C_{o1}$ is found as 22.5 nF. 22 nF was selected as a standard value.

4. Transformer Design

The transformer is the largest, heaviest, and most expensive component of the converter. To address these challenges, a switching frequency of 100 kHz was selected. Therefore, the input to the transformer is 100 kHz AC with a magnitude of 2 kV. The output voltage will be 5 kV ac. The power is 2 kW with a minimum efficiency requirement of 98.5%. The series inductance of 400 $\mathsf{\mu }$H will be part of the transformer as the primary leakage inductance. The desired magnetizing inductance is 22.22 mH. The following paragraphs describe the transformer design based on these specifications.

To minimize core losses and provide sufficient space for the windings to facilitate high-level insulation, a U100/57/25 part-numbered ferrite core using the 3C94 material from Ferroxcube was selected. Two U pieces are placed face-to-face to create enough window height for the windings. From the core datasheet, the measured $A_L$ value for a combination of two U cores is 5500 nH. Equation (25) yields the number of primary turns based on this $A_L$ value and the desired magnetizing inductance:

$$N_p=\sqrt{{\displaystyle \frac{L_m}{A_L}}}$$

(25)

The value is calculated as $N_p=63.56$ and rounded to 64. Accordingly, the secondary number of turns becomes 180. Again, from the datasheet, this core has a 645 ${\mathrm{mm}}^2$ cross-section area and a 199,000 ${\mathrm{mm}}^3$ volume. As two of these cores are used as a set, the total volume is 398,000 ${\mathrm{mm}}^3$. The maximum flux density in the core is calculated from (26) for operation at 100 kHz with 0.5 duty cycle as $D_{\max }$, 64 for $N_p$, and 645 mm² for $A_{\mathrm{core}}$ as 121 mT.

$$B_{\max }={\displaystyle \frac{V_{in}{D}_{\max }}{2f_s{N}_p{A}_{\mathrm{core}}}}$$

(26)

This value is below the 300 mT saturation level and is ideal for a low-loss transformer design. From the loss curve of the 3C94 ferrite material, the core loss at this flux density and 100 kHz operation is found to be approximately 60.3 kW/${\mathrm{m}}^3$. When the core loss density is multiplied by volume, the total core loss is calculated to be 24 W.

To facilitate the easy, flexible manufacturing of a core with the specified leakage inductance, the transformer windings were designed using the planar transformer concept. Both the primary and secondary windings have been implemented using PCB stacks. A picture of the transformer is shown in Figure 8. The maximum skin depth at 100 kHz operation is 200 $\mathsf{\mu }$m. With the PCB concept, it is possible to go well below this limit and minimize skin and proximity-effect-related losses. The primary trace width is 4 mm with 1 oz copper, and the secondary trace width is 1.5 mm with 1 oz copper. The effective resistance of the windings was measured using Bode100 from Omicron Lab, including the DC and AC resistances, lumped to the primary side as 6 Ω. The primary RMS current is 1.353 A. Hence, the total winding losses (primary and secondary) are calculated to be 10.98 W. Thus, the total transformer losses become 34.98 W, which makes the transformer’s predicted overall efficiency 98.28%. The design is also in good shape with respect to insulation requirements, as there are large distances between the windings and PCB layers for high-level insulation.

5. Simulation Results

The components have been determined based on the device stresses observed in the initial simulations.

Table 5. Selected components and ratings of the full-bridge converter.

Component	Max. Voltage	Max. Current	Selected Part	Part Ratings
Full-bridge MOSFET	2 kV	2.4 A (peak)/ 0.95 A (RMS)	G2R1000MT33J	SiC MOSFET, $R_{\mathrm{DS}\left(\mathrm{on}\right)}=1.5\Omega$ at 100 °C, 3300 V/5 A, $t_r=45$ ns, $t_f=20$ ns, $L_{\mathrm{sig}}=150$ nH
Gate Driver	5700 V	3 A	Infineon 1ED3431MC12M	SiC MOSFET driver with DESAT protection
Voltage doubler diode	10 kV	0.33 A (RMS)/ 0.2 A (mean)	GD05MPS17H	SiC Schottky MPS™, 7 diodes in series, $C_{\mathrm{total}}=20$ pF, $V_F=0.9$ V @ 0.2 A, total $V_F=6.3$ V, $\mathrm{d}{i}_{rr}/\mathrm{d}t=11\times {10}^8$ A/s, $t_{rr}=19$ ns, $I_{rrm}=2$ A, $Q_{rr}=40$ nC, $L_{rr}=1$ nH
Voltage doubler capacitor	5 kV	0.26 A (RMS)	FKP1Y022207E00KSSD	Film capacitor, 22 nF/6 kV

presents the components selected for the converter. Later, the PLECS model shown in Figure 9 was constructed to verify the design. It includes all major parasitics: the lossy components of the selected SiC MOSFET and the diodes, except the capacitive components. The transformer was modeled as a mutual inductance, which is available in the PLECS library. We have observed that a design in CRM is very sensitive to parameter variations; the output voltage is significantly affected by the parasitic components. A typical solution is to adjust the switching frequency to modify the converter gain, as in frequency-modulated resonant converters. Alternatively, if constant-frequency operation is preferred, parameter or input-voltage adjustments can be made. Because constant-frequency operation was preferred, the parameters were adjusted until the power stage design was finalized. In the final stage, the Z-source will regulate the full bridge (FB) converter’s input voltage based on the feedback from the FB output, ensuring overall system regulation during parameter variations and load transients. In summary, $L_{\mathrm{series}}$ is reduced to 398 $\mathsf{\mu }$H to account for the resistive losses and associated voltage drops.

Figure 10 shows the primary voltage, the voltage across $L_m$ and $L_{\mathrm{series}}$, and the primary side currents of the transformer. The waveforms closely match the analytical results in both shape and magnitude. Figure 11 illustrates the output voltage and its ripple, with the ripple amplitude remaining below 25 V, as specified. These simulation results are consistent with the analytical study, confirming the design’s accuracy.

After a successful simulation, a prototype converter was built to test the design. The initial tests revealed a significant difference between experimental and simulation results. During the open-loop test, the output voltage reached 12 kV, well above the targeted voltage of 10 kV. We also observed rapid MOSFET heating and high-power dissipation. In summary, the experimental results deviated from both the simulation and the analytical predictions because the converter was not operating in CRM as originally assumed. Upon closer inspection, the parasitic capacitance was found to affect the converter’s gain, causing a significant shift from CRM to DCM. As a quick solution, the simulation model was updated to incorporate parasitic capacitance. We determined the parasitics using the Bode100 from Omicron Lab. Figure 12 shows the updated and optimized model, which also includes two key design modifications: a reduced turn ratio and increased leakage inductance. The justifications for these changes are detailed in the following paragraphs.

The top trace in Figure 13 shows the voltage across diode D5, the middle trace shows the current through D5 and its junction capacitance, along with the current through the junction capacitance of D6, and finally, the bottom trace shows the transformer’s secondary current. As shown in Figure 13, the waveforms are heavily influenced by the capacitive currents. Each time a diode switches on or off, a significant dv/dt event occurs, injecting current through the junction capacitors of both diodes, as shown by the red and blue waveforms in the middle trace of Figure 13. These capacitive currents behave like common-mode currents, returning from the capacitor midpoint back to the transformer. When a diode turns on, the combined current originating from the two capacitors commutates into the diode, similar to the discharge of a MOSFET’s $C_{oss}$ during a turn-on. As a result, instead of starting from zero, the current value now begins at a much higher value. The transformer’s secondary-side parasitic capacitance creates the same effect as the diode junction capacitors. These combined effects cause the output voltage to rise. On the positive side, junction capacitors help reduce ${\displaystyle \frac{dv}{dt}}$, thereby lowering EMI noise.

Figure 14 shows the primary-side current, further highlighting how the waveform is altered. Spikes at the start of each current pulse are due to the primary-side parasitic capacitance of the transformer. In summary, the simulation provided crucial insights into the impact of parasitic capacitance and guided us to update the design.

The most effective solution to mitigate unwanted current injections is to use diodes with lower junction capacitance and to design a transformer with the lowest possible parasitic capacitance. The selected diodes are already the best available at this voltage level. The planar winding design was also crucial in achieving the practically attainable optimum levels of both the leakage inductance and parasitic capacitance. Each primary PCB stack consists of two layers with a total of eight turns: four on the top layer and four on the bottom. Similarly, each secondary PCB stack has two layers with 20 turns: 10 on the top layer and 10 on the bottom. Hence, while connecting 8 primary stacks in series makes 64 primary turns, nine secondary stacks in series yield 180 secondary turns. This modular design enabled large air gaps between PCB stacks, as shown in Figure 8, thereby significantly reducing intra-winding capacitance.

After selecting the optimal diodes and designing a transformer with the lowest practical parasitic, the final step in the design update was to adjust the turn ratio and leakage inductance. The turn ratio was reduced from 2.8125 to 2.5, and the spacing between the windings was increased to increase the series inductance from 398 $\mathsf{\mu }$H to 1228.9 $\mathsf{\mu }$H. In the first design (398 $\mathsf{\mu }$H), the primary and secondary PCB stacks were on the same core leg with a specific arrangement. But now, the primary stack was kept at the left leg, and the secondary stack was moved to the right leg, as shown in Figure 8. This new arrangement also significantly reduced the interwinding capacitance as a side benefit.

With these changes, the primary and secondary intra-winding capacitances were measured at 12 pF and 11.8 pF, respectively, while the interwinding capacitance was only 1 pF. These values represent the lowest capacitance levels achievable in practice, making the transformer design highly effective. The dominant capacitive effects in this design stem primarily from the secondary diodes. With all these changes, operation at CRM under full load was achieved. Section 7 will detail the experimental verification of these design improvements.

6. Controller and Isolated Gate Drive Design

To avoid regulation issues caused by parasitic components and to achieve a robust system, the FB converter was operated at a constant switching frequency (100 kHz) and a constant duty cycle ratio (50%), without output regulation. Full-load efficiency was ensured through CRM operation. Accordingly, control of the overall output voltage (Z-source + FB) was achieved via the Z-source converter’s switching signal. The cascaded control architecture adopted for this purpose is shown in Figure 15. In this scheme, the input current of the Z-source converter and the isolated full-bridge converter’s output voltage are measured independently. The output voltage is compared with the reference to generate an error signal, which is processed by a Type-II voltage mode compensator in the outer loop to produce the input current reference. The inner loop is implemented using peak-current mode control.

Current feedback was obtained using an isolated LTSR 25-NP current transducer (75 mV/A). The signal was scaled with an OPA350UA op-amp and fed to the MCU ADC. The voltage feedback was derived from a divider (70 $\mathrm{M}\Omega$, 10 kV, 1% MOX1125237005F1 resistor and a 30 $\mathrm{k}\Omega$ resistor) and isolated through an AMC1350 amplifier (gain = 0.4), powered by a 12 V/3.3 V, 1-W isolated DC–DC converter R1S-123.3/H-R. The amplifier output was scaled again using the same op-amp. The control system was implemented on an STM32G474RE Nucleo board.

Cycle-by-cycle current protection was implemented based on the input current. Additionally, the gate driver IC automatically halts switching upon detecting an over-current situation via a rising Drain-Source voltage, providing dual-level current protection. Because a boost-type Z-source converter can experience an abrupt rise in output voltage when a load is suddenly lost, the output voltage is continuously monitored, and the circuit is shut down if it exceeds 115% of the nominal value.

The Texas Instruments UCC21750 gate driver IC was selected to convert the microcontroller’s logic-level drive signals to the voltage levels required to switch SiC MOSFETs. A key advantage of this IC is its galvanic isolation between the input and output which protects the control circuitry from faults in the power stage. The recommended gate-to-source drive voltages are +15/−5 V for the SiC MOSFET devices of the Z-source converter, and +20/−5 V for the devices of the inverter. Furthermore, the integrated active Miller clamp suppresses the gate voltage rise during turn-off because of Miller capacitance charging, preventing false switching. In addition, the DESAT pin monitors the VGS, and switching is automatically stopped if the current exceeds the defined threshold, generating a fault signal to the controller. Additionally, using UCC21750’s integrated isolated analog sensing capability, the full-bridge DC-link voltage is continuously monitored, and the circuit is automatically shut down if the DC-link voltage exceeds 2100 V.

7. Experimental Verification

The experimental prototype, shown in Figure 16, was built to test the concept at the rated power and voltage. The first picture shows the Z-source stage, the second shows the FB stage, and the third shows the complete setup.

Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27 and Figure 28 show the experimental results under various conditions. Figure 17 shows the output voltage (blue) and current (pink) of the Z-source converter. As expected, the output is regulated at 2 kV. The current waveform is also as expected from the coupled inductor structure. The Z-source output voltage is applied to the FB converter, which inverts it at high frequency.

Figure 18 shows the drain-source voltage of one of the low-side MOSFETs. The waveform is clean, with a maximum voltage of 2 kV and no signs of ringing or overshooting. The slow rise and fall of the drain-source voltage confirms ZVS operation.

Figure 19 displays the primary current of the HVHF transformer, where the capacitive current spikes are visible but smaller than those predicted in the simulation given in Figure 14. Figure 20 shows the HVHF transformer primary voltage, indicating the CRM operation and a voltage level clamped at 2 kV as expected.

Figure 21 shows the HVHF transformer secondary current with waveform and values closely matching the simulation results shown in Figure 13. The value and the shape of the current are exact replicas of the simulation results. Figure 22 illustrates the HVHF transformer secondary voltage, which swings between −5 kV and +5 kV, with a low slew rate owing to parasitic capacitances.

Figure 23 highlights the output voltage ripple, confirming that the peak-to-peak ripple stays below 25 V, as designed. Figure 24 shows the variation in the system efficiency over a 50–100% load change. The red curve belongs to the stage that includes the FB converter, HVHF transformer, and voltage doubler. The blue one shows the Z-source converter’s efficiency. The orange one is the total efficiency curve from one end to the other. Owing to the CRM operation and ZVS, the FB efficiency was measured as 98.31% at the rated load. The Z-source converter had an efficiency of 96.32% at the same point, yielding a combined efficiency of 94.69%. This efficiency is quite acceptable for a high-voltage power supply operating at such a high frequency.

Figure 25 and Figure 26 show the load transient responses when the load was changed from 50% to 100% and back to 50%, respectively. The system exhibited a stable response, with no resonance peaks, approximately 14% undershoot when the load was applied, and 10% overshoot when the load was removed.

Similarly, Figure 27 and Figure 28 illustrate the line transient response for an input voltage change from 350 V to 300 V and back to 350 V, with a 10 V/ms slew rate. The system exhibited excellent stability and regulation under transient conditions and disturbances.

A summary of the design process development steps, including the before-and-after model corrections, is presented in

Table 6. Development steps and performance comparison.

Development Steps	Step 1 Simulation	Step 2 Experiment	Step 3 Simulation	Step 4 Experiment
Effective Duty	50%	37%	50%	50%
Series inductor, $L_{\mathrm{series}}$	398 $\mathsf{\mu }$H	398 $\mathsf{\mu }$H	1228.9 $\mathsf{\mu }$H	1228.9 $\mathsf{\mu }$H
Turns ratio, n	2.8125	2.8125	2.5	2.5
Operation mode	CRM	DCM	CRM	CRM
Switching of SiC MOSFETs	ZVS	HARD	ZVS	ZVS
Efficiency, $\eta$	98.41%	97.54%	98.15%	98.31%
MOSFET Power Dissipation	6.80 W	–	4.00 W	–
Diode Power Dissipation	2.56 W	–	11.74 W	–
Transformer Power Dissipation	22.88 W	–	22.00 W	–
Total Power Dissipation	32.24 W	50.38 W	37.74 W	34.38 W

. For each step, the output voltage and power were kept constant at 10 kV and 2 kW, respectively. Step 1 indicates the initial simulation, during which no stray capacitors were identified. The dissipative elements of the model were constructed based on component datasheet values and Bode100 measurements, such as the transformer’s ac resistance. When this design was tested in Step 2, the operating mode changed from soft switching to hard switching. The closed-loop controller regulated the phase shift to keep the effective primary voltage duty around 37% indicating DCM operation. The measured power dissipation was 18.14 W higher than what the simulation yielded. In Step 3, the same model was improved only by adding the stay capacitors, as shown in Figure 9 and Figure 12. Based on the simulation in Step 3, the transformer was redesigned to minimize the effect of stray capacitors on the operating mode. Note that power dissipation in MOSFETs in Step 3 was reduced. This is due to the reduced peak of the current at turn-off, an additional benefit of the large series inductance. However, diode dissipation increased due to the junction capacitors. Finally, the experiment in Step 4 demonstrated that the final design achieved ZVS with 15 W less dissipation than in the previous experiment in Step 2, thereby successfully concluding the design process for the full-bridge stage.

8. Conclusions

HVDC power supplies typically use hard-switched inverters and high-step-up transformers to achieve high DC voltages. However, the stray capacitance reflected from the high-voltage side has a significant detrimental effect on the primary side owing to the transformer’s high turn ratio. A novel high-voltage DC power supply architecture was proposed in this paper to address this challenge. The proposed structure employs a Z-source DC–DC converter to step up the input voltage to 2 kV, and an inverter operating at high frequency. SiC devices meet high-voltage and high-frequency requirements. Because switching occurs at a high voltage, the transformer does not require a high turn ratio, and the reflected capacitance becomes reasonably small. This approach enables constant-frequency PWM regulation with descent efficiency, contributing to improved performance, compactness, and manufacturability.

This paper also shows that, especially in high-voltage, high-frequency applications, stray components are critical and may lead to deviations from the operation predicted by analytical equations and simulation results. The paper uses and proposes an iterative methodology, which can be summarized as “initial analytical design, parasitic-aware simulation, prototype testing, discrepancy identification, parameter extraction, model calibration, redesign, and retesting”. This method provides a more efficient and reliable operation.

Simulation and experimental results validate the effectiveness of the proposed design, demonstrating its potential for high-voltage applications in demanding fields such as aerospace, medical imaging, and advanced manufacturing. Future work may further optimize the transformer structure and control strategies to enhance scalability and robustness.