Overlap Time Compensation and Characteristic Analysis for Current Source Photovoltaic Grid-Connected Inverter

: In the current source photovoltaic grid-connected system, to prevent the DC-link inductor from incurring an opening circuit fault, it is necessary to include the overlap time in the switching signals. However, current error and serious harmonic distortion in the inverter-side and grid-side currents are generated, which will cause additional losses and reduce the power quality of the grid, so it is important to compensate for the current error caused by the overlap time. In this paper, the relationship between the nonlinear current errors caused by the overlap time and the AC-side voltage is analyzed. Then, the mathematical expression of the low-order harmonics with losses caused by the overlap time is derived. On this basis, a current error compensation method with a discrete filter of AC-side voltage is proposed. Finally, a simulation and experiment are carried out to verify the correctness and effectiveness of the theoretical analysis and compensation scheme presented in this paper. With an overlap time of 3 µ s, the THD of the grid-side current decreases from 5.93% to 1.59% after compensation.


Introduction
Solar energy is widely used in the sustainable and environment-friendly power generation field [1].Due to the simple structure and mature control technology, a voltage source inverter (VSI) is commonly adopted in the photovoltaic (PV) grid-connected system [2].However, the VSI is a buck inverter, which requires the DC input voltage to be higher than the peak of the AC output voltage [3].Therefore, on cloudy or rainy days, the output voltage of the PV cells reduces, the operation of the system stops, and the utilization rate decreases [4].To address the problem that the input voltage is insufficient, the boost converter or the transformer needs to be added [5,6].
Compared with the VSI, the current source inverter (CSI) is a boost inverter [7,8], so only a single-stage CSI can realize the whole process of light utilization from weak to strong [9,10].The DC-link inductor of CSI is series connected with the PV cells, so the input current is continuous and controllable, which is convenient in realizing maximum power point tracking (MPPT) [11,12].The CSI is capable of overcurrent protection, so the reliability is higher than that of the VSI [10,13].Meanwhile, the operation time of the CSI is longer than that of the VSI [14,15].Based on the above advantages, CSI is more suitable for the PV grid-connected system [16].
To prevent the short circuit fault, the dead time needs to be added during the modulation process in the VSI [17,18].Since the dead-time causes the distortion of the inverter output voltage and the gird-side current [19], many compensation schemes for VSI have been proposed to suppress the deadtime effect, such as pulse duration compensation [20], average voltage compensation [21], and adaptive harmonic compensation [22].Different from VSI, the shoot-through is a normal switching state of the CSI, but the open circuit

SVM Scheme of CSI
The current vectors with corresponding switching states are shown in Figure 2. The space is divided into six sectors (I-VI) by the active vectors Ik (k = 1, 2,…, 6).In addition, there are three null vectors: I7, I8, and I9.
Under the common seven-segment sequence SVM based on the triangular carrier wave, the inverter-side current is symmetrical, and the content of the low-order harmonic is less than that under other SVM schemes.If the target vector Iref is located in sector I, Iref is synthesized by the adjacent active vectors (I1 and I6) and null vector I7.When Iref is located in sector I, the switching signals diagrams are shown in Figure 3a, where ma, mb, and mc are the compared values of the triple commutation time, and p1-p6 represent the switching signals of S1-S6, respectively.'0′ represents off-state, and '1′ represents on-state.At this time, all switching signals of the upper bridge arm (p1, p3, and p5) remain '0′ or '1′ in a carrier period; commutation occurs among the switching tubes of the lower bridge arm (p2, p4 and p6), and the total number of commutation times is six.t1-t6 represent the commutation comments.When Iref is located in sector II, the switching signals diagrams are shown in Figure 3b, and the commutation occurs among the switching tubes of the upper bridge.The solid lines represent the actual signal waveform, and different color dashed lines are used to point out the commutation comments.

SVM Scheme of CSI
The current vectors with corresponding switching states are shown in Figure 2. The space is divided into six sectors (I-VI) by the active vectors I k (k = 1, 2, . .., 6).In addition, there are three null vectors: I 7 , I 8 , and I 9 .

SVM Scheme of CSI
The current vectors with corresponding switching states are shown in Figure 2. The space is divided into six sectors (I-VI) by the active vectors Ik (k = 1, 2,…, 6).In addition, there are three null vectors: I7, I8, and I9.
Under the common seven-segment sequence SVM based on the triangular carrier wave, the inverter-side current is symmetrical, and the content of the low-order harmonic is less than that under other SVM schemes.If the target vector Iref is located in sector I, Iref is synthesized by the adjacent active vectors (I1 and I6) and null vector I7.

Overlap time Generation Mechanism
In Figure 3, the moment of turn-on is consistent with that of turn-off.However, the delay phenomenon exists in the turn-on and turn-off process of the switching tube; if the delay process of turn-off is longer than that of turn-on, a brief open circuit state will appear in the inverter bridge, which will lead to a high dv/dt in the DC-link inductor.Therefore, turn-off delay should be introduced into all switching signals, at this time, the switching signals in the action of Sector I are shown in Figure 4.It can be seen that there are two switching signals in the on-state during tov; this is named the overlap time.

Analysis of Overlap time Effect
In this section, the commutation characteristics during the overlap time are analyzed first; then, the inverter-side current error caused by the overlap time is analyzed.

Commutation Characteristics during the Overlap time
Figure 5a shows the equivalent circuit during the overlap time in the commutation process from the null vector I7 to the active vector I1.At this time, both S4 and S6 are turned on simultaneously, but the flow path of idc depends on the relation of ua and ub.
If ua > ub, D4 remains in the conduction state, and D6 withstands the reverse voltage; the generated current vector remains I7, which leads to the nonlinear error on ia and ib.

Overlap Time Generation Mechanism
In Figure 3, the moment of turn-on is consistent with that of turn-off.However, the delay phenomenon exists in the turn-on and turn-off process of the switching tube; if the delay process of turn-off is longer than that of turn-on, a brief open circuit state will appear in the inverter bridge, which will lead to a high dv/dt in the DC-link inductor.Therefore, turn-off delay should be introduced into all switching signals, at this time, the switching signals in the action of Sector I are shown in Figure 4.It can be seen that there are two switching signals in the on-state during t ov ; this is named the overlap time.

Overlap time Generation Mechanism
In Figure 3, the moment of turn-on is consistent with that of turn-off.However, the delay phenomenon exists in the turn-on and turn-off process of the switching tube; if the delay process of turn-off is longer than that of turn-on, a brief open circuit state will appear in the inverter bridge, which will lead to a high dv/dt in the DC-link inductor.Therefore, turn-off delay should be introduced into all switching signals, at this time, the switching signals in the action of Sector I are shown in Figure 4.It can be seen that there are two switching signals in the on-state during tov; this is named the overlap time.

Analysis of Overlap time Effect
In this section, the commutation characteristics during the overlap time are analyzed first; then, the inverter-side current error caused by the overlap time is analyzed.

Commutation Characteristics during the Overlap time
Figure 5a shows the equivalent circuit during the overlap time in the commutation process from the null vector I7 to the active vector I1.At this time, both S4 and S6 are turned on simultaneously, but the flow path of idc depends on the relation of ua and ub.
If ua > ub, D4 remains in the conduction state, and D6 withstands the reverse voltage; the generated current vector remains I7, which leads to the nonlinear error on ia and ib.

Analysis of Overlap Time Effect
In this section, the commutation characteristics during the overlap time are analyzed first; then, the inverter-side current error caused by the overlap time is analyzed.

Commutation Characteristics during the Overlap Time
Figure 5a shows the equivalent circuit during the overlap time in the commutation process from the null vector I 7 to the active vector I 1 .At this time, both S 4 and S 6 are turned on simultaneously, but the flow path of i dc depends on the relation of u a and u b .
If ua > ub, the forward voltage of D3 is higher than D1, so D3 remains in the conduction state, and D1 withstands the reverse voltage; the generated current vector remains I8, which leads to the nonlinear error on ia and ib.
If ua < ub, D3 withstands the reverse voltage, D1 changes to the conduction state, idc is switched from S3 and D3 to S1 and D1, and the generated current vector changes from I8 to I6; no nonlinear error will occur.The commutation characteristics during the overlap time can be summarized as follows: 1.When the target current vector is located in Sector I, III, or V, the commutation occurs among the lower bridge arms (S4, S6, and S2).DC-link current only flows through the switching tube and diode whose phase voltage is higher, so the nonlinear current will not be generated if the sequence of commutation is from high voltage to low voltage; 2. When the target current vector is located in Sector II, IV, or VI, the commutation occurs among the upper bridge arms (S1, S3, and S5).DC-link current only flows through the switching tube and diode whose phase voltage is lower, so the nonlinear current will not be generated if the sequence of commutation is from low voltage to high voltage.

Current Error Caused by the Overlap time in a Carrier Period
According to the analysis of the commutation characteristics during the overlap time, combined in Figures 3 and 4, under all relationships of the AC voltage, the diagrams of the current error caused by the overlap time in sector I during a whole carrier period are shown in Figure 6.It can be seen that there are three stages in which the overlap time generates current error in a carrier period, and the average three-phase inverter-side current error can be expressed as If u a > u b , D 4 remains in the conduction state, and D 6 withstands the reverse voltage; the generated current vector remains I 7 , which leads to the nonlinear error on i a and i b .
If u a < u b , D 4 withstands the reverse voltage, D 6 changes to the conduction state, i dc is switched from S 4 and D 4 to S 6 and D 6 , and the generated current vector changes from I 7 to I 1 ; commutation can be achieved, and no nonlinear error is generated.
Figure 5b shows the equivalent circuit during the overlap time in the commutation process from the null vector I 8 to the active vector I 6 .At this time, both S 1 and S 3 are turned on simultaneously, but the flow path of i dc also depends on the relation of u a and u b .
If u a > u b , the forward voltage of D 3 is higher than D 1 , so D 3 remains in the conduction state, and D 1 withstands the reverse voltage; the generated current vector remains I 8 , which leads to the nonlinear error on i a and i b .
If u a < u b , D 3 withstands the reverse voltage, D 1 changes to the conduction state, i dc is switched from S 3 and D 3 to S 1 and D 1 , and the generated current vector changes from I 8 to I 6 ; no nonlinear error will occur.
The commutation characteristics during the overlap time can be summarized as follows: 1.When the target current vector is located in Sector I, III, or V, the commutation occurs among the lower bridge arms (S 4 , S 6 , and S 2 ).DC-link current only flows through the switching tube and diode whose phase voltage is higher, so the nonlinear current will not be generated if the sequence of commutation is from high voltage to low voltage; 2.
When the target current vector is located in Sector II, IV, or VI, the commutation occurs among the upper bridge arms (S 1 , S 3 , and S 5 ).DC-link current only flows through the switching tube and diode whose phase voltage is lower, so the nonlinear current will not be generated if the sequence of commutation is from low voltage to high voltage.

Current Error Caused by the Overlap Time in a Carrier Period
According to the analysis of the commutation characteristics during the overlap time, combined in Figures 3 and 4, under all relationships of the AC voltage, the diagrams of the current error caused by the overlap time in sector I during a whole carrier period are shown in Figure 6.It can be seen that there are three stages in which the overlap time generates current error in a carrier period, and the average three-phase inverter-side current error can be expressed as where f s is the carrier frequency, ∆i a , ∆i b , and ∆i c represent the three-phase inverter-side current error, respectively, and x, y, and z belong to {a, b, c}.
Energies 2024, 17, x FOR PEER REVIEW 6 of 19 where fs is the carrier frequency, ∆ia, ∆ib, and ∆ic represent the three-phase inverter-side current error, respectively, and x, y, and z belong to {a, b, c}.
When Iref is located in sector II, under all relationships with the AC-side voltage, the diagrams of the current error caused by the overlap time in sector I during a whole carrier period are shown in Figure 7, where the red lines are used to indicate the moment of current error.It can be seen that the average three-phase current error can also be expressed by Formula (1), so the average current error caused by the overlap time in a whole carrier period is only related to the AC-side voltage and is independent of the sector where Iref locates.The average current error under all relationships of the AC-side voltages can be summarized in Table 1.
When I ref is located in sector II, under all relationships with the AC-side voltage, the diagrams of the current error caused by the overlap time in sector I during a whole carrier period are shown in Figure 7, where the red lines are used to indicate the moment of current error.It can be seen that the average three-phase current error can also be expressed by Formula (1), so the average current error caused by the overlap time in a whole carrier period is only related to the AC-side voltage and is independent of the sector where I ref locates.The average current error under all relationships of the AC-side voltages can be summarized in Table 1.Table 1.Average current error caused by the overlap time.

Harmonic Characteristics for Overlap time
According to Table 1, the waveform of ∆ia is shown in Figure 8, the initial phase of ua is considered zero, and ∆ia can be expressed as (2) Table 1.Average current error caused by the overlap time.

Harmonic Characteristics for Overlap Time
According to Table 1, the waveform of ∆i a is shown in Figure 8, the initial phase of u a is considered zero, and ∆i a can be expressed as Energies 2024, 17, 1768 8 of 18 shows that the overlap time introduces the 6k ± 1-order harmonics to the inverter-side current of CSI, and the amplitude of the harmonic is proportional to tov and idc.

Parameters Design for L, C, and R
Next, the harmonics of the grid-side current caused by the overlap time will be discussed.According to Figure 1 and reference [29], the transfer function Gi2ig(s) from ia to iag can be derived as The parameters of L, C, and R are determined by the Bode plots under different values.First, L and C remain unchanged.The Bode plots under different values of R are shown Figure 9a.The resonance peak decreases with the increase in R, but the efficiency of the system will decrease, so the value of R should be moderate.Meanwhile, the gain in the high-frequency range is independent of the value of R.
Then, L and R remain unchanged.The Bode plots under different values of C are shown Figure 9b.As the value of C increases, the high-frequency range gain increases, but the bandwidth of Gi2ig(s) decreases.
Since there are abundant high-order harmonics in the inverter-side current near the switching frequency, to achieve good filtering performance, this paper stipulates that the gain of Gi2ig(s) is less than 60 dB at the switching frequency of 10 kHz, so the values of L and C should be satisfied as Based on the above analysis, the parameters of L, C, and R are set as 4 mH, 66 μF, and 0.5 Ω, respectively.Substituting these parameters into Equation (4), the Bode plot of Gi2ig(s) is shown in Figure 9c.To improve efficiency, the value of R is small, resulting in Gi2ig(s) being an under-damped system.This is the symmetry of half wave and quarter wave, so ∆i a only contains the odd-order harmonics, Equation ( 2) is decomposed into Fourier series, and the harmonic expression of ∆i a can be obtained as Equation (3) shows that the overlap time introduces the 6k ± 1-order harmonics to the inverter-side current of CSI, and the amplitude of the harmonic is proportional to t ov and i dc .

Parameters Design for L, C, and R
Next, the harmonics of the grid-side current caused by the overlap time will be discussed.According to Figure 1 and reference [29], the transfer function G i2ig (s) from i a to i ag can be derived as The parameters of L, C, and R are determined by the Bode plots under different values.First, L and C remain unchanged.The Bode plots under different values of R are shown Figure 9a.The resonance peak decreases with the increase in R, but the efficiency of the system will decrease, so the value of R should be moderate.Meanwhile, the gain in the high-frequency range is independent of the value of R.
Then, L and R remain unchanged.The Bode plots under different values of C are shown Figure 9b.As the value of C increases, the high-frequency range gain increases, but the bandwidth of G i2ig (s) decreases.
Since there are abundant high-order harmonics in the inverter-side current near the switching frequency, to achieve good filtering performance, this paper stipulates that the gain of G i2ig (s) is less than 60 dB at the switching frequency of 10 kHz, so the values of L and C should be satisfied as 4π 2 LC > 10 −5 . ( Based on the above analysis, the parameters of L, C, and R are set as 4 mH, 66 µF, and 0.5 Ω, respectively.Substituting these parameters into Equation (4), the Bode plot of G i2ig (s) is shown in Figure 9c.To improve efficiency, the value of R is small, resulting in G i2ig (s) being an under-damped system.
There is a resonance peak in the magnitude-frequency characteristic curve of G i2ig (s), and G i2ig (s) will amplify the harmonics whose frequency belongs to the range [70 Hz, 400 Hz] in the inverter-side current.According to the expression of the harmonic caused by the overlap time, the frequencies of the fifth and seventh harmonics are 250 Hz and 350 Hz, and belong to the resonance region, which shows that the overlap time will introduce fifth and seventh harmonic distortion to the gird-side current of CSI.There is a resonance peak in the magnitude-frequency characteristic curve of Gi2ig(s), and Gi2ig(s) will amplify the harmonics whose frequency belongs to the range [70 Hz, 400 Hz] in the inverter-side current.According to the expression of the harmonic caused by the overlap time, the frequencies of the fifth and seventh harmonics are 250 Hz and 350 Hz, and belong to the resonance region, which shows that the overlap time will introduce fifth and seventh harmonic distortion to the gird-side current of CSI.

Analysis of Harmonic Losses Caused by Overlap Time
Since the fundamental component of the current and switching action times have no change, the conduction and switching losses have no relationship with the overlap time.However, the harmonic components in the inverter-side current generate harmonic losses

Analysis of Harmonic Losses Caused by Overlap Time
Since the fundamental component of the current and switching action times have no change, the conduction and switching losses have no relationship with the overlap time.However, the harmonic components in the inverter-side current generate harmonic losses on resistors.Taking the fifth harmonic as an example, according to Equations ( 3) and ( 4), the amplitude of fifth harmonic component in grid-side current can be derived as where I ag5 is the amplitude of fifth harmonic component in i ag , and ω 5 is the angular frequency of the fifth harmonic, being equal to 500π rad/s.The whole harmonic loss P h_loss caused by the overlap time is expressed as

Compensation Scheme of the Overlap Time
Figure 10 shows the control structure of the current source PV grid-connected inverter.It contains the conventional double-loop control scheme and the proposed overlap time compensation, where θ g represents the grid voltage angle and is detected by the phaselocked loop, i dg and i qg represent the grid-side currents in d-q axis, and i * dg and i * qg represent the references of i dg and i qg , respectively.i * dc is the reference of the DC-link current and is determined by the MPPT principle.The PI controller is adopted to regulate the DC-link current; its output is i * dg , and i * qg is commonly set to zero.i dg and i qg are controlled by the PI controller with feedback decoupling and active damping, and the references of inverter-side currents in the d-q axis, i * d and i * q , are obtained.
quency of the fifth harmonic, being equal to 500π rad/s.The whole harmonic loss Ph_loss caused by the overlap time is expressed as ]

Compensation Scheme of the Overlap time
Figure 10 shows the control structure of the current source PV grid-connected inverter.It contains the conventional double-loop control scheme and the proposed overlap time compensation, where θg represents the grid voltage angle and is detected by the phase-locked loop, idg and iqg represent the grid-side currents in d-q axis, and * dg i and * qg i represent the references of idg and iqg, respectively.* dc i is the reference of the DC-link cur- rent and is determined by the MPPT principle.The PI controller is adopted to regulate the DC-link current; its output is * dg i , and * qg i is commonly set to zero.idg and iqg are controlled by the PI controller with feedback decoupling and active damping, and the references of inverter-side currents in the d-q axis, * d i and * q i , are obtained.Before implementing the SVPWM algorithm, compensation is required to eliminate the current error caused by the overlap time.First, the three-phase AC-side voltages are sampled at each carrier period, so ∆ia, ∆ib, and ∆ic can be obtained by looking up Table 1.Then, Clarke and Park's transformations are performed, and the current errors of the inverter-side currents in the d-q axis, ∆id and ∆iq, are obtained.Before SVPWM, ∆id and ∆iq are subtracted from Con trol sche me According to Table 1, the proposed compensation scheme has a high requirement for AC voltage sampling accuracy.However, the filter capacitor absorbs the high-order harmonics of the inverter-side current, so there are significant ripples in the AC voltage, which seriously affect the sampling accuracy.If a low-pass filter is adopted, the phase delay will be generated, and the relations of the AC-side voltages will not be judged correctly.Therefore, a high-performance discrete filter is adopted to eliminate the ripple interference, its transfer function expression GR(z) in the z-domain is Before implementing the SVPWM algorithm, compensation is required to eliminate the current error caused by the overlap time.First, the three-phase AC-side voltages are sampled at each carrier period, so ∆i a , ∆i b , and ∆i c can be obtained by looking up Table 1.Then, Clarke and Park's transformations are performed, and the current errors of the inverter-side currents in the d-q axis, ∆i d and ∆i q , are obtained.Before SVPWM, ∆i d and ∆i q are subtracted from i * d and i * q , respectively.According to Table 1, the proposed compensation scheme has a high requirement for AC voltage sampling accuracy.However, the filter capacitor absorbs the high-order harmonics of the inverter-side current, so there are significant ripples in the AC voltage, which seriously affect the sampling accuracy.If a low-pass filter is adopted, the phase delay will be generated, and the relations of the AC-side voltages will not be judged correctly.Therefore, a high-performance discrete filter is adopted to eliminate the ripple interference, its transfer function expression G R (z) in the z-domain is where ω n is the fundamental angle frequency and T s is the sampling period.The performance of G R (z) under T s = 1 ms is shown in Figure 11.The fundamental wave of u a can be accurately extracted without phase shift under a low carrier ratio.
where ωn is the fundamental angle frequency and Ts is the sampling period.The performance of GR(z) under Ts = 1 ms is shown in Figure 11.The fundamental wave of ua can be accurately extracted without phase shift under a low carrier ratio.

Simulation Results and Analysis
In the environment of MATLAB 2022b/Simulink, the simulation models are established to verify the correctness of the analysis of the harmonic characteristics and the effectiveness of the proposed compensation method.The reference of the DC-link current is set as 15 A, fs is set as 10 kHz, the simulations are carried out under tov = 0 μs and tov = 3 μs, and the simulation waveforms and FFT results are shown in Figure 12 and Figure 13, respectively.Without the overlap time, it is obvious that there are very few harmonics in ia and iag.However, after the overlap time of 3 μs is introduced, the fundamental amplitude of ia, decreases from 9.90 A to 9.474 A, and the fifth harmonic, seventh harmonic, and total harmonic distortion (THD) significant increase.Affected by LC resonance, the harmonic distortion of iag is very significant; the ratios of the fifth harmonic and seventh harmonic are 4.52% and 3.56%.
To verify the correctness of the harmonic expression, the amplitude of the fundamental wave, fifth and seventh harmonics, and the THD of ia under different overlap times are simulated and shown in Table 2.
where Ia is the fundamental amplitude of ia, φ is the phase of ia lagging ua, and is equal to 67°.In this operation, the amplitude loss of ia related to the overlap time can be derived as

Simulation Results and Analysis
In the environment of MATLAB 2022b/Simulink, the simulation models are established to verify the correctness of the analysis of the harmonic characteristics and the effectiveness of the proposed compensation method.The reference of the DC-link current is set as 15 A, f s is set as 10 kHz, the simulations are carried out under t ov = 0 µs and t ov = 3 µs, and the simulation waveforms and FFT results are shown in Figures 12 and 13, respectively.Without the overlap time, it is obvious that there are very few harmonics in i a and i ag .However, after the overlap time of 3 µs is introduced, the fundamental amplitude of i a , decreases from 9.90 A to 9.474 A, and the fifth harmonic, seventh harmonic, and total harmonic distortion (THD) significant increase.Affected by LC resonance, the harmonic distortion of i ag is very significant; the ratios of the fifth harmonic and seventh harmonic are 4.52% and 3.56%.
To verify the correctness of the harmonic expression, the amplitude of the fundamental wave, fifth and seventh harmonics, and the THD of i a under different overlap times are simulated and shown in Table 2.
Energies 2024, 17, x FOR PEER REVIEW 12 of 19 where ∆Ia is the fundamental amplitude loss of ia.Since the contents of the fifth and seventh harmonics in ia are very few without the overlap time, ∆Ia5 and ∆Ia7, the amplitude increment of the fifth and seventh harmonics in ia, are approximately derived as s ov dc a5 43 5 s ov dc a7 43 7 Under different overlap times, ∆Ia, ∆Ia5, and ∆Ia7, shown in Table 2, are compared with Equation (7) to Equation ( 9), respectively, and the comparison results are shown in Figure 13.The amplitude errors of the fundamental wave and fifth and seventh harmonics in ia are relatively close to the lines of Equations ( 7)-( 9), which shows that the derived expression of the harmonic caused by the overlap time is theoretically correct.Next, the proposed compensation model is introduced into the simulation, and the amplitude of the fundamental wave and fifth and seventh harmonics in ia are obtained and shown in Table 3.Meanwhile, comparison results with no compensation are reflected in Figure 14; the amplitude errors of the fundamental wave and fifth and seventh harmonics in ia, can be significantly reduced by the proposed compensation scheme.At this time, the simulation waveforms and FFT results of iag under tov = 3 μs are shown in Figure 15; compared to Figures 12 and 13, the low harmonic distortion caused by the overlap time can be suppressed by the current error compensation.According to Equation (3), the fundamental of i a is expressed as where I a is the fundamental amplitude of i a , φ is the phase of i a lagging u a , and is equal to 67 • .In this operation, the amplitude loss of i a related to the overlap time can be derived as where ∆I a is the fundamental amplitude loss of i a .Since the contents of the fifth and seventh harmonics in i a are very few without the overlap time, ∆I a5 and ∆I a7 , the amplitude increment of the fifth and seventh harmonics in i a , are approximately derived as Under different overlap times, ∆I a , ∆I a5 , and ∆I a7 , shown in Table 2, are compared with Equation (7) to Equation (9), respectively, and the comparison results are shown in Figure 13.The amplitude errors of the fundamental wave and fifth and seventh harmonics in i a are relatively close to the lines of Equations ( 7)- (9), which shows that the derived expression of the harmonic caused by the overlap time is theoretically correct.
Next, the proposed compensation model is introduced into the simulation, and the amplitude of the fundamental wave and fifth and seventh harmonics in i a are obtained and shown in Table 3.Meanwhile, comparison results with no compensation are reflected in Figure 14; the amplitude errors of the fundamental wave and fifth and seventh harmonics in i a , can be significantly reduced by the proposed compensation scheme.At this time, the simulation waveforms and FFT results of i ag under t ov = 3 µs are shown in Figure 15; compared to Figures 12 and 13, the low harmonic distortion caused by the overlap time can be suppressed by the current error compensation.

Experimental Results and Analysis
To further verify the effectiveness of the overlap time compensation method proposed in this paper, a prototype of the CSI is established and shown in Figure 16, and the part numbers and parameters of each component are listed in Table 4.

Experimental Results and Analysis
To further verify the effectiveness of the overlap time compensation method proposed in this paper, a prototype of the CSI is established and shown in Figure 16, and the part numbers and parameters of each component are listed in Table 4.The operation of the experiment is the same as the simulation: idc = 15 A; fs = 10 kHz; tov = 3 μs.Without compensation, the experimental waveform and FFT result of iag are shown in Figure 17.Due to the overlap time effect and LC resonance, the obvious loworder harmonic distortion occurs in iag, where the amplitude of the fifth and seventh harmonics are 0.451 A and 0.356 A, respectively.It presents the same phenomenon as the simulation results shown in Figure 12.The operation of the experiment is the same as the simulation: i dc = 15 A; f s = 10 kHz; t ov = 3 µs.Without compensation, the experimental waveform and FFT result of i ag are shown in Figure 17.Due to the overlap time effect and LC resonance, the obvious low-order harmonic distortion occurs in i ag , where the amplitude of the fifth and seventh harmonics are 0.451 A and 0.356 A, respectively.It presents the same phenomenon as the simulation results shown in Figure 12.After the proposed current error compensation is introduced into the control algorithm, the experimental waveform and FFT result of i ag are shown in Figure 18; after compensation, the fundamental amplitude increase from 9.69 A to 9.95 A, the amplitudes of the fifth and seventh harmonics are reduced to 0.119 A and 0.097 A, and the THD decreases from 5.93% to 1.95%.After the proposed current error compensation is introduced into the control algorithm, the experimental waveform and FFT result of iag are shown in Figure 18; after compensation, the fundamental amplitude increase from 9.69 A to 9.95 A, the amplitudes of the fifth and seventh harmonics are reduced to 0.119 A and 0.097 A, and the THD decreases from 5.93% to 1.95%.
To demonstrate the necessity of the discrete filter Equation ( 9), Figure 19 shows the experimental waveform and FFT result of iag without a discrete filter.Due to the voltage sampling errors, the determination of the AC voltage relationships within a few carrier cycles is incorrect.Compared to Figure 18, although the fundamental amplitude can be compensated effectively, the suppression effect of the fifth and seventh harmonics is weaker than those adopted the discrete filter.The THD of iag is 2.65%, and the amplitudes of the fifth and seventh harmonics are 0.178 A and 0.158 A, respectively.To demonstrate the necessity of the discrete filter Equation ( 9), Figure 19 shows the experimental waveform and FFT result of i ag without a discrete filter.Due to the voltage sampling errors, the determination of the AC voltage relationships within a few carrier cycles is incorrect.Compared to Figure 18, although the fundamental amplitude can be compensated effectively, the suppression effect of the fifth and seventh harmonics is weaker than those adopted the discrete filter.The THD of i ag is 2.65%, and the amplitudes of the fifth and seventh harmonics are 0.178 A and 0.158 A, respectively.that if the AC voltage relationship can be accurately obtained, the current error and harmonic distortion caused by the overlap time can be significantly compensated.

Conclusions
To prevent an open circuit fault in the current source inverter, the switching signal needs to be delayed and turned off, resulting in overlap time and low-order harmonics appearing in inverter-side and grid-side currents.In this paper, based on analyzing the

Conclusions
To prevent an open circuit fault in the current source inverter, the switching signal needs to be delayed and turned off, resulting in overlap time and low-order harmonics appearing in inverter-side and grid-side currents.In this paper, based on analyzing the nonlinear error and harmonic characteristics caused by the overlap time, a current compensation method with an AC voltage discrete filter is proposed.Finally, the correctness and effectiveness of the theoretical analysis and compensation scheme are certified via simulation and experiment, and our conclusions are formed as follows: (1) The current error during the overlap time is only determined by the relation of the AC-side voltage; it is not related to the sector of the target current vector.(2) The overlap time leads to a decrease in the fundamental wave and an increase in the low-order odd harmonics in the inverter-side current.Due to the LC resonance, the fifth and seventh harmonics in the grid-side current will further increase.(3) Since the AC-side voltage can be accurately obtained, the nonlinear errors caused by the overlap time can be significantly reduced by the proposed compensation scheme.(4) The proposed approach is dependent on the sampling accuracy of the filter capacitor voltage.Further research can focus on the control system bandwidth design and active damping method to suppress the harmonic distortion caused by the overlap time, eliminating the need for the sampling of the voltage.

Figure 1 .
Figure 1.Topology of the current source PV grid-connected inverter.

Figure 2 .
Figure 2. Current vectors and sectors.When Iref is located in sector I, the switching signals diagrams are shown in Figure 3a, where ma, mb, and mc are the compared values of the triple commutation time, and p1-p6 represent the switching signals of S1-S6, respectively.'0′ represents off-state, and '1′ represents on-state.At this time, all switching signals of the upper bridge arm (p1, p3, and p5) remain '0′ or '1′ in a carrier period; commutation occurs among the switching tubes of the lower bridge arm (p2, p4 and p6), and the total number of commutation times is six.t1-t6 represent the commutation comments.When Iref is located in sector II, the switching signals diagrams are shown in Figure 3b, and the commutation occurs among the switching tubes of the upper bridge.The solid lines represent the actual signal waveform, and different color dashed lines are used to point out the commutation comments.

Figure 2 . 2 t 1 t 2 t 3 t 4 t 5 t 6 Figure 3 .
Figure 2. Current vectors and sectors.Under the common seven-segment sequence SVM based on the triangular carrier wave, the inverter-side current is symmetrical, and the content of the low-order harmonic is less than that under other SVM schemes.If the target vector I ref is located in sector I, I ref is synthesized by the adjacent active vectors (I 1 and I 6 ) and null vector I 7 .When I ref is located in sector I, the switching signals diagrams are shown in Figure 3a, where m a , m b , and m c are the compared values of the triple commutation time, and p 1 -p 6 represent the switching signals of S 1 -S 6 , respectively.'0' represents off-state, and '1' represents on-state.At this time, all switching signals of the upper bridge arm (p 1 , p 3 , and p 5 ) remain '0' or '1' in a carrier period; commutation occurs among the switching tubes of the lower bridge arm (p 2 , p 4 and p 6 ), and the total number of commutation times is six.t 1 -t 6 represent the commutation comments.When I ref is located in sector II, the switching signals diagrams are shown in Figure 3b, and the commutation occurs among the switching tubes of the upper bridge.The solid lines represent the actual signal waveform, and different color dashed lines are used to point out the commutation comments.

Figure 4 .
Figure 4. Switching signals diagrams with overlap time.

Figure 3 .
Figure 3. Switching signals diagrams in a carrier period under seven-segment SVM: (a) sector I; (b) sector II.

2 t 1 t 2 t 3 t 4 t 5 t 6 Figure 3 .
Figure 3. Switching signals diagrams in a carrier period under seven-segment SVM: (a) sector I; (b) sector II.

Figure 4 .
Figure 4. Switching signals diagrams with overlap time.

Figure 4 .
Figure 4. Switching signals diagrams with overlap time.

Figure 5 .
Figure 5. Equivalent circuit during the overlap time: (a) commutation from I 7 to I 1 ; (b) commutation from I 8 to I 1 .

Figure 6 .
Figure 6.The diagrams of i a , i b , and i c with their error caused by the overlap time in sector I:(a) u a > u b > u c ; (b) u a > u c > u b ; (c) u b > u a > u c ; (d) u b > u c > u a ; (e) u c > u a > u b ; (f) u c > u b > u a .

Figure 7 .
Figure 7.The diagrams of i a , i b , and i c with their error caused by the overlap time in sector II: (a) u a > u b > u c ; (b) u a > u c > u b ; (c) u b > u a > u c ; (d) u b > u c > u a ; (e) u c > u a > u b ; (f) u c > u b > u a .

Figure 10 .
Figure 10.Control structure with compensation of the overlap time.

Figure 10 .
Figure 10.Control structure with compensation of the overlap time.

Figure 11 .
Figure 11.The waveforms of ua before and after the discrete filter.

Figure 11 .
Figure 11.The waveforms of u a before and after the discrete filter.

Figure 12 .Figure 13 .
Figure 12.Simulation results without overlap time: (a) switching signals; (b) FFT results of i a ; (c) i ag , (d) FFT results of i ag .

Figure 13 .
Figure 13.Simulation results with overlap time of 3 µs: (a) switching signals; (b) FFT results of i a ; (c) i ag ; (d) FFT results of i ag .

Figure 15 .
Figure 15.Simulation results after compensation under t ov = 3 µs: (a) waveform of i ag ; (b) FFT results of i ag .

Figure 17 .
Figure 17.Experimental results without compensation under t ov = 3 µs: (a) waveform of i ag ; (b) FFT result of i ag .Purple arrow-the zero tick mark.

Figure 18 .
Figure 18.Experimental results with compensation under t ov = 3 µs: (a) waveform of i ag ; (b) FFT result of i ag .Purple arrow-the zero tick mark.

Figure 20
Figure 20 shows the comparison results of no compensation, compensation without discrete filter, and the proposed compensation under different overlap time, which shows

Figure 19 .
Figure 19.Experimental results with compensation and no discrete filter under t ov = 3 µs.: (a) waveform of i ag ; (b) FFT results of i ag .Purple arrow-the zero tick mark.

Figure 20
Figure20shows the comparison results of no compensation, compensation without discrete filter, and the proposed compensation under different overlap time, which shows that if the AC voltage relationship can be accurately obtained, the current error and harmonic distortion caused by the overlap time can be significantly compensated.Energies 2024, 17, x FOR PEER REVIEW 17 of 19

Figure 20 .
Figure 20.The comparison results of no compensation, compensation without discrete filter, and the proposed compensation under different overlap time: (a) fundamental amplitude; (b) THD; (c) amplitude of fifth harmonic; (d) amplitude of seventh harmonic.

Figure 20 .
Figure 20.The comparison results of no compensation, compensation without discrete filter, and the proposed compensation under different overlap time: (a) fundamental amplitude; (b) THD; (c) amplitude of fifth harmonic; (d) amplitude of seventh harmonic.
Topology of the current source PV grid-connected inverter.

Table 2 .
Average current error caused by the overlap time.

Table 3 .
The low harmonic characteristics of ia after the proposed compensation.

Table 2 .
Average current error caused by the overlap time.

Table 3 .
The low harmonic characteristics of ia after the proposed compensation.

Table 4 .
The part numbers and parameters of each component.

Table 4 .
The part numbers and parameters of each component.