OpenEdgePMU: An Open PMU Architecture with Edge Processing for Future Resilient Smart Grids

: The increase in renewable energy sources (RESs) in distribution grids is a major driver for achieving green energy goals worldwide. However, RES power inverters affect power quality, increase power losses, and, in certain cases, may cause power interruptions due to harmonics, deterioration of the rate of change of frequency, and inability to rapidly react in grid faults. Today, phasor measurement units (PMUs) are the ultimate tools for real-time monitoring of distribution grids’ health, and they enable several data-driven added-value services such as fast and automated fault detection, isolation, and recovery; state estimation; power quality monitoring; dynamic events analysis, etc. The present paper proposes an open hardware and software PMU platform, which is low cost, high performance, expandable, and, in general, suitable for research and innovation activities. The system is based on two processor modules (a digital signal processor from Texas Instruments TMS320c5517, and a microprocessor System-in-Package from Octavo Systems OSD3358), two local databases of 64 Gbytes each, GPS module, 5G modem interface, as well as analog and signal conditioning circuits to interface three-phase power voltage and current signals. The entire hardware design, schematics, and instrumentation components, as well as all ﬁrmware and software functions are completely open source. Pilot operation of the prototype design has been installed in three medium-/low-voltage substations in Cyprus, as well as twelve substations in Spain and Italy.


Introduction
Today, synchrophasor technology offers a valuable tool for monitoring and analyzing power systems.Phasor measurement units (PMUs) digitize voltage and current phasors with high frequency and synchronize acquired data with absolute timing via satellite GPS signals.By using advanced signal processing and correlation techniques on the data received from several PMUs, a high-quality analysis of the dynamic behavior of the electric power grid can be performed.Nowadays, this method is very valuable due to increasing penetration of renewable energy sources (RESs) and the increased stochasticity of distribution grid management.Apart from analysis purposes, today, PMUs are used for fast monitoring, protecting, and automating contemporary complicated distribution systems.Typical applications regarding wide area monitoring in distribution grids include: angle/frequency monitoring, post mortem analysis, voltage stability monitoring, improved state estimation, DG/IPP applications, power system restoration, etc. [1].Further interesting applications of PMUs for distribution networks are: microgrid automation and operations, fault detection and localization, FACTS devices, grid's situational awareness, power quality analysis, etc. [2][3][4][5][6][7].
Energies 2023, 16, 2756 4 of 29 Schofield et al. [28], in 2018, carried out a review of commercial implementation of PMUs, and then open-source-based implementations (open architecture hardware and software).They also demonstrated the realization of another low-cost design.
Bucci et al. [29], in 2019, designed and implemented a measuring system based on a high-performance microcontroller that could carry out power quality analysis of three phase power systems.The main features of the design were cost effectiveness, reduced dimensions, and low power consumption, which made it suitable for installation in existing electrical cabinets or civil and commercial users.
Femine et al. [30], in 2019, presented another low-cost implementation of a PMU.The key feature of the design was that the data acquisition, data processing, and data communication were integrated in a single low-cost microcontroller.A thorough metrological characterization of the realized prototype was conducted, using a high-performance PMU calibrator.
Seger et al. [31], in 2020, prototyped another low-cost design approach for a PMU.The device was built around an ARM board and commercially available modules.A comparison with a commercial PMU device demonstrated that similar results for monitoring low voltage networks and frequency events could be achieved, however, with a cost between USD 100 and 150.
Shankar et al. [32], in 2021, presented the development for a low-cost design and implementation of a PMU.The design followed the existing IEEE standards for synchrophasor measurement with the help of Arduino Uno and Arduino Due microcontrollers.
Rama Raju et al. [33], in 2021, developed a cost-effective PMU for wide area monitoring system applications, with open-source hardware, which could be easily modified as per the requirements of the applications.
The most recent approach comes from Schofield et al. [34], in 2022, with the lowcost PMU named PhasorsCatcher.The design is described in high detail, and the performance proved to be acceptable for research approaches in distribution grids.Last but not least, three PhD dissertations have designed and developed experimental PMU architectures [35][36][37].
Taking into consideration all the above-mentioned publications, it seems that, since 2008, several designs and implementations of experimental PMU arrangements have been researched and proposed.Most of the designs have focused on low cost, some of them are open source, and some others are based on COTS programmable evaluation modules and boards.In several cases, the experimental prototypes have achieved performances comparable to more expensive commercial devices.
Although several industrial PMU devices are currently available in the market, all the systems are based on closed proprietary technologies and are mainly targeted to commercial applications.In addition, although certain open-source PMU and laboratory/breadboard approaches are also available, there is an implementation maturity gap compared to off-theshelf devices.These experimental devices are not suitable for pilot installation, something that is highly required in research and innovation actions and initiatives.In addition, recent advances in smart grid research towards future resilient distribution grids need to go a step further from simulation environments and need to apply proposed state-of-the-art methodologies and algorithms in real application fields.In such cases, the deployable systems should comply with a minimum of industrial hardware standards and specifications, as well as provide re-programmable open platforms that are able to easily deploy AI applications, following edge and fog approaches.Finally, both hardware and software platforms should be easy to be tailored according to specific application requirements.

Motivation for the OpenEdgePMU Initiative
The motivation behind the present project is to establish an open community focused on high-end PMU applications for distribution grids.The principal novelty of the project is to provide a rigid set of open-source hardware and software tools that are useful for easy and flexible implementation of pilot arrangements for research and innovation actions, with interest coming from academic entities, institutes, innovative SMEs, and startups.
Special interest in our initiative is anticipated by research and innovation projects (such as the European Union Research and Innovation Actions-RIA), where in most cases, system analyses based on simulations are not always adequately deliverable.These projects require proof-of-concepts and pilot installations in real-world applications and use case scenarios.A major necessity when developing and deploying such systems is to utilize programmable devices that have small knowledge entry barriers and comply with certain engineering standards (e.g., EMI, EMC, safety, etc.).Although development platforms and breadboards for laboratory use are widely available and adopted by academia, the hardware maturity is not adequate for industrial applications, even when targeting pilot cases.Certain development boards, such as Raspberry PI [38] and Beaglebone Black [39], can partially cover the applications' requirements; however, custom-made add-on cards, modules, and interfaces with external devices are also required.Thus, the total design fall (in most cases) into the breadboard/prototype status.
The proposed OpenEdgePMU initiative, bridges the aforementioned gap, and may help smart energy related academic entities to propose more mature hardware & software concepts for pilot cases and easily attract collaboration with potential end-users, such as electricity utilities, distribution system operators, energy generation plant owners, etc., in innovation activities.Targeting to increase the impact of our initiative in the research and innovation community, the OpenEdgePMU initiative provides open-source licensing for all software and hardware developments; the software is provided under the GPL license [34,35] and the hardware is provided under the TAPR Open Hardware license [14,15].

Challenges and Requirements for Distribution Grid PMUs
By focusing on PMU applications for power distribution grids, particular challenges must be taken into consideration.First, since most industrial PMUs are designed for transmission systems and contain a high number of functionalities, the cost is rather high.In distribution grids, the number of required PMU devices is high.The complexity of the distribution grid, having several distributed generation units and several different kinds of load, requires a much higher number of measuring devices.Even though the equipment cost is not the biggest part of the total cost of ownership for PMU applications [40], a possible high number of devices required in distribution grid applications could make the case unaffordable for massive exploitation.
In addition, transmission and distribution system measurements have key differences that must be taken into consideration [19,23].For instance, the phase angle resolution regarding the distribution system must be as low as a few millidegrees, whereas in the transmission system a few degrees may be adequate.The resolution of the phasor magnitudes must be better in distribution grids as well as the accuracy of measurement, and the noise filtering and rejection in distribution grids need to be improved compared to transmission system cases.In general, combining both magnitude and phase, the accuracy of the TVE must be in the 0.0x% range.
The size of the devices is another factor that could affect deployment of PMUs in distribution grids.The available space for electronic equipment, especially in the secondary distribution substations, is very limited.Therefore, only compact apparatuses are possible to be installed and, in most cases, must comply to certain mechanical standards of the cabinets (e.g., DIN rail mount, etc.).
Furthermore, challenges regarding PMUs for distribution grids are relevant to highfidelity data integration with utility distribution operations [3].In a typical distribution grid case, several PMUs generate enormous numbers of data, which (at least) must be filtered, stored, transmitted, processed, correlated, and visualized in real time, in order to provide useful information and support operators' decisions.Several emerging trade-offs create a situation with extremely innovative potential.For instance, the dilemma of edge/fog vs. cloud processing, or centralized vs. distributed data storage and processing, etc., seems to create huge research and scientific interest with respect to proposing new algorithms and innovative applications.

Novelty of the OpenEdgePMU Initiative
Based on all the above-mentioned challenges and applications' requirements, as well as the extensive review of recent PMU designs available in the scientific literature, our approach aims at aggregating the following high-level requirements, features, and functionalities into a novel integrated arrangement:

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Soft real-time edge/fog processing;

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Adequate project documentation to support adoption from the research and scientific community.
Our desire is to emphasize the edge/fog capabilities of the OpenEdgePMU system, as we vastly believe that the majority of future energy smart grid applications must follow similar concepts for several different reasons.First, a major trend today is to take advantage of the vast amount of generated data acquired by sensors installed in the field.These timeseries contain valuable information that can be extracted by artificial intelligence algorithms.Without edge processing capability, huge datasets must be transmitted to cloud software applications, in order to proceed to data processing, something that, in general, may be very challenging due to communication bandwidth limitations, cost of transmission, delays caused by data transfers, etc.The proposed OpenEdgePMU system supports a novel edge processing approach.Edge processing together with the availability of local databases are used to eliminate the previously mentioned challenges.The following steps are applied:

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Vast amounts of locally generated data are processed by artificial intelligence agents running locally.

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The edge system generates only events to remote cloud software backends/frontends, thus reducing the necessity of extensive communication bandwidth and the relevant cost of transmission.

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The edge system stores the generated data timeseries locally, in case of a potential end-user's request for further detailed analysis.This distributed database may also vastly reduce the costs for cloud services.

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The edge system that processes the acquired data can communicate with minimum delays with other edge systems that are able to execute actions and control (e.g., protection, automation, etc.).The 5G infrastructure comes together to minimize communication latency and provide time-critical solutions.
The following sections present a brief description of all the system's components and related functionalities.The description begins with an overview of the system, continues with descriptions of the key components such as the DSP module, the edge processing module, the GPS, and the power supply module, and finishes with brief descriptions of certain application cases and projects that have been recently applied.

System Architecture
The OpenEdgePMU system is based on a configuration that uses two powerful processors: one processor that targets hard real-time deterministic responses and another processor for soft real-time functionalities.A GPS system is used to resynchronize the data acquisition with the global absolute time.Extensive on-system nonvolatile memory provides the opportunity for distributed databases.Fast Ethernet is used for interfacing 5G or ADSL communication means.More specifically, the high-level architecture of the proposed OpenEdgePMU system is depicted in Figure 1.The system consists of the following subsystems:

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The digital signal processor (DSP) module which is responsible for all hard real-time processing of the digitized phasor signals.It also contains the digitizer and analog conditioning electronic circuits that are responsible for interfacing with the external sensors of the phasor signals, as well as filtering and amplification suitable for the digitizer, which is responsible for the analog-to-digital conversion of the acquired phasor signals.

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The edge gateway module, which is responsible for all soft real-time processing, such as artificial intelligence, communication protocols, etc.

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The GPS module which is responsible for interfacing the satellite GPS signals, keeping absolute timing, and generating the time resynchronization signal for the digitizer.

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The power supply module which is responsible for the AC-to-DC conversion of one of the voltage phasors, to suitable low voltages for powering all electronic components.
related functionalities.The description begins with an overview of the system, continues with descriptions of the key components such as the DSP module, the edge processing module, the GPS, and the power supply module, and finishes with brief descriptions of certain application cases and projects that have been recently applied.

System Architecture
The OpenEdgePMU system is based on a configuration that uses two powerful processors: one processor that targets hard real-time deterministic responses and another processor for soft real-time functionalities.A GPS system is used to resynchronize the data acquisition with the global absolute time.Extensive on-system nonvolatile memory provides the opportunity for distributed databases.Fast Ethernet is used for interfacing 5G or ADSL communication means.More specifically, the high-level architecture of the proposed OpenEdgePMU system is depicted in Figure 1.The system consists of the following subsystems:

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The digital signal processor (DSP) module which is responsible for all hard real-time processing of the digitized phasor signals.It also contains the digitizer and analog conditioning electronic circuits that are responsible for interfacing with the external sensors of the phasor signals, as well as filtering and amplification suitable for the digitizer, which is responsible for the analog-to-digital conversion of the acquired phasor signals.

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The edge gateway module, which is responsible for all soft real-time processing, such as artificial intelligence, communication protocols, etc.

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The GPS module which is responsible for interfacing the satellite GPS signals, keeping absolute timing, and generating the time resynchronization signal for the digitizer.

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The power supply module which is responsible for the AC-to-DC conversion of one of the voltage phasors, to suitable low voltages for powering all electronic components.

DSP Module
The DSP module handles all time-critical, hard real-time functionalities.The DSP module has been based on the design of the Texas Instruments TMDSEVM5517-C5517 Evaluation Module (EVM) [41].The block diagram of the DSP module is depicted in Figure 2. The key components of the DSP module are: • DSP TMS320c5517 (Texas Instruments, Dallas, TX, USA) [42] is the brain of the module running a firmware that handles all operations related to data acquisition, storage, processing synchronization, communication, and configuration.This is a highperformance, low-power, fixed-point digital signal processor from Texas Instruments, with the following specifications: • SDRAM (external) (Micron MT48H32M16LF) [43] is useful for firmware execution.The size of the SDRAM is 64 MB.

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Nonvolatile flash memory (external) (Infineon S29GL128S11DHIV20) [44] for storing the firmware of the DSP module.The size of the FLASH memory is 16 MB.The memory is in-system programmable; therefore, the developer can change and upload the DSP module's firmware.

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Nonvolatile SD memory (SD Card) [45] for storing the acquired data and other parameters for configuring the device.The default storage size is 64 GB and, depending on the sampling frequency, the storage period can last from some hours to several days.

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Analog-to-digital converter (ADS8586S, Texas Instruments) [46] for digitizing the analogue input signal.This is a 6-channel, high-speed, simultaneous-sampling ADC, with 16-bit resolution and fully differential bipolar inputs on a single supply, with the following key performance specifications: 1. 250 kSPS max throughput per channel; 2.
Antialiasing low-pass filter to 24 kHz for ±10 V range and to 16  Range, 100 mV/1000 A typical, but configurable for different sensors.
As depicted in Figure 2, the following interfaces with other subsystems are provided: • Full Duplex UART serial interface at 921,600 bps for direct debugging using a common terminal (common interface with MCU/edge processing module).
• Current analog input interface, to connect the external Rogowski coil; • Full-duplex UART serial interface with the MCU/edge processing module, providing bandwidth 921,600 bps; • GPS-PPS input signal interface, used for immediate external interrupt to the DSP, in order to resynchronize the internal sampling frequency timer; • JTAG interface, used for connecting an external JTAG board to interconnect the DSP module with Texas Instruments Code Composer Studio environments, useful for firmware development and debugging; • Full Duplex UART serial interface at 921,600 bps for direct debugging using a common terminal (common interface with MCU/edge processing module).The DSP module is supported by two firmware: bootloader and application.The bootloader is used for bootstrapping the system, i.e., load the application firmware to the appropriate system memories, and then initiating execution.Based on certain jumper switches, the developer can use different boot loading sources, such as flash, SD, and McBSP.The standard boot loading method is via flash memory.The application firmware contains all the DSP module functionalities, which can be categorized as hard real-time, soft real-time, and system support functionalities:

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Hard real-time functionalities: 1. Sampling of six (6) channels and conversion to digital signals; 2. Storage of digital signals to the nonvolatile SD memory using EDMA transfers; 3. Processing of the digital signals; 4. Timing resynchronization with GPS.
• System support functionalities: The DSP module is supported by two firmware: bootloader and application.The bootloader is used for bootstrapping the system, i.e., load the application firmware to the appropriate system memories, and then initiating execution.Based on certain jumper switches, the developer can use different boot loading sources, such as flash, SD, and McBSP.The standard boot loading method is via flash memory.The application firmware contains all the DSP module functionalities, which can be categorized as hard real-time, soft real-time, and system support functionalities:
Sampling of six (6) channels and conversion to digital signals; 2.
Storage of digital signals to the nonvolatile SD memory using EDMA transfers; 3.
Processing of the digital signals; 4.
Timing resynchronization with GPS.
Communication with the edge processing module; 2.
Debugging via JTAG and Texas Instruments CCS; 4.
In-system programming.
The application firmware of the DSP module is divided into four main layers: drivers, support libraries, processes, and application (shown in Figure 3).The structuring of all four layers is based on the pattern where higher level layers always utilize elements from lower level layers.The following list provides a description regarding each layer:

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The drivers layer is responsible for low-level driver implementation regarding certain internal DSP peripherals and external peripherals.The DSP internal peripherals are McSPI, I2C, UART, SD/MMC, EMIF, EDMA, GPIO, and ISR.The external peripherals are the ADC, NOR flash, and SDRAM memories.

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The support layer provides the application programming interface (API) to be used by processes to access low-level functionalities.This includes the terminal prompt interface, the file system, and the XTERM support library, which is an implementation of the XMODEM protocol [47] used in In-System-Programming (ISP) to support future firmware updates, as well as potential file/data transfers.

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The process layer contains high and low priority processes related to device operation, including data acquisition (ACQ), data handling (DH), communication with the GW module (REMOTE), and the command prompt.

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The application Layer refers to the top-level application related to the actual functional operation of the DSP module regarding measurement.Essentially, this is a single entity that combines different processes to accomplish a certain task.
lower level layers.The following list provides a description regarding each layer: • The drivers layer is responsible for low-level driver implementation regarding certain internal DSP peripherals and external peripherals.The DSP internal peripherals are McSPI, I2C, UART, SD/MMC, EMIF, EDMA, GPIO, and ISR.The external peripherals are the ADC, NOR flash, and SDRAM memories.

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The support layer provides the application programming interface (API) to be used by processes to access low-level functionalities.This includes the terminal prompt interface, the file system, and the XTERM support library, which is an implementation of the XMODEM protocol [47] used in In-System-Programming (ISP) to support future firmware updates, as well as potential file/data transfers.

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The process layer contains high and low priority processes related to device operation, including data acquisition (ACQ), data handling (DH), communication with the GW module (REMOTE), and the command prompt.

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The application Layer refers to the top-level application related to the actual functional operation of the DSP module regarding measurement.Essentially, this is a single entity that combines different processes to accomplish a certain task.The acquired data are stored into an intermediate memory buffer (Block_MEASURE-MENT) as depicted in Algorithm 1.This memory buffer is separated into two identical parts.Each part contains the date and time of the first sample with millisecond accuracy, an array of 1363 samples for each one of the six channels, and finally a 32-bit checksum of the contained data into this structure (Figure 4).When the ISR-TMR0 completes filling one Block_Measurement buffer, it continues to the next one.The soft real-time functionalities follow a round robin execution of three functions: proc_STORAGE, proc_DSP, and proc_REMOTE.All these processes are realized as state machines running in a cooperative manner, by means of sharing the available processing in reasonable time.The storage process checks if the hard real-time ISR-TMR0 has filled one Block_Measurement, to transfer the total block to the nonvolatile SD memory, via the MMC/SD peripheral of the DSP using EDMA transfers to achieve the best possible performance.The implementation achieves continuous and uninterruptible storage of all six channels at 250 KHz sampling frequency, which means 6 channel × 250.000 samples/channel × 2 Bytes/sample = 3 Mbytes/s.The DSP process refers to any digital signal processing functionality that the developer needs to execute.The sample-by-sample and block processing options are both available to be applied according to the developer's request.The The soft real-time functionalities follow a round robin execution of three functions: proc_STORAGE, proc_DSP, and proc_REMOTE.All these processes are realized as state machines running in a cooperative manner, by means of sharing the available processing in reasonable time.The storage process checks if the hard real-time ISR-TMR0 has filled one Block_Measurement, to transfer the total block to the nonvolatile SD memory, via the MMC/SD peripheral of the DSP using EDMA transfers to achieve the best possible performance.The implementation achieves continuous and uninterruptible storage of all six channels at 250 KHz sampling frequency, which means 6 channel × 250.000 samples/channel × 2 Bytes/sample = 3 Mbytes/s.The DSP process refers to any digital signal processing functionality that the developer needs to execute.The sample-by-sample and block processing options are both available to be applied according to the developer's request.The remote process is responsible for handling all data communication and commanding by using the edge gateway module.Again, this process follows a state machine approach, to avoid monopolizing the available processing time with this task.The firmware of the DSP module also provides certain non-real-time processes (pro-cess_PROMPT, process_XTERM, etc.) that are responsible for the module's configuration, debugging, and other supporting tasks.The nonvolatile SD card of the DSP module provides a local database that is used for storage of: The biggest part of the memory is used for storage of the acquired signal data.Depending on the application requirements, the developer may change the default nonvolatile memory configuration accordingly.In addition, larger SD card sizes (e.g., 128 GBytes+) can probably be used; however, these have not yet been validated.Due to very high storage rates, very high-speed SD cards have been chosen (such as the SanDisk Extreme ® microSD™ UHS-I Card) [45].

Edge Processing Module
The edge processing module is based on the Beaglebone Black design [39].It can run a Linux operating system and is responsible for most soft real-time functionalities, including AI processing, communication protocols, IoT interfacing with the backend, etc.The brain of the module is the OSD3358 System-on-Chip (SoC) [48], which includes the following key features:
Figure 5 shows the high-level architecture of the edge processing module, including the interfaces with other subsystems.As depicted, the MCU (OSD3358) provides the following interfaces: • MMC to interface with the SD memory card storing the OS and all the data; Figure 5 shows the high-level architecture of the edge processing module, including the interfaces with other subsystems.As depicted, the MCU (OSD3358) provides the following interfaces: • MMC to interface with the SD memory card storing the OS and all the data; • I2C to interface with the on-board EEPROM memory; • UART to interface with the PMU and other external modules; • Ethernet to provide an Ethernet interface to connect to the local network.The edge processing module software is based on the Linux Debian 10 operating system.This is important since critical functionalities, especially in terms of networking, become immediately available.These include all the TCP/IP protocol stack and security via firewalls.Additionally, the use of Linux OS allows the creation of software using highlevel programming languages such as C++ and Python.Python is the main programming language used in the development of the provided software.Python was selected for its readily available scientific and mathematical libraries that allow quick development of AI functionalities.The following libraries come preinstalled in the edge processing module software: • PandaPower [49], a library used for power system modeling; • Pandas [50], a numerical and data analysis library; • Scikit-learn [51], an AI construction and execution library; • Flask [52], a library for the development of HTTP-REST interfaces; • SQLite [53], a library for the interaction with the local SQLite database.
It is noted that the user can add libraries to cover other specific needs.Additionally, it is also noted that the user may rely on a completely different programming stack by using the Linux distribution's repositories.The current stack is depicted in Figure 6.The edge processing module software is based on the Linux Debian 10 operating system.This is important since critical functionalities, especially in terms of networking, become immediately available.These include all the TCP/IP protocol stack and security via firewalls.Additionally, the use of Linux OS allows the creation of software using highlevel programming languages such as C++ and Python.Python is the main programming language used in the development of the provided software.Python was selected for its readily available scientific and mathematical libraries that allow quick development of AI functionalities.The following libraries come preinstalled in the edge processing module software: • PandaPower [49], a library used for power system modeling; • Pandas [50], a numerical and data analysis library; • Scikit-learn [51], an AI construction and execution library; • Flask [52], a library for the development of HTTP-REST interfaces; • SQLite [53], a library for the interaction with the local SQLite database.
It is noted that the user can add libraries to cover other specific needs.Additionally, it is also noted that the user may rely on a completely different programming stack by using the Linux distribution's repositories.The current stack is depicted in Figure 6.The application software is built on top of the aforementioned stack and its main functionalities are: Figure 7 depicts the high-level architecture of the edge processing module application software.It consists of the following main building blocks:

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The DSP module connector is responsible for connecting the edge processing module application with the DSP module via the serial port.After a successful connection, it can retrieve the current measurement of the DSP module.Additionally, it is respon- The application software is built on top of the aforementioned stack and its main functionalities are:

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Command and control of the PMU, including commands for the DSP module; Figure 7 depicts the high-level architecture of the edge processing module application software.It consists of the following main building blocks:

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The DSP module connector is responsible for connecting the edge processing module application with the DSP module via the serial port.After a successful connection, it can retrieve the current measurement of the DSP module.Additionally, it is responsible for periodically retrieving the latest measurements of the DSP module.It also stores the measurements to the database after successful retrieval.

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The REST server is a stand-alone service, based on the Flask framework, and is responsible for deploying a RESTful API on the edge processing module application, to serve HTTP requests.Such requests can refer to the latest measurements retrieved from the DSP module, historic measurements, or the status of the device (e.g., connection status, free storage space, MAC address, etc.).For the first two types of requests, the REST server connects directly to the database and retrieves the requested data, while for the third type of request, the REST server obtains the relevant information directly from the OS, by executing certain Linux commands.In all cases, the REST server will reply to the client with a REST protocol HTTP response, containing either the requested data upon success, or an error message upon failure.

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The real-time database component acts as a bridge between the edge processing module application and the database.Any measurements that must be stored are first sent to this agent, who is then responsible for storing them properly.Additionally, this agent handles write errors (e.g., duplicate values), database connectivity issues, and provides the state fetcher agent any measurements that might be requested.The latter functionality is crucial when storing rows across multiple tables, which must link their data by utilizing foreign keys.

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The SQLite database application, after retrieving the measurements, takes care of storing the measurements in the database that the device has in its storage disk.Since this database is installed on each device, it is important to consider some basic parameters, such as the storage frequency and the size of the tables.A fine balance between collecting adequate data samples for future analysis and properly utilizing the limited storage space is found in one-minute sampling of the real-time DSP module measurements.Regarding the storage frequency, the storage (by the gateway application) and the retrieval (by the main application) can differ.In addition, the database used is relational and is based on SQLite technology.It is noted that the database already has a predetermined structure that allows the continuous storage of PMU and RTU data.
Energies 2023, 16, 2756 14 of 30 All of the above are designed to run as out-of-the-box features, meaning that even without developing an additional AI application, all PMU data are collected, stored, and exposed via a dedicated API.However, by using the above features and the power of the preinstalled libraries, one can create AI-powered applications without having to worry about the low-level technical issues such as data retrieval from the DSP module.

GPS Module
The OpenEdgePMU system contains a Global Positioning System (GPS) module to acquire the global absolute time and to use the GPS-PPS signal for resynchronizing acquisition.A UART interface is utilized for communicating with the edge processing module to configure system time.The following two GPS modules can be used in the All of the above are designed to run as out-of-the-box features, meaning that even without developing an additional AI application, all PMU data are collected, stored, and exposed via a dedicated API.However, by using the above features and the power of the preinstalled libraries, one can create AI-powered applications without having to worry about the low-level technical issues such as data retrieval from the DSP module.

GPS Module
The OpenEdgePMU system contains a Global Positioning System (GPS) module to acquire the global absolute time and to use the GPS-PPS signal for resynchronizing acquisition.A UART interface is utilized for communicating with the edge processing module to configure system time.The following two GPS modules can be used in the OpenEdgePMU system:
The options both provide an uncertainty of the PPS signal less than 500 ns.

Power Supply Module
The power supply module (PSM) is responsible for providing power to all electronic components.The PSM input is the 230 VAC input from any of the three input voltage phases.Figure 8 depicts the high-level architecture of the PSM.The AC mains filter is used to protect the power supply from signal interference coming from the input voltage.The primary AC-to-DC converter is used to convert the 230 VAC to 5 VDC.Several other DC-to-DC converters generate all required voltages for the system's electronics.The main design specifications of the PSU are: All of the above are designed to run as out-of-the-box features, meaning that even without developing an additional AI application, all PMU data are collected, stored, and exposed via a dedicated API.However, by using the above features and the power of the preinstalled libraries, one can create AI-powered applications without having to worry about the low-level technical issues such as data retrieval from the DSP module.

GPS Module
The OpenEdgePMU system contains a Global Positioning System (GPS) module to acquire the global absolute time and to use the GPS-PPS signal for resynchronizing acquisition.A UART interface is utilized for communicating with the edge processing module to configure system time.The following two GPS modules can be used in the OpenEdgePMU system: The options both provide an uncertainty of the PPS signal less than 500 ns.

Power Supply Module
The power supply module (PSM) is responsible for providing power to all electronic components.The PSM input is the 230 VAC input from any of the three input voltage phases.Figure 8 depicts the high-level architecture of the PSM.The AC mains filter is used to protect the power supply from signal interference coming from the input voltage.The primary AC-to-DC converter is used to convert the 230 VAC to 5 VDC.Several other DCto-DC converters generate all required voltages for the system's electronics.The main design specifications of the PSU are:

Results and Discussion
This section presents the results regarding the implementation and certain application cases of the OpenEdgePMU system.

Hardware Implementation
Hardware implementation of the OpenEdgePMU system consists of three (3) electronics boards:

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The DSP board is one of the key components in the OpenEdgePMU system.To simplify the overall design and utilization of the DSP in different devices, the DSP board is segregated by having its own design.In this way, a separate board was designed to include all the necessary components required for the DSP to operate with the aim to keep the digital high-speed electronics section segregated and to expose all the necessary interfaces via a common board-to-board mezzanine connector.The idea is that the DSP board is mounted onto the main board of the PMU module, which has a simpler design and uses only the necessary interfaces required.Figure 9 shows the top side of the DSP board, depicting its main components (DSP, external memory modules, power regulator, crystal etc.).The DSP Board has: Estimated cost, €120.
• Regarding the edge board, as shown in Figure 10, the edge processing module is also segregated from the OpenEdgePMU system; it is essentially a separate board that is connected to the OpenEdgePMU base board.This board includes the most essential elements to make the MCU OSD3358 SoC operate properly, and all the interfaces are exposed to two mezzanine connectors to be used in other designs depending on the application.This is done to simplify the design process and to easily accommodate different designs utilized in different devices.Figure 10  Estimated cost, €200.

Results and Discussion
This section presents the results regarding the implementation and certain application cases of the OpenEdgePMU system.

Hardware Implementation
Hardware implementation of the OpenEdgePMU system consists of three (3) electronics boards:

•
The DSP board is one of the key components in the OpenEdgePMU system.To simplify the overall design and utilization of the DSP in different devices, the DSP board is segregated by having its own design.In this way, a separate board was designed to include all the necessary components required for the DSP to operate with the aim to keep the digital high-speed electronics section segregated and to expose all the necessary interfaces via a common board-to-board mezzanine connector.The idea is that the DSP board is mounted onto the main board of the PMU module, which has a simpler design and uses only the necessary interfaces required.Figure 9 shows the top side of the DSP board, depicting its main components (DSP, external memory modules, power regulator, crystal etc.).The DSP Board has:  • Regarding the edge board, as shown in Figure 10, the edge processing module is also segregated from the OpenEdgePMU system; it is essentially a separate board that is connected to the OpenEdgePMU base board.This board includes the most essential elements to make the MCU OSD3358 SoC operate properly, and all the interfaces are exposed to two mezzanine connectors to be used in other designs depending on the application.This is done to simplify the design process and to easily accommodate different designs utilized in different devices.Figure 10 depicts the top side of the edge board.The edge board has: As an alternative to the developed edge processing module, a COTS Beaglebone Black can be used, Figure 11.

•
The main board includes all other electronic components of the OpenEdgePMU system, such as the power supply, the analog conditioning and ADC part of the DSP module, input/output connectors, etc., as well as all other sockets suitable to attach the rest of the circuits, such as the DSP board, the edge board, and the GPS. Figure 12 shows the board without and with system add-on components.The main board has:  As an alternative to the developed edge processing module, a COTS Beaglebone Black can be used, Figure 11.

•
The main board includes all other electronic components of the OpenEdgePMU system, such as the power supply, the analog conditioning and ADC part of the DSP  As an alternative to the developed edge processing module, a COTS Beaglebone Black can be used, Figure 11.

•
The main board includes all other electronic components of the OpenEdgePMU system, such as the power supply, the analog conditioning and ADC part of the DSP module, input/output connectors, etc., as well as all other sockets suitable to attach the rest of the circuits, such as the DSP board, the edge board, and the GPS. Figure 12 shows the board without and with system add-on components.The main board has:

Current Funded Projects Using the OpenEdgePMU System
3.2.1.eBalance+ Project (European Union H2020) The design of the OpenEdgePMU system has been used in the eBalance+ project [56] for a low voltage management unit (LVGMU).Figure 13 depicts a diagram of how the hardware units have been enclosed in a plastic box and interfaced with external sensors and subsystems.The PMU module, and eventually the LVGMU device, are integrated directly with the transformer.Specifically, the voltage inputs, on the one hand, are directly

eBalance+ Project (European Union H2020)
The design of the OpenEdgePMU system has been used in the eBalance+ project [56] for a low voltage management unit (LVGMU).Figure 13 depicts a diagram of how the hardware units have been enclosed in a plastic box and interfaced with external sensors and subsystems.The PMU module, and eventually the LVGMU device, are integrated directly with the transformer.Specifically, the voltage inputs, on the one hand, are directly connected to the low-voltage side of the transformer; three inputs correspond to the three grid phases.The current inputs, on the other hand, are connected using Rogowski coil sensors that measure the current through each phase line.The device is designed to accommodate different types of Rogowski coil sensors by simply configuring a specific parameter to translate the output of the sensor to ampere units.The LVGMU is housed in a polycarbonate enclosure with the dimensions 300 mm × 200 mm × 90 mm. Figure 13 shows the connections between the LVGMU and the external elements, the types of cables used, and information about the connectors used.As depicted, the cable used to connect to the transformer is a 4 × 2.5 mm 2 cable, although other types with thinner inner wires can also be used, since the size of the cordgrip used (M20) can accept cables of 12 mm maximum diameter.Similar type cordgrips, but smaller size (M12), are used to hold the Rogowski coil sensor cables entering the enclosure.For the power input, an IEC C14 plug is used, which is part of the input AC mains filter that is included.For the network interface, a common panel mount RJ45 connector is used to provide the Ethernet interface required.Finally, an SMA connector is provided for the connection of the GPS antenna.Within the context of the eBalance+ project, two different pilot demo sites are foreseen: the University of Malaga (UMA) and the University of Calabria (UNC)).A total number of 12 LVGMU devices are foreseen to be installed and operated during the demonstration phase of the project.Some devices have already been installed, and as planned, the remaining devices will be installed within the 2023 Q1 period.

TEXNOREYMETA Project (Greek National Funded)
The design of the OpenEdgePMU system has been utilized for the development of a secondary substation monitoring (STM) solution for a research and development project [57].The objectives of the project were (a) the detection of non-technical losses in distribution grids and (b) the predictive maintenance of medium-voltage/low-voltage distribution transformers.The firmware of the OpenEdgePMU was modified in order to support:

•
Real-time power quality analysis based on EN50160; • Energy meter for secondary distribution substation; • Phasor measurement unit.
The hardware design of the OpenEdgePMU system was adopted, and certain additional automation features were added, such as low sampling frequency measurements regarding the transformer health (temperature, vibrations, magnetic field, etc.).A mechanical enclosure similar to the eBalance+ project was used.The system has been installed in three (3) secondary power distribution substation in the Cyprus grid (operated by the Electricity Authority of Cyprus), Figure 14.
The combination of the PMU with a power quality analysis (based on EN50160) is an ideal case to demonstrate the edge processing benefits.More specifically, the PMU con- Within the context of the eBalance+ project, two different pilot demo sites are foreseen: the University of Malaga (UMA) and the University of Calabria (UNC)).A total number of 12 LVGMU devices are foreseen to be installed and operated during the demonstration phase of the project.Some devices have already been installed, and as planned, the remaining devices will be installed within the 2023 Q1 period.

TEXNOREYMETA Project (Greek National Funded)
The design of the OpenEdgePMU system has been utilized for the development of a secondary substation monitoring (STM) solution for a research and development project [57].The objectives of the project were (a) the detection of non-technical losses in distribution grids and (b) the predictive maintenance of medium-voltage/low-voltage distribution transformers.The firmware of the OpenEdgePMU was modified in order to support:

•
Real-time power quality analysis based on EN50160; • Energy meter for secondary distribution substation; • Phasor measurement unit.
The hardware design of the OpenEdgePMU system was adopted, and certain additional automation features were added, such as low sampling frequency measurements regarding the transformer health (temperature, vibrations, magnetic field, etc.).A mechanical enclosure similar to the eBalance+ project was used.The system has been installed in three (3) secondary power distribution substation in the Cyprus grid (operated by the Electricity Authority of Cyprus), Figure 14.
Energies 2023, 16, 2756 19 of 30 the event, however this is configurable) and each data page has 1363 samples of six channels, so the event related data generated every day is: 50 events × 10 pages/event × 1363 samples/page × 6 channels × 2 bytes/channel = 8.2 Mbytes/day which is three orders of magnitude lower than transferring the total amount of data generated.Today, the system is in pilot operation and detailed results will be published soon.

Power Flow (PF)
The power flow model of a power system is built using the relevant network, load, and generation data.Outputs of the power flow model include voltages at different buses, line flows in the network, and system losses.These outputs are obtained by solving nodal power balance equations [58].Since these equations are nonlinear, the Newton-Raphson technique is employed to solve this problem.By running PF, useful information about the voltages (magnitude and angle) for a given load, generation, and grid condition can be obtained at any time, and therefore appropriate actions can be taken to avoid surges and overloads.The power flow component is a wrapper for the python PandaPower library.PandaPower is extensively used for power system modeling, analysis, and optimization [59][60][61][62] as it presents a lot of advantageous features.PandaPower is implemented in Python, guaranteeing free availability and flexible expansion with other open-source libraries.The OpenEdgePMU system, and more specifically the edge processing module has been used to execute the above power flow approach for several distribution grid topologies, and the maximum execution time was limited to a few seconds (even milliseconds in certain low complexity grids).

Optimal Power Flow (OPF)
The optimal power flow (OPF) problem refers to the actions that should be taken to satisfy the power requirements of each consumption node in the most economical way, while obeying operational constraints [63].During this task, the control variables (reactive power of PV inverter) are optimized, and then the control actions are applied within an iterative loop.By solving OPF, the instant optimal parameters of each generation bus and controllable bus of the grid are determined.The OPF problem, in its generic form, is a large-scale, nonconvex, mixed integer nonlinear programming (MINLP) optimization problem, belonging to the NP-hard class.This is partly due to the nature of the design The combination of the PMU with a power quality analysis (based on EN50160) is an ideal case to demonstrate the edge processing benefits.More specifically, the PMU continuously and uninterruptedly acquires the voltage and current phasors and saves the data to the local database of the DSP module.Using 10 kHz sampling frequency, the size of the data generated every day is: 10,000 samples/s × 6 channels × 2 bytes/channel × 86,400 s/day = 10.4GBytes/day Apparently, this size of data is very difficult to send to the backend even using 5G communication modems.Instead, the EN50160 power analysis algorithms are executed in real time in the DSP module and are responsible to mark the segments of data (data blocks) that a power quality event has detected (e.g., voltage sag, harmonics, voltage dip, etc.).Only the interesting blocks are selected to be automatically transmitted in the backend.For instance, the average daily events of each one of the three installations in Cyprus is around 50 events.The backend retries 10 data pages (five before and five after the event, however this is configurable) and each data page has 1363 samples of six channels, so the event related data generated every day is: 50 events × 10 pages/event × 1363 samples/page × 6 channels × 2 bytes/channel = 8.2 Mbytes/day which is three orders of magnitude lower than transferring the total amount of data generated.Today, the system is in pilot operation and detailed results will be published soon.The power flow model of a power system is built using the relevant network, load, and generation data.Outputs of the power flow model include voltages at different buses, line flows in the network, and system losses.These outputs are obtained by solving nodal power balance equations [58].Since these equations are nonlinear, the Newton-Raphson technique is employed to solve this problem.By running PF, useful information about the voltages (magnitude and angle) for a given load, generation, and grid condition can be obtained at any time, and therefore appropriate actions can be taken to avoid surges and overloads.The power flow component is a wrapper for the python PandaPower library.PandaPower is extensively used for power system modeling, analysis, and optimization [59][60][61][62] as it presents a lot of advantageous features.PandaPower is implemented in Python, guaranteeing free availability and flexible expansion with other open-source libraries.The OpenEdgePMU system, and more specifically the edge processing module has been used to execute the above power flow approach for several distribution grid topologies, and the maximum execution time was limited to a few seconds (even milliseconds in certain low complexity grids).

Optimal Power Flow (OPF)
The optimal power flow (OPF) problem refers to the actions that should be taken to satisfy the power requirements of each consumption node in the most economical way, while obeying operational constraints [63].During this task, the control variables (reactive power of PV inverter) are optimized, and then the control actions are applied within an iterative loop.By solving OPF, the instant optimal parameters of each generation bus and controllable bus of the grid are determined.The OPF problem, in its generic form, is a largescale, nonconvex, mixed integer nonlinear programming (MINLP) optimization problem, belonging to the NP-hard class.This is partly due to the nature of the design variables that may be discrete, and to the non-continuity, non-differentiability, and non-convexity of the objective function.The optimization problem in hand can be described as: The vector x contains the state variables of the power grid, namely the active power P i , voltage V i , and phase δ i of the nodes, while vector u contains the control variables, which can be the active power of generation nodes P G i , reactive power injections Q G i , transformers tap position T ik , phase shifter position ϕ ik , and capacitor bank switch position Q c ik .The underlying constraints of the OPF problem are derived from the physical limits of the system and Kirchhoff's laws [64] and are listed below: • Generation limits of generation nodes • Tap limits on ik branch • Loading limit of ik branch • External grid active and reactive power injection limits Energies 2023, 16, 2756 20 of 29

•
Upper and lower limits of the curtailed power of each RES unit • Active and reactive power balance at i node where P L i and Q L i are the active and reactive load, and P i and Q i are the incoming or outgoing active and reactive power.Similar to PF, OPF is also executed with the help of PandaPower.The inputs of the algorithm consist of (a) the grid's topology and (b) the real-time state of the grid.The desired target objective must also be determined which may differ among: • real power losses where P LOSS is the total active power losses in the distribution network, m is the number of branches, R ik is the resistance in the branch ik, and I ik is the current in the branch ik.

•
voltage deviation minimization where V sp i is the prespecified reference voltage value at i-th load bus, which is usually set at the value of 1.0 p.u. and N is the number of load buses, where CF i is a weight factor of the curtailed power of the i-th RES unit, with ∑ M i=1 CF i = 1.Regarding the optimization algorithm, several metaheuristic methodologies have been implemented, namely particle swarm optimization (PSO) [65] and genetic algorithms (GA) [66], while more can be easily integrated.The effectiveness and superiority of metaheuristics for solving the OPF problem have been thoroughly researched and demonstrated [67][68][69].After the execution of the algorithm, two types of outputs are produced.The first concerns commanding and controlling the underlying elements of the power grid, specifically, for the RES elements.The second concerns a series of KPIs that define the performance of the algorithm.The architecture of the implemented algorithm is illustrated in Figure 15.The OPF approach has been realized and executed in the OpenEdgePMU system using the edge processing module.The results of OPF executions for the benchmark grid IEEE123 are presented in Table 1.As this section serves as an overview of the capabilities of OEPMU application, the results for real power losses minimization are only included, demonstrating the initial and optimized values.Looking at these values, it is obvious that the proposed Volt/Var algorithm achieves its goals.
The architecture of the implemented algorithm is illustrated in Figure 15.The OPF approach has been realized and executed in the OpenEdgePMU system, using the edge processing module.The results of OPF executions for the benchmark grid IEEE123 are presented in Table 1.As this section serves as an overview of the OEPMU application capabilities, the results for real power loss minimization are only included, demonstrating the initial and optimized values.Looking at these values, it is obvious that the proposed Volt/Var algorithm achieves its goals.
view of the capabilities of OEPMU application, the results for real power losses minimization are only included, demonstrating the initial and optimized values.Looking at these values, it is obvious that the proposed Volt/Var algorithm achieves its goals.
The architecture of the implemented algorithm is illustrated in Figure 15.The OPF approach has been realized and executed in the OpenEdgePMU system, using the edge processing module.The results of OPF executions for the benchmark grid IEEE123 are presented in Table 1.As this section serves as an overview of the OEPMU application capabilities, the results for real power loss minimization are only included, demonstrating the initial and optimized values.Looking at these values, it is obvious that the proposed Volt/Var algorithm achieves its goals.An important metric while trying to optimize an objective is always the speed of convergence.The convergence of the fitness function values versus the generations of the PSO algorithm is depicted in Figure 16.An important metric while trying to optimize an objective is always the speed of convergence.The convergence of the fitness function values versus the generations of the PSO algorithm is depicted in Figure 16.

Load Prediction Based on AI
Electric load forecasting is, from a mathematical modeling point of view, a regression problem where the future value of the load demand has to be estimated by having a set of past values available.The field of computational intelligence, and more specifically, the field of machine learning (ML) [70] has proven to be an invaluable resource that provides a multitude of approaches to solve the aforementioned problem [71].A number of the most widely used methodologies, namely linear regression [72,73], support vector regression (SVR) [74,75], regression trees [76], random forests [77], MLP neural networks [78,79], and LSTM neural networks [80] have been developed in Python and wrapped in a single algorithmic framework that supports the following operations: data preprocessing, model

Load Prediction Based on AI
Electric load forecasting is, from a mathematical modeling point of view, a regression problem where the future value of the load demand has to be estimated by having a set of past values available.The field of computational intelligence, and more specifically, the field of machine learning (ML) [70] has proven to be an invaluable resource that provides a multitude of approaches to solve the aforementioned problem [71].A number of the most widely used methodologies, namely linear regression [72,73], support vector regression (SVR) [74,75], regression trees [76], random forests [77], MLP neural networks [78,79], and LSTM neural networks [80] have been developed in Python and wrapped in a single algorithmic framework that supports the following operations: data preprocessing, model training, model evaluation, extraction of the desired dataset, and results acquisition of an evaluated model.In a future version of the predictive framework, it is foreseen to add additional methodologies such as sparse coding [81] and convolutional neural networks [82].It is useful to note that the integration of new models follows a standard and straightforward formalism.At the same time, the possibility of simulations is provided under different configurations, such as training scenario, evaluation scenario, prediction horizon, and reference year.Due to the high computational cost required to train the models, this process takes place at a central operational point (cloud application for power forecasting backend support), while the generation of predictions from the already trained models are performed seamlessly by the OpenEdgePMU system, and specifically using the edge processing module.Providing reliable and accurate load forecasts is an essential complementary feature of any modern power system, participating in a multitude of tasks such as scheduling generation sources [83], energy price forecasting [84], and secure operation [85].The performances of some standard ML methods are evaluated based on the values of the MSE and R 2 indices obtained for forecasts with different horizons and different execution scenarios for each horizon are shown in Table 2.The execution times for the load forecasting models in the OpenEdgePMU system are in the range of a few seconds.The explanation of the simulation scenarios is set out below: sc001, weekdays of one year; sc011, daylight hours of one year; sc013, daylight hours of weekdays only of one year; sc034, spring days of one year; sc035, summer days of one year.

Islanding
Intentional islanding is the purposeful sectionalization of the utility system during widespread disturbances to create power "islands".These islands can be designed to maintain a continuous supply of power during disturbances of the main distribution system.The distributed energy resources can then supply the load power demand of the islands created until reconnection with the main utility system occurs.These disturbances refer to cascading failures, of which the massive economic and social impacts have motivated a great deal of research effort on studying the vulnerability of power grids [86,87].The aim of intentional islanding within the proposed approach is the resiliency of the network in terms of frequency balancing and continuous demand supply [88,89].This optimization task is conceptualized by executing optimal power flow for several islanding setups of the network.The problem formulation includes the objective of load shedding and switches cost minimization.The design variables comprise the setpoints of DERs, while the constraints of the intentional islanding problem coincide with those of OPF.
The execution of the algorithm implemented in Python can be done entirely in the field, in the edge board of the OpenEdgePMU system.First, a configuration must be defined that contains the network's topology, the optimization objectives, the type and point of failure (e.g., line tripping) that enables the islanding, as well as all the possible islanding setups.Then, the current state of each island is needed as input to the OPF algorithm which has already been described.The aim of this process is to extract the islanding setup with minimum cost, depending on the objective target set when OPF is executed.The application of the selected islanding setup is carried out by movements of smart switches that control the separation of the islands from the grid.It is also worth noting that communication between OpenEdgePMU nodes via 5G interface greatly reduces latency.Finally, the load level of the islands is monitored continuously, and load shedding is applied in the case of an imbalance.A test case is presented to validate the correct and efficient operation of the islanding algorithm carrying out the following steps: 1.
Assume that failures are detected on Lines 5, 6, 12, and 16 of the grid topology shown in Figure 17.
For each islanding setup, OPF is conducted, and the respective objective value is obtained, as shown in Table 3. Islanding setup (a) is selected as it achieves the minimum objective value.6.
Islanding setup (a) is applied, and then load shedding is conducted to maintain power supply to as many consumers as possible, as presented in Table 4.In this case, no load shedding is taking place, as the required demand does not exceed the available energy produced.The islanding algorithm is completed by solving the OPF problem for each island to ensure that power losses are minimized.tained, as shown in Table 3. Islanding setup (a) is selected as it achieves the minimum objective value.6. Islanding setup (a) is applied, and then load shedding is conducted to maintain power supply to as many consumers as possible, as presented in Table 4.In this case, no load shedding is taking place, as the required demand does not exceed the available energy produced.The islanding algorithm is completed by solving the OPF problem for each island to ensure that power losses are minimized.Cascading failures comprise a critical challenge in supply networks such as electric power grids, as they can lead to major economical and functional issues.The above supervision/control scheme can be used to address cascading failures and to increase the network resilience and stability [90,91].

Discussion and Remarks
Regarding hardware implementation of the system, we demonstrated that the OpenEdgePMU system has a modular realization, compact size, and very low cost, taking into consideration the processing power available for edge processing (DSP + MCU).By providing open-source licensing for both hardware and software, we encourage tailoring, modifications, and use of the platform in future smart grid projects.
Targeting to encourage adoption of the platform in this direction, we presented two funded projects, that have adopted and tailored the design according to projects' requirements.The scope was just to outline the application cases and demonstrate the suitability of the OpenEdgePMU system in similar research and innovation actions.Further details regarding these projects will be published in the future, as, currently, both projects are in pilot execution phases.In similar project circumstances, researchers would have to tailor the main board of the system and provide potential extensions that are required specifically for a project's objectives and needs.In contrast, the DSP module and the edge processing module are ready to be used without any modifications; thus, significantly reducing required project labor, cost, and risks.
Finally, we have presented selected algorithms and applications able to be executed according to the edge processing approach.Again, the scope of the description was to provide an outline of the application cases and to demonstrate the applicability of the OpenEdgePMU system.All application cases presented are related to future resilient smart grids where the major requirements are to analyze critical situations inside the grid, make fast decisions, and execute decisions in a fully automated manner; thus, the overall processing, communication, and actions' timing latency are minimized.

Figure 1 .
Figure 1.High-level architecture of the OpenEdgePMU system.Figure 1. High-level architecture of the OpenEdgePMU system.

Figure 1 .
Figure 1.High-level architecture of the OpenEdgePMU system.Figure 1. High-level architecture of the OpenEdgePMU system.

Figure 2 .
Figure 2. High-level architecture of the DSP module.

Figure 2 .
Figure 2. High-level architecture of the DSP module.

Figure 3 .
Figure 3. Layered architecture of the DSP module firmware.The core functionality of the DSP module is depicted in Figure 4.The hard real-time operation is based on two interrupt service routines (ISR): one for TIMER-0 which is responsible for signals' sampling, and another for the GPS acquisition timing resynch.The ISR TIMER-0 calls the sampling function, which is responsible for transferring the ready sampled data from the ADC, via the McSPI peripheral.The clock speed for the transfer is 20 MHz, thus the time required for the total transfer of six channels with 16-bits for each channel is around 100 clock periods, i.e., 100 × 50 ns = 5 µs.Before doing the actual transfer, it signals the ADC to start a new signal sampling task.This can be handled by the ADC in parallel with the transfer of the previous sampled data to the DSP via the McSPI interface.The acquired data are stored into an intermediate memory buffer (Block_MEASURE-MENT) as depicted in Algorithm 1.This memory buffer is separated into two identical parts.Each part contains the date and time of the first sample with millisecond accuracy, an array of 1363 samples for each one of the six channels, and finally a 32-bit checksum of the contained data into this structure (Figure4).When the ISR-TMR0 completes filling one Block_Measurement buffer, it continues to the next one.

Figure 3 .
Figure 3. Layered architecture of the DSP module firmware.The core functionality of the DSP module is depicted in Figure 4.The hard realtime operation is based on two interrupt service routines (ISR): one for TIMER-0 which is responsible for signals' sampling, and another for the GPS acquisition timing resynch.The ISR TIMER-0 calls the sampling function, which is responsible for transferring the ready sampled data from the ADC, via the McSPI peripheral.The clock speed for the transfer is 20 MHz, thus the time required for the total transfer of six channels with 16-bits for each channel is around 100 clock periods, i.e., 100 × 50 ns = 5 µs.Before doing the actual transfer, it signals the ADC to start a new signal sampling task.This can be handled by the ADC in parallel with the transfer of the previous sampled data to the DSP via the McSPI interface.The acquired data are stored into an intermediate memory buffer (Block_MEASUREMENT) as depicted in Algorithm 1.This memory buffer is separated into two identical parts.Each part contains the date and time of the first sample with millisecond accuracy, an array of 1363 samples for each one of the six channels, and finally a 32-bit checksum of the contained data into this structure (Figure4).When the ISR-TMR0 completes filling one Block_Measurement buffer, it continues to the next one.Energies 2023, 16, 2756 11 of 30

Figure 5 .
Figure 5. High-level architecture of the edge processing module.

Figure 5 .
Figure 5. High-level architecture of the edge processing module.

Figure 6 .
Figure 6.High-level architecture of the edge processing module software stack.

•
Command and control of the PMU, including commands for the DSP module; • Acquisition of data generated by the DSP module; • Local database; • Communication with backend/frontend applications; • Communication with other OpenEdgePMUs; • Execution of artificial intelligence functionalities.

Figure 6 .
Figure 6.High-level architecture of the edge processing module software stack.

Figure 7 .
Figure 7. High-level architecture of the edge processing module application.

Figure 7 .
Figure 7. High-level architecture of the edge processing module application.

Figure 8 .
Figure 8. High−level architecture of the power supply module.Figure 8. High−level architecture of the power supply module.

Figure 8 .
Figure 8. High−level architecture of the power supply module.Figure 8. High−level architecture of the power supply module.

Figure 9 .
Figure 9. Implementation of the DSP module board, top side.

Figure 9 .
Figure 9. Implementation of the DSP module board, top side.

Figure 10 .
Figure 10.Implementation of the edge processing board.

Figure 11 .
Figure 11.The Beaglebone Black can be attached as the edge processing module.

Figure 10 .
Figure 10.Implementation of the edge processing board.

Figure 10 .
Figure 10.Implementation of the edge processing board.

Figure 11 .
Figure 11.The Beaglebone Black can be attached as the edge processing module.

Figure 11 .
Figure 11.The Beaglebone Black can be attached as the edge processing module.

Figure 12 .
Figure 12.Implementation of the main board.Left: The main board.Right: The main board along with mounted DSP and EDGE processing units.

Figure 12 .
Figure 12.Implementation of the main board.Left: The main board.Right: The main board along with mounted DSP and EDGE processing units.

Figure 13 .
Figure 13.The LVGMU realization for the eBalance+ project, based on the design of the OpenEdgePMU system.

Figure 13 .
Figure 13.The LVGMU realization for the eBalance+ project, based on the design of the OpenEdgePMU system.

Figure 14 .
Figure 14.The STM realization for the TEXNOREYMETA project based on the OpenEdgePMU system.

Figure 14 .
Figure 14.The STM realization for the TEXNOREYMETA project based on the OpenEdgePMU system.

Figure 15 .
Figure 15.High-level architecture of the OPF framework implemented by the OpenEdgePMU system.Figure 15.High-level architecture of the OPF framework implemented by the OpenEdgePMU system.

Figure 15 .
Figure 15.High-level architecture of the OPF framework implemented by the OpenEdgePMU system.Figure 15.High-level architecture of the OPF framework implemented by the OpenEdgePMU system.

Figure 16 .
Figure 16.Fitness function value versus number of generations.

Figure 16 .
Figure 16.Fitness function value versus number of generations.
Ethernet to provide an Ethernet interface to connect to the local network.
Energies 2023, 16, 2756•I2C to interface with the on-board EEPROM memory; • UART to interface with the PMU and other external modules; • depicts the top side of the edge board.The edge board has:

Table 1 .
OPF results subject to real power loss minimization.

Table 1 .
OPF results subject to real power loss minimization.

Table 2 .
Load forecasting results for multiple time horizons and ML methodologies.

Table 3 .
Optimal power flow solution results.

Table 4 .
Optimal power flow solution detailed results.