High Step-Up Three-Level Soft Switching DC-DC Converter for Photovoltaic Generation Systems

: In this paper, a high step-up three-level DC–DC converter with a symmetric structure for PV application is proposed. The converter has high voltage gain. This is achieved due to the use of two high step-up cells and two resonant paths in its structure. The converter has low input current ripples and the voltage stress across all switches is equal to half of the output voltage. The proposed converter uses simple pulse–width modulation (PWM) to trigger the switches. Hence, the proposed converter beneﬁts from a simple structure and control circuit. All semiconductor devices are turned on/off under ZCS conditions. Thus, the switching losses are decreased, and the total efﬁciency is increased. The converter is implemented and tested through a laboratory prototype. The experimental results verify the theoretical analysis.


Introduction
The demand for photovoltaic (PV) power generation has increased significantly in recent years.Many reasons are effective to reach this aim, such as the reduction of PV cost and increment of PV power generation capacity.In addition, global warming and environmental pollution are other important reasons that have forced different countries to use renewable energy sources, especially PV to generate electricity instead of using fossil fuels [1,2].In a grid-connected PV system, the voltage level, which is generated by PV arrays, cannot be used to feed the grid-connected side.In fact, the low input voltage should be boosted with high voltage gain.Hence, high step-up DC-DC converters are presented to use as a liaison between low-voltage PV arrays and high-voltage gridconnected sides, as shown in Figure 1 [3,4].On the other hand, soft switching techniques can be used in the interface circuit to increase the converter efficiency, as well as to reduce the cost and dissipation of the system.Amongst the fundamental techniques for soft switching, one can name zero current switching (ZCS) and zero voltage switching (ZVS) [5].Undoubtedly, numerous high step-up DC-DC converters achieved with various techniques are presented in the literature.Using transformers [6], stacked converters [7], switched capacitors [8], switched inductors [9], coupled inductors [10], input-parallel-output-series connections [11], and cascaded structures [12] is a well known techniques for achieving high voltage gain.Most of the mentioned techniques have a complex structure with a high number of elements [13].In addition, they usually suffer from high voltage stress across semiconductor devices.Three-level DC-DC converters (TLDC) have extensively decreased the semiconductor voltage stress, down to the half of the output voltage.As a result, TLDCs are very attractive to use in high output voltage applications.A high step-up soft switched TLDC with an active clamp has been presented in [14].Though the voltage stress had been lowered, the use of four power switches is explicitly associated with a more complex Energies 2023, 16, 41 2 of 22 control circuit.A high step-up TLDC has been introduced in [15], which has utilised a voltage doubler circuit and coupled inductor in its structure.The converter only uses two switches in its topology.However, the hard switching was associated with lower efficiency, as expected.In [16], a hybrid high step-up TLDC for PV applications has been introduced.The topology is derived from a diode-clamped three-level inverter.Moreover, it uses only one inductor in its structure.Besides, a high step-up TLDC neutral-point-clamped has been presented in [17].Unfortunately, both presented converters in [16,17] have complex structures due to the use of four switches.High step-up TLDC with active clamp is presented in [18].The converter efficiency is high due to the soft switching operation.The converter has a complex structure.A high number of passive elements, such as coupled inductors, switched capacitors, clamp capacitors, and output capacitors, are used in the converter.A double-input three-level topology is proposed in [19].The structure consists of buck-boost half-bridge modules, which can feed the loads when one of the input sources have been failed.The converter uses an active clamp to create soft switching, which leads to high efficiency.Moreover, a cascaded arrangement is used to decrease the voltage stress across the power switches.A dual-output three-level quadratic boost topology is proposed in [20].Quadratic static gain is achieved with a low number of elements.The input and output have connection points, while their polarity is opposite.The dual-output voltages are balanced by using only two power devices.[21] proposes a three-level power converter, where the higher number of levels means the higher voltage gain ratio.A high step-up feature is achieved by using a three-winding coupled inductor in its structure.All switches are turned on under ZCS condition and the diodes are turned off naturally.In this way, the converter does not suffer from the reverse recovery problem, and its efficiency increases significantly.By using the advantages of interleaved and three-level structures, a boost converter has been proposed in [22], where the inputs were connected in parallel, and the outputs were put in series.The converter can operate with an extensive input voltage range properly.High step-up capability is achieved by applying two capacitors at the output side.Low input current ripple and low voltage stress across semiconductor devices (V O /2) are the main advantages of the proposed converter.A single-switch boost converter is proposed in [23], which uses diode-capacitor modules in its structure.The converter achieves high voltage gain with a low-duty cycle.Low voltage stress across active components (V O /n) and simple structure are the main advantages of the proposed converter.A boost three-level converter is proposed in [24].It uses a diode rectification quasi-Z source structure in the topology.The converter has common ground between the input and the load, low voltage stress across semiconductor devices, and wide voltage gain.Quasi Z-source is used to clamp the flying-capacitor voltage to V O /2.ZVS condition is achieved for synchronous rectification switch, which leads to high efficiency.A non-isolated converter with high voltage gain is proposed in [25].High step-up operation is obtained by using switched capacitor and a switched inductor.The proposed DC-DC converter has high safety conditions due to the use of common ground between the input and the load.Moreover, the voltage stress on the semiconductors is lowered, i.e., equivalent to half of the output (V O /2).This paper deals with introducing a high step-up TLDC with a symmetric configuration.The converter has high voltage gain due to the use of two high step-up cells and two resonant paths in its structure.The energy stored in the cells transfers to the output when the switches are turned off.Moreover, the energy stored in the resonant elements, the input filter, the input source, and high step-up cells is transferred to the output.The above two factors increase the voltage gain as much as possible.Input filter inductors L1 and L2 cause the converter has a low input ripple current.The voltage stress across all switches is equal to half of the output voltage.In addition, the voltage stress across all diodes is also less than or equal to VO/2.This characteristic leads the converter to be used in many high voltage, high power applications.The resonant cells in the proposed converter are positioned in such a way that the peak current of the resonant inductors does not pass through the switch.As a result, the switches have low current stress.A symmetric structure leads to simplify the converter design and reduces its complexity.The proposed converter uses simple PWM to trigger the switches.Only two switches related to TLDC are used in the converter.The gating signals of the switches have a phase difference of 180 degrees with respect to each other.As a result, the converter does not have any auxiliary switch.Hence, the proposed converter has a simple structure and control circuit.All semiconductor devices are turned on/off under ZCS condition.Thus, the switching losses are decreased, and the total efficiency is increased.The converter does not have any coupled inductor to increase the voltage gain.High step-up operation is based on the proper power transfer to the output.
The following sections are ordered as follows.Circuit structure and its characteristics are described in Section 2. Consideration of operating modes is analyzed in Section 3. The equations, obtained values, and types of components are explained in Section 4. Section 5 presents the simulation and experimental results of the prototype.Ultimately, Section 6 concludes the findings.

Circuit Structure and Its Characteristics
The proposed converter is shown in Figure 2. Inductors L1 and L2 act as the input filter inductors.There are two voltage step-up cells with linear operation that are located symmetrically.These cells include: inductors L3 and L4, capacitors C1 and C2, and diodes D1 and D2.Furthermore, the converter has two resonant cells which consist of inductors L5, L6 and capacitors C3, C4.The mentioned cells are also positioned symmetrically.Two series inductors L7 and L8 tune the current that flows through the linear and resonant cells.Output diodes D3 and D4 are used to transfer the power to the load.Capacitors CO1 and CO2 are usually used in conventional TLDCs.It should be noted that the voltage across each capacitor is equal to half of the output voltage.The theoretical waveforms are shown in Figure 3.This paper deals with introducing a high step-up TLDC with a symmetric configuration.The converter has high voltage gain due to the use of two high step-up cells and two resonant paths in its structure.The energy stored in the cells transfers to the output when the switches are turned off.Moreover, the energy stored in the resonant elements, the input filter, the input source, and high step-up cells is transferred to the output.The above two factors increase the voltage gain as much as possible.Input filter inductors L 1 and L 2 cause the converter has a low input ripple current.The voltage stress across all switches is equal to half of the output voltage.In addition, the voltage stress across all diodes is also less than or equal to V O /2.This characteristic leads the converter to be used in many high voltage, high power applications.The resonant cells in the proposed converter are positioned in such a way that the peak current of the resonant inductors does not pass through the switch.As a result, the switches have low current stress.A symmetric structure leads to simplify the converter design and reduces its complexity.The proposed converter uses simple PWM to trigger the switches.Only two switches related to TLDC are used in the converter.The gating signals of the switches have a phase difference of 180 degrees with respect to each other.As a result, the converter does not have any auxiliary switch.Hence, the proposed converter has a simple structure and control circuit.All semiconductor devices are turned on/off under ZCS condition.Thus, the switching losses are decreased, and the total efficiency is increased.The converter does not have any coupled inductor to increase the voltage gain.High step-up operation is based on the proper power transfer to the output.
The following sections are ordered as follows.Circuit structure and its characteristics are described in Section 2. Consideration of operating modes is analyzed in Section 3. The equations, obtained values, and types of components are explained in Section 4. Section 5 presents the simulation and experimental results of the prototype.Ultimately, Section 6 concludes the findings.

Circuit Structure and Its Characteristics
The proposed converter is shown in Figure 2. Inductors L 1 and L 2 act as the input filter inductors.There are two voltage step-up cells with linear operation that are located symmetrically.These cells include: inductors L 3 and L 4 , capacitors C 1 and C 2 , and diodes D 1 and D 2 .Furthermore, the converter has two resonant cells which consist of inductors L 5 , L 6 and capacitors C 3 , C 4 .The mentioned cells are also positioned symmetrically.Two series inductors L 7 and L 8 tune the current that flows through the linear and resonant cells.Output diodes D 3 and D 4 are used to transfer the power to the load.Capacitors C O1 and C O2 are usually used in conventional TLDCs.It should be noted that the voltage across each capacitor is equal to half of the output voltage.The theoretical waveforms are shown in Figure 3.

Consideration of Operating Modes
Interval 1: (t0-t1) [see Figure 4a]: This mode starts when switch M2 is turned on at t0, while switch M1 is also turned on.Since switch M2 is connected in series with inductor L8,

Consideration of Operating Modes
Interval 1: (t0-t1) [see Figure 4a]: This mode starts when switch M2 is turned on at t0, while switch M1 is also turned on.Since switch M2 is connected in series with inductor L8,

Consideration of Operating Modes
Interval 1: (t 0 -t 1 ) [see Figure 4a]: This mode starts when switch M 2 is turned on at t 0 , while switch M 1 is also turned on.Since switch M 2 is connected in series with inductor L 8, which has zero current at t 0 , the switch is turned on under ZCS condition.Hence, diode D 4 is also switched off at zero current.On the other hand, diode D 2 is switched on under ZCS condition to flow inductor current I L8 .
Energies 2023, 15, x FOR PEER REVIEW 8 of 25 Similar to mode 4, the resonance between inductors L6, L8, and capacitor C6 through diode D2 and switch M2 continues.On the other hand, the energy stored in inductor L3 is transferred to capacitor C1, while the energy stored in capacitor C2 is transmitted to inductor L4.This mode terminates when switch M2 is turned off at t5.

Small Signal Modelling
Small signal modeling is used to analyze the stability of a closed-loop system.This method is used by a state space average model.In this model, state space variables are capacitor voltage and inductor current.By considering the converter operating in CCM, state space equations can be calculated as follows.
Since the proposed converter has a symmetric structure, V L1 = −V L2 , V C1 = V C2 , and During this mode, a resonance starts between capacitor C 3 and inductor L 5 .In this condition, the capacitor voltage decreases, and the inductor current increases in a resonance manner.
Furthermore, another resonance occurs between capacitor C 4 and inductor L 6 .The resonance increases V C4 and decreases I L6 . ) During this mode, diode D 1 is switched on to transfer the energy stored in the input filter inductors to series inductors (L 7 and L 8 ).At the end of this mode, inductor current I L5 reaches I in .
Besides, the following equations are obtained for mode 1.
In fact, mode 1 ends when switch M 1 is turned off at t 1 .
Interval 2: (t 1 -t 2 ) [see Figure 4b]: This mode starts when switch M 1 is turned off at t 1 while switch M 2 is still turned on.When switch M 1 is turned off, diode D 3 is switched on and conducts the current that flows through inductor L 7 .During this mode, diodes D 1 and D 2 are switched on as same as the former mode.A resonance starts between C 3 , L 5 , L 7 , and C 1 in this mode.Hence, inductor current I L5 and capacitor voltage V C3 decrease in Energies 2023, 16, 41 7 of 22 a resonance manner.At the end of this mode, the inductor current reaches zero, and the capacitor voltage will be equal to − The resonance between C 4 and L 6 continues as same as mode 1.
Interval 3: (t 2 -t 3 ) [see Figure 4c]: This mode starts when inductor current I L5 reaches zero at t 2 .As a result, the inductor current will be reversed during this mode.The current that flows through inductor L 7 decreases and reaches zero at the end of this mode.In addition, diodes D 1 and D 3 are switched off under ZCS condition at t 3 .During this mode, the resonance continues between C 4 and L 6 .Finally, inductor current I L6 reaches zero, and the voltage across capacitor C 4 reaches its peak value.
During this mode, inductor current I L8 increases.Interval 4: (t 3 -t 4 ) [see Figure 4d]: This mode starts when I L7 reaches zero and diodes D 1 and D 3 are switched off under ZCS condition.Besides, I L3 also equals zero at t 3 .Consequently, the energies stored in the input source, input filter inductors, capacitor C 1 , and inductor L 5 are transferred to the output and capacitor C 3 .During this mode, the resonance between capacitor C 3 and inductor L 5 stops.On the other hand, inductor current I L6 will be reversed.As a result, a new resonance occurs among inductors L 6 , L 8 , and capacitor C 4 through diode D 2 and switch M 2 .Hence, I L6 increases based on the direction, which is shown in Figure 4d. ) This mode ends when switch M 1 is turned on at t 4 .
Interval 5: (t 4 -t 5 ) [see Figure 4e]: This mode starts when switch M 1 is turned on at t 4 while switch M 2 is still turned on.As same as the former mode, diodes D 3 and D 4 are reverse biased.When switch M 1 is turned on, the current that flows through inductor L 7 increases from zero.Thus, the switch is turned on under ZCS condition at t 4 .
During this mode, a resonance starts between capacitor C 3 and inductor L 5 .In this condition, the inductor current is reduced, and the capacitor voltage rises.
Similar to mode 4, the resonance between inductors L 6 , L 8 , and capacitor C 6 through diode D 2 and switch M 2 continues.On the other hand, the energy stored in inductor L 3 is transferred to capacitor C 1 , while the energy stored in capacitor C 2 is transmitted to inductor L 4 .This mode terminates when switch M 2 is turned off at t 5 .

Small Signal Modelling
Small signal modeling is used to analyze the stability of a closed-loop system.This method is used by a state space average model.In this model, state space variables are capacitor voltage and inductor current.By considering the converter operating in CCM, state space equations can be calculated as follows.
x(t) = A j x(t) + Bu(t) (41) where, x(t) is the state space variable, x(t) is derivative of x(t), and A, B, C and D, respectively, denote the matrices of the state, input, output and input-output.Besides, j is the number of operation modes in the proposed converter (j = 1, 2, . . .,5).Due to symmetric structure of the proposed converter, state variables are defined as follows.
Kirchhoff's laws in Mode 1 leads to the following equations.
The following equations are associated with Mode 3.
Applying Kirchhoff's laws to Mode 4 yields: Eventually, by inspection, the associated equations with Mode 5 are as follows.
A ave , B ave , and C ave can be determined by state space averaging as follows.
Energies 2023, 16, 41 The Laplace transform can be applied to the matrices above to derive the open-loop signal-to-output transfer functions.
Open loop conversion function is obtained by substituting (80) and ( 82) into (83).Zeros and poles of the conversion function at the continuous time state space can be reached by using Gzpk command in MATLAB software.Obtained zeros and poles lie within the left-half of the s-plane.As a result, the open loop conversion function is stable.

Design Considerations
This part explains the design consideration of the proposed converter.The essential equations to design different parts are presented.Furthermore, the selection of elements based on the design guidelines and obtained values are described in detail.It should be noted that the proposed converter has a symmetric structure.In this condition, the elements in the symmetric parts have the same values.

Design of Input Filter Inductors L 1 , L 2
The calculation of the input filter inductors in the proposed converter is similar to a conventional boost converter.Since L 1 and L 2 have equal inductances and they are connected in series with each other, the following equation is obtained.
In (84), D k indicates the on-time duration of both switches M 1 and M 2 .∆I L1 represents the half value of the current ripple that flows through input inductors.It should be designed in such a way that the proposed converter operates in CCM.

Design of Output Capacitors C o1 , C o2
Since the proposed topology is a three-level converter that has a symmetric structure, C O1 and C O2 are equal.These capacitors act as an output filter.
The output capacitor in the worst condition in CCM operation can be calculated as follows.
In ( 86) and (88), R indicates the output load resistor and ∆V O /V O calculates the relative error in the output voltage.

Design of Series Inductors L 7 , L 8
According to the converter operation in mode 5, the following equations are reached.
Inductors L 7 and L 8 can be operated either in resonant or linear modes in the proposed converter.The maximum current that flows through the inductors is equal to the peak resonant current.Inductors L 3 and L 4 have equal inductances.
In (92), ∆I L3 = ∆I L4 .Moreover, their values are equal to half the peak-to-peak current that flows through L 3 and L 4 .

Design of Capacitors C 1 , C 2
Based on the capacitor charge balance, the following equations are computed.
Since the capacitors have linear operation, the following equation can be used.
Based on the converter operation during modes 1 and 2, the following formula is obtained.
Because i L3 has a small value, it is ignored.
In (100), ∆V C1 is usually 10% of the rated output voltage.

Design of Switches M 1 and M 2
Voltage and current stresses should be calculated to select the appropriate type of switches.50 kHz is selected as the switching frequency for the proposed converter.

Design of Output Diodes D 3 , D 4
The voltage and current stresses of the diodes can be calculated as follows.Voltage and current stresses of the diodes can be considered as follows.
5.9.Design of Resonant Elements C 3 , C 4 , L 5 , L 6 The maximum current that flows through the resonant elements is considered equal to the input current.
By considering 20% as over-design, the following equation is computed.
According to the converter operation, the resonant frequency should be at least twice the switching frequency.
By using (109) and ( 110), the values of resonant inductors (L 5 = L 6 ) and resonant capacitors (C 3 = C 4 ) are obtained.It should be noted that the voltage gain of the proposed converter in CCM can be calculated as follows.

Control of the Proposed DC-DC Converter
Figure 5 shows the general block diagram of the control circuit followed by the detailed diagram presented in Figure 6.The first two blocks, i.e., the output sampler and isolator, are realised through TL431.These are then followed by error amplifier and a PID compensator block.This is eventually directed to the SG3527 for PWM and then to the pulse delay circuit to adjust the produced signal.
compensator block.This is eventually directed to the SG3527 for PWM and then to the pulse delay circuit to adjust the produced signal.
At different loads, the output voltage should be stabilized by the control circuit.Hence, the influence of load variations on the output voltage is illustrated in Figure 7.As can be shown from the figure, the control circuit performs well during sudden load changes.Changing of the load is 25 to 100% and 50 to 100% of the rated load in Figure 7a,b, respectively.

Simulation and Experimental Results
To confirm the theoretical analysis of the proposed converter, simulation waveforms using Pspice software are shown in Figure 8.Moreover, a prototype of the proposed converter is constructed.According to the design consideration, the value for each element is presented in Table 1.A prototype of the proposed converter is presented in Figure 9.At different loads, the output voltage should be stabilized by the control circuit.Hence, the influence of load variations on the output voltage is illustrated in Figure 7.As can be shown from the figure, the control circuit performs well during sudden load changes.Changing of the load is 25 to 100% and 50 to 100% of the rated load in Figure 7a,b, respectively.

Simulation and Experimental Results
To confirm the theoretical analysis of the proposed converter, simulation waveforms using Pspice software are shown in Figure 8.Moreover, a prototype of the proposed converter is constructed.According to the design consideration, the value for each element is presented in Table 1.A prototype of the proposed converter is presented in Figure 9.
Table 1.Main parameters of the converter.

Parameter
Value Type Number

Simulation and Experimental Results
To confirm the theoretical analysis of the proposed converter, simulation waveforms using Pspice software are shown in Figure 8.Moreover, a prototype of the proposed converter is constructed.According to the design consideration, the value for each element is presented in Table 1.A prototype of the proposed converter is presented in Figure 9.The derived voltage and current waveforms of the active power switches M2 and M1 are, respectively, shown in Figures 10 and 11.According to the converter operation in mode 1, the switch is turned on under ZCS condition.This is performed because the switch is connected in series with inductor L8, which has zero current at t0. Due to the symmetric structure, the waveforms of switch M1 are similar to M2.The gating signals of the TLDC should have a phase difference of 180 degrees to each other.The derived voltage and current waveforms of the active power switches M2 and M1 are, respectively, shown in Figures 10 and 11.According to the converter operation in mode 1, the switch is turned on under ZCS condition.This is performed because the switch is connected in series with inductor L8, which has zero current at t0. Due to the  The derived voltage and current waveforms of the active power switches M 2 and M 1 are, respectively, shown in Figures 10 and 11.According to the converter operation in mode 1, the switch is turned on under ZCS condition.This is performed because the switch is connected in series with inductor L 8 , which has zero current at t 0 .Due to the symmetric structure, the waveforms of switch M 1 are similar to M 2 .The gating signals of the TLDC should have a phase difference of 180 degrees to each other.The output capacitors, i.e., CO1 and CO2, operate as expected with the dc voltage waveforms shown in Figure 12.Due to the three-level structure, the voltage across each capacitor is equal to half of the output voltage.Figure 13 illustrates the input and output voltages.The output capacitors, i.e., CO1 and CO2, operate as expected with the dc voltage waveforms shown in Figure 12.Due to the three-level structure, the voltage across each capacitor is equal to half of the output voltage.Figure 13 illustrates the input and output voltages.The output capacitors, i.e., C O1 and C O2 , operate as expected with the dc voltage waveforms shown in Figure 12.Due to the three-level structure, the voltage across each capacitor is equal to half of the output voltage.Figure 13 illustrates the input and output voltages.The output capacitors, i.e., CO1 and CO2, operate as expected with the dc voltage waveforms shown in Figure 12.Due to the three-level structure, the voltage across each capacitor is equal to half of the output voltage.Figure 13 illustrates the input and output voltages.Figure 14 presents the voltage and current waveforms of diode D4, which is connected in series with inductor L8.Based on the converter operation in mode 1, the diode is switched off under ZCS condition when switch M2 is turned on.Due to the symmetric structure, the voltage and current waveforms of diode D3 are similar to diode D4.In the second half of the switching cycle, inductor current I L4 is similar to I L3 .Capacitor voltage V C1 is presented in Figure 17.Due to the symmetric structure, capacitor voltage V C2 is similar to V C1 in the second half of the switching cycle.In the second half of the switching cycle, inductor current IL4 is similar to IL3.Capacitor voltage VC1 is presented in Figure 17.Due to the symmetric structure, capacitor voltage VC2 is similar to VC1 in the second half of the switching cycle.The comparison between the proposed converter and other high step-up TLDCs in terms of voltage gain, voltage stress, soft switching, switching frequency, and the number of active elements is presented in Table 2.
Figure 21 show the efficiency variations with variations in the output load.Moreover, the operation of the converter under hard switching conditions is also plotted in this figure .It is obvious that the total efficiency of the proposed converter under soft-switching conditions is equal to 96.2% at full load.( ) [16] ( )   The comparison between the proposed converter and other high step-up TLDCs in terms of voltage gain, voltage stress, soft switching, switching frequency, and the number of active elements is presented in Table 2.
Figure 21 show the efficiency variations with variations in the output load.Moreover, the operation of the converter under hard switching conditions is also plotted in this figure .It is obvious that the total efficiency of the proposed converter under soft-switching conditions is equal to 96.2% at full load.( ) [16] ( )  The comparison between the proposed converter and other high step-up TLDCs in terms of voltage gain, voltage stress, soft switching, switching frequency, and the number of active elements is presented in Table 2.  Figure 21 show the efficiency variations with variations in the output load.Moreover, the operation of the converter under hard switching conditions is also plotted in this figure .It is obvious that the total efficiency of the proposed converter under soft-switching conditions is equal to 96.2% at full load.The voltage gain obtained by ( 111) is shown in Figure 22 for different values of the duty cycle.It is obvious that the voltage gain of the proposed converter is sufficiently high that it can be used for PV applications.Moreover, the voltage gains of other selected converters are depicted in Figure 22 to compare with the proposed converter.The power loss distribution at 250 W for the proposed TLDC is plotted in Figure 23.To explain Figure 23, power loss calculation with details is shown in Table 3.  Voltage gain versus duty cycle: the red, blue, and black graphs respectively correspond to the proposed converter, the converter in [25] and the converter in [22,23].The voltage gain obtained by ( 111) is shown in Figure 22 for different values of the duty cycle.It is obvious that the voltage gain of the proposed converter is sufficiently high that it can be used for PV applications.Moreover, the voltage gains of other selected converters are depicted in Figure 22 to compare with the proposed converter.The power loss distribution at 250 W for the proposed TLDC is plotted in Figure 23.To explain Figure 23, power loss calculation with details is shown in Table 3.The voltage gain obtained by ( 111) is shown in Figure 22 for different values of the duty cycle.It is obvious that the voltage gain of the proposed converter is sufficiently high that it can be used for PV applications.Moreover, the voltage gains of other selected converters are depicted in Figure 22 to compare with the proposed converter.The power loss distribution at 250 W for the proposed TLDC is plotted in Figure 23.To explain Figure 23, power loss calculation with details is shown in Table 3.  Voltage gain versus duty cycle: the red, blue, and black graphs respectively correspond to the proposed converter, the converter in [25] and the converter in [22,23].Voltage gain versus duty cycle: the red, blue, and black graphs respectively correspond to the proposed converter, the converter in [25] and the converter in [22,23].

Conclusions
A Three-level DC-DC converter has been proposed, which benefits from a high voltage gain and a symmetric structure.The voltage gain ratio can reach up to 15 times, while no transformer or coupled inductor has been used.This high step-up capability is achieved by using two high step-up cells and two resonant paths in the converter topology.The converter has low input current ripple.Moreover, the voltage and current stresses of the switches are quite low.As the zero current switching has been achieved, the switching losses have been lowered, and the total efficiency of the proposed converter reaches 96.2% at full load.The proposed converter uses simple PWM to trigger only two power switches in its structure.A comprehensive comparison with the existing topologies, as well as simulations and experiments on a 250 W prototype, have confirmed the analysis for the operating conditions of 48 V as the input voltage and 700 V as the output voltage, with a switching frequency of 50 kHz

Figure 1 .
Figure 1.Block diagram of a grid-connected PV system.

Figure 1 .
Figure 1.Block diagram of a grid-connected PV system.

Figure 2 .
Figure 2. The circuit arrangement of the proposed converter.

Figure 3 .
Figure 3. Theoretical waveforms for the proposed converter.

Figure 2 . 25 Figure 2 .
Figure 2. The circuit arrangement of the proposed converter.

Figure 3 .
Figure 3. Theoretical waveforms for the proposed converter.

Figure 3 .
Figure 3. Theoretical waveforms for the proposed converter.

Figure 5 .
Figure 5.The block control of the proposed high step-up three-level converter.Figure 5.The block control of the proposed high step-up three-level converter.

Figure 5 . 25 Figure 6 .Figure 7 .
Figure 5.The block control of the proposed high step-up three-level converter.Figure 5.The block control of the proposed high step-up three-level converter.Energies 2023, 15, x FOR PEER REVIEW 16 of 25

Figure 7 .
Figure 7. Performance of the control circuit for a load exposed to an instantaneous change (a) 25% to 100% of rated load (b) 50% to 100% of rated load.

Figure 8 .
Figure 8. Simulation waveforms of the proposed converter: (a) voltage and current of switch M1, (b) voltage and current of diode D4, (c) voltage and current of diode D2, (d) voltage of capacitors C3 and C4, (e) current of inductors L5 and L6, and (f) current of inductors L7 and L8.

Figure 9 .
Figure 9. Experimental setup of the proposed converter.

Figure 8 .
Figure 8. Simulation waveforms of the proposed converter: (a) voltage and current of switch M 1 , (b) voltage and current of diode D 4 , (c) voltage and current of diode D 2 , (d) voltage of capacitors C 3 and C 4 , (e) current of inductors L 5 and L 6 , and (f) current of inductors L 7 and L 8 .

Table 1 .Figure 8 .
Figure 8. Simulation waveforms of the proposed converter: (a) voltage and current of switch M1, (b) voltage and current of diode D4, (c) voltage and current of diode D2, (d) voltage of capacitors C3 and C4, (e) current of inductors L5 and L6, and (f) current of inductors L7 and L8.

Figure 9 .
Figure 9. Experimental setup of the proposed converter.

Figure 9 .
Figure 9. Experimental setup of the proposed converter.

Figure 14
Figure 14 presents the voltage and current waveforms of diode D4, which is connected in series with inductor L8.Based on the converter operation in mode 1, the diode is switched off under ZCS condition when switch M2 is turned on.Due to the symmetric structure, the voltage and current waveforms of diode D3 are similar to diode D4.

Figure 14 .
Figure 14.Voltage (top) and current (bottom) waveforms of diode D4 (vertical scale 200 V/div or 2.5 A/div).Inductor currents IL7 and IL8 are shown in Figure 15.Moreover, inductor current IL3 is depicted in Figure 16.As mentioned earlier, IL3 increases and decreases linearly.

Figure 14 25 Figure 13 .
Figure 14 presents the voltage and current waveforms of diode D 4 , which is connected in series with inductor L 8 .Based on the converter operation in mode 1, the diode is switched off under ZCS condition when switch M 2 is turned on.Due to the symmetric structure, the voltage and current waveforms of diode D 3 are similar to diode D 4 .

Figure 14 .
Figure 14.Voltage (top) and current (bottom) waveforms of diode D4 (vertical scale 200 V/div or 2.5 A/div).Inductor currents IL7 and IL8 are shown in Figure 15.Moreover, inductor current IL3 is depicted in Figure 16.As mentioned earlier, IL3 increases and decreases linearly.

Figure 14 .
Figure 14.Voltage (top) and current (bottom) waveforms of diode D 4 (vertical scale 200 V/div or 2.5 A/div).Inductor currents I L7 and I L8 are shown in Figure15.Moreover, inductor current I L3 is depicted in Figure16.As mentioned earlier, I L3 increases and decreases linearly.

Figure 14
Figure 14 presents the voltage and current waveforms of diode D4, which is connected in series with inductor L8.Based on the converter operation in mode 1, the diode is switched off under ZCS condition when switch M2 is turned on.Due to the symmetric structure, the voltage and current waveforms of diode D3 are similar to diode D4.

Figure 14 .
Figure 14.Voltage (top) and current (bottom) waveforms of diode D4 (vertical scale 200 V/div or 2.5 A/div).Inductor currents IL7 and IL8 are shown in Figure 15.Moreover, inductor current IL3 is depicted in Figure 16.As mentioned earlier, IL3 increases and decreases linearly.

Figure 16 .
Figure 16.Inductor current IL3 (vertical scale 500 mA/div).In the second half of the switching cycle, inductor current IL4 is similar to IL3.Capacitor voltage VC1 is presented in Figure17.Due to the symmetric structure, capacitor voltage VC2 is similar to VC1 in the second half of the switching cycle.

Figure 17 .
Figure 17.Capacitor voltage VC1 (vertical scale 5 V/div).Voltage and current waveforms of diode D2 are displayed in Figure18.The diode is forward-bioased under ZCS at t0 to flow IL8.

Figure 18 .
Figure 18.Voltage (top) and current (bottom) waveforms of diode D2 (vertical scale 100 V/div or 20 A/div).Voltage waveforms of resonant capacitors C3 and C4 are shown in Figure 19.In addition, current waveforms of resonant inductors L5 and L6 are depicted in Figure 20.

Energies 2023 , 25 Figure 16 .
Figure 16.Inductor current IL3 (vertical scale 500 mA/div).In the second half of the switching cycle, inductor current IL4 is similar to IL3.Capacitor voltage VC1 is presented in Figure17.Due to the symmetric structure, capacitor voltage VC2 is similar to VC1 in the second half of the switching cycle.

Figure 17 .
Figure 17.Capacitor voltage VC1 (vertical scale 5 V/div).Voltage and current waveforms of diode D2 are displayed in Figure18.The diode is forward-bioased under ZCS at t0 to flow IL8.

Figure 18 .
Figure 18.Voltage (top) and current (bottom) waveforms of diode D2 (vertical scale 100 V/div or 20 A/div).Voltage waveforms of resonant capacitors C3 and C4 are shown in Figure 19.In addition, current waveforms of resonant inductors L5 and L6 are depicted in Figure 20.

Figure 17 .
Figure 17.Capacitor voltage V C1 (vertical scale 5 V/div).Voltage and current waveforms of diode D 2 are displayed in Figure18.The diode is forward-bioased under ZCS at t 0 to flow I L8 .Energies 2023, 15, x FOR PEER REVIEW 20 of 25

Figure 18 .
Figure 18.Voltage (top) and current (bottom) waveforms of diode D 2 (vertical scale 100 V/div or 20 A/div).Voltage waveforms of resonant capacitors C 3 and C 4 are shown in Figure 19.In addition, current waveforms of resonant inductors L 5 and L 6 are depicted in Figure 20.

Figure 21 .
Figure 21.Efficiency curve of the proposed converter under different load conditions.

Figure 22 .
Figure 22.Voltage gain versus duty cycle: the red, blue, and black graphs respectively correspond to the proposed converter, the converter in[25] and the converter in[22,23].

Figure 21 .
Figure 21.Efficiency curve of the proposed converter under different load conditions.

Figure 21 .
Figure 21.Efficiency curve of the proposed converter under different load conditions.

Figure 22 .
Figure 22.Voltage gain versus duty cycle: the red, blue, and black graphs respectively correspond to the proposed converter, the converter in[25] and the converter in[22,23].

Figure 22 .
Figure 22.Voltage gain versus duty cycle: the red, blue, and black graphs respectively correspond to the proposed converter, the converter in[25] and the converter in[22,23].

Energies 2023 , 25 Figure 23 .Table 3 . 9 Figure 23 .
Figure 23.Power loss distribution at 250 W.Table 3. Power losses of high step-up three-level soft switching DC-DC converter.Type of Loss Formula Proposed Converter 1

Table 1 .
Main parameters of the converter.

Table 2 .
A comprehensive comparison between the proposed converter and other TLDCs.

Table 2 .
A comprehensive comparison between the proposed converter and other TLDCs.

Table 2 .
A comprehensive comparison between the proposed converter and other TLDCs.