The Effect of Replacing Si-MOSFETs with WBG Transistors on the Control Loop of Voltage Source Inverters

: The operation of a voltage source inverter (VSI) depends on its output LC ﬁlter and the PWM modulator delay. The VSI model includes serial equivalent resistance based on the resistances of the active inverter bridge transistors, the ﬁlter coil winding, and additional PCB elements, such as traces and connectors, in addition to the large equivalent resistances that result from power losses in the coil core and switches. These dynamic power losses depend on the switching frequency and the inverter load. This paper investigates the change in equivalent serial resistance that occurs if the standard Si-MOSFET switches are replaced with wide bandgap (WBG) transistors with correspondingly lower equivalent serial resistance. The paper further investigates how such a change inﬂuences the design of the controller, given that replacement of the switches shifts the roots of the closed-loop characteristic equation. Theoretical analyses of the inﬂuence of equivalent serial resistance for a multi-input single-output passivity-based controller and a single-input single-output coefﬁcient diagram method are also presented. These analyses are applied to both types of switches. Two methods are used to measure the serial equivalent resistance for a given VSI using Si and WBG switches. The possibility of replacing switches with WBG technology in existing inverters was assessed, and the corresponding controller adjustment that would be required. The theoretical analysis is veriﬁed via the use of an experimental VSI.


Introduction
Contemporary power converters operate only in switching mode. For this purpose, different types of semiconductor power switches can be used. Power converters of small or medium size most commonly use Si-MOSFET enhancement mode switches. This typically includes converters of up to 10 kW power, although the IEC 62040-3 standards [1] define the boundaries of parameter measurement methods at 3 kW or 4 kW. N-channel switches have a driving threshold voltage of greater than zero, and are much cheaper than wide bandgap (WBG) transistors. They are relatively fast and easy to drive, even when a "current attack" is accounted for. However, n-channel switches have two disadvantages. First, the conduction channel, which is the drain-to-source resistance R DS , has a large resistivity. Second, the inductive load (e.g., the output filter inductance) suffers dynamic power losses when the gate-to-source capacitance Cgs is loaded and, critically, the gate-to-drain capacitance C gd at the Miller plateau [2,3], which exists while the MOSFET is within the active region. Key MOSFET parameters include the reverse transfer capacitance C rss = C gd , the input capacitance C iss = C gs + C gd , and the output capacitance C oss = C gd + C ds . Another relevant parameter [2,4] is the gate charge Q g but the switching power losses occur during loading of the charge Q sw (the charge stored in the gate capacitance from when the gate-source voltage has reached V th until the end of the Miller plateau), where Q sw < Q g , Q sw > Q gd . portant for our research, as the equivalent serial resistance will be measured for each type of switching transistor when part of the same 4H bridge VSI experimental model with identical drivers and output filter (a coil with a Super-MSS or FluxSan core [5]). The control changes required due to a reduction in equivalent resistance will be investigated for certain SISO and MISO control methods. There are some papers [11,12] concerning the control in the inverters with WBG transistors, but they do not consider the problem of changing the Si transistors to WBG transistors in the existing inverter. The basic static and dynamic properties of the tested Si, SiC, and GaN transistors are presented in Table 1. Table 1. Basic properties of the tested transistors. The remainder of this paper is laid out as follows. Section 2 investigates the theoretical influence of equivalent serial resistance on the maximum gains of multi-input single-output passivity-based (MISO-PBC) control. Section 3 investigates the theoretical influence of equivalent serial resistance on the coefficients of single-input single-output coefficient diagram method (SISO-CDM) control, and determines how a change in resistance shifts the poles of the closed-loop system transfer function, designed for different resistances. Section 4 presents Bode plots of measurements of the inverter's control transfer function for the different switch technologies, different coil core materials, and different switching frequencies. The VSI equivalent dynamic serial resistances are then calculated [13]. The power loss serial resistances for the same cases are calculated using the power efficiency measurements of the VSI, and compared with the dynamic serial resistances. Section 5 presents the experimental testing of the VSI using SISO-CDM control for the different types of switches. Section 6 summarizes the results of the previous sections. Section 7 concludes the paper, and considers the feasibility of changing VSI switch technology when using SISO-CDM control.

The Theoretical Influence of Equivalent Serial Resistance on the MISO-PBC Control Loop
As shown in Figure 1, the load current of an MISO controller is treated primarily as an independent disturbance (e.g., [14,15]). Although this approach allows the load impedance to be eliminated from the control law, it also eliminates feedback from the output voltage to the load current. In some cases, this simplification changes the locus of the characteristic equation poles for a closed-loop system [16]. However, this does not usually result in instability. Hence, the modulator model consists of the following: the state variables: inductor current i LF and output voltage v OUT ; an independent disturbance, load current i OUT ; and delay equal to T s . For a high switching frequency, the delay can be omitted. The influence of the equivalent serial resistance Rse must now be determined, which varies with the use of different switching technologies, on the design of the control loop. The system is passive whenever the energy supplied to the system exceeds the stored energy. Within an inverter, energy is stored in two non-dissipative components-the filter coil and the filter capacitor. The energy stored within a system is described by the Hamiltonian function H(x) (also known as the Lyapunov function [17]). The Hamiltonian function of the error vector e is Equation (1).
The equilibrium of a closed-loop system is asymptotically stable [18], and is achieved if H(e) has a minimum at x = xref (3): The system is passive if the time derivative of H(e) is negative Equation (4): The control law of improved PBC v.2 (IPBC2) in single-phase inverters is based on the creation of a control law for interconnection and damping assignment PBC (IDAPBC) [14,18,19], Equations (9) and (10). The IPBC2 control law can be calculated [20,21] as the difference between the equation for a closed-loop PBC system (5) and the equation for an open-loop PBC system (6).
where the interconnection matrix J, the damping matrix R, and the PBC controller matrix Ra, are defined as Equation (7) 01 10 The influence of the equivalent serial resistance R se must now be determined, which varies with the use of different switching technologies, on the design of the control loop. The system is passive whenever the energy supplied to the system exceeds the stored energy. Within an inverter, energy is stored in two non-dissipative components-the filter coil and the filter capacitor. The energy stored within a system is described by the Hamiltonian function H(x) (also known as the Lyapunov function [17]). The Hamiltonian function of the error vector e is Equation (1). where The equilibrium of a closed-loop system is asymptotically stable [18], and is achieved if H(e) has a minimum at x = x ref (3): The system is passive if the time derivative of H(e) is negative Equation (4): The control law of improved PBC v.2 (IPBC2) in single-phase inverters is based on the creation of a control law for interconnection and damping assignment PBC (IDAPBC) [14,18,19], Equations (9) and (10). The IPBC2 control law can be calculated [20,21] as the difference between the equation for a closed-loop PBC system (5) and the equation for an open-loop PBC system (6).
where the interconnection matrix J, the damping matrix R, and the PBC controller matrix R a , are defined as Equation (7) Energies 2022, 15, 5316

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Note that R a includes the injected damping values-the current error gain R i and the voltage error conductive gain K v . Subtracting Equation (6) from Equation (5) gives the control law Equation (8): The PWM registers are set in one period, and the pulse widths are set in the following switching period. If the switching frequency is sufficiently high (25,600 Hz or greater), the switching period delay T s of the digital PWM modulator can be omitted. The final form of the IPBC2 control law is then Equations (9) and (10): IPBC requires that appropriate values of the injected resistance R i (inductor current gain) and conductance K v (output voltage gain) be chosen. The values R se + R i and the value of K v should be positive to fulfil the requirements of the negative real components of the roots λ 1,2 of the characteristic polynomial of the closed-loop IPBC system [21]: Equation (11) This equation does not provide the upper boundaries for the current and voltage gains. The higher the gains, the greater the convergence of the error tracking. However, IPBC2 gain values that are too high cause oscillations of the VSI output voltage. This is because the control voltage increases too quickly when compared to the speed of the PWM. This creates a saturation-like effect within the control loop. For a higher switching frequency with correspondingly faster PWM, higher gains can be used [22]. Estimating PWM speed can be difficult. For double-edge symmetrical regular modulation, the PWM signal increases as V DC /(T s /2) [17]. However, the fastest change of modulation in one switching period is V DC during one T s (V DC /T s ), what was taken in care of in [22]. All the time, the T s delay of the modulator is omitted.
The mutual dependency of the two PBC controller gains is highly important. During a single sampling period, the approximation d(v OUTref )/dt ≈ 0 can be made. Therefore, from Equations (10), (12)- (14) were obtained: From Equations (9), (13)-(16) were obtained: During a single switching cycle, for R LOAD >> 1/(2πf s C F ), the following approximations, Equations (17) and (18), can be made: From Equation (18), the final boundary on PBC gains, R i and K v Equation (19), was obtained: Equation (19) demonstrates the influence of switching frequency f s = 1/T s and equivalent serial resistance R se on the maximum values of the IPBC2 gains. These relationships are portrayed in Figure 2. The lower the value of T s /L F , the lower the influence of the equivalent serial resistance R se . For high values of f s , the influence of R se will be negligible, and the maximum voltage and current gains will be higher [22]. This demonstrates the weak influence of equivalent serial resistance on maximum gains.
From Equation (18), the final boundary on PBC gains, Ri and Kv Equation (19), was obtained: Equation (19) demonstrates the influence of switching frequency fs = 1/Ts and equivalent serial resistance Rse on the maximum values of the IPBC2 gains. These relationships are portrayed in Figure 2. The lower the value of Ts/LF, the lower the influence of the equivalent serial resistance Rse. For high values of fs, the influence of Rse will be negligible, and the maximum voltage and current gains will be higher [22]. This demonstrates the weak influence of equivalent serial resistance on maximum gains. The presented gain values are derived from simulation models featuring a reference voltage amplitude of unity, a bridge supplied by VDC, and controller input signals from the inverter model output scaled by a factor of 1/VDC. Amplification of the voltage trace was adjusted for the real inverter such that for the nominal amplitude of the output voltage fundamental harmonic for a 50 Ω load, for the ADC range −4095-4095, provided a value of 3000 units. The 3000 output value was adjusted for the unity voltage scaling ratio. For the 50 Ω load resistance, which was assumed to be nominal, the amplification of the current trace was adjusted until the ADC provided a reading of 2000 units. This gave an output current scaling ratio of (3000/2000)/50 = 0.03. For a small output capacitance of 1 μF, it was performed the same adjustment procedure was performed for the inductor current trace, and the same current scaling ratio of 0.03 was obtained. The voltage and current scaling factors require careful adjustment because they are multiplied by the PBC controller gains. For the experimental inverter, reference amplitudes of 1640 and 820 for the 25,600 Hz and 51,200 Hz switching frequencies, respectively, were used. The presented gain values are derived from simulation models featuring a reference voltage amplitude of unity, a bridge supplied by V DC , and controller input signals from the inverter model output scaled by a factor of 1/V DC . Amplification of the voltage trace was adjusted for the real inverter such that for the nominal amplitude of the output voltage fundamental harmonic for a 50 Ω load, for the ADC range −4095-4095, provided a value of 3000 units. The 3000 output value was adjusted for the unity voltage scaling ratio. For the 50 Ω load resistance, which was assumed to be nominal, the amplification of the current trace was adjusted until the ADC provided a reading of 2000 units. This gave an output current scaling ratio of (3000/2000)/50 = 0.03. For a small output capacitance of 1 µF, it was performed the same adjustment procedure was performed for the inductor current trace, and the same current scaling ratio of 0.03 was obtained. The voltage and current scaling factors require careful adjustment because they are multiplied by the PBC controller gains. For the experimental inverter, reference amplitudes of 1640 and 820 for the 25,600 Hz and 51,200 Hz switching frequencies, respectively, were used. For each set of values, 3000 units were used for the voltage and 2000 units for the current as nominal ADC values. Therefore, the gain scaling factors between simulation and experiment were r(25,600 Hz) = 3000/1640 = 1.829, and r(51,200 Hz) = 3000/820 = 3.659 for 25,600 Hz and 51,200 Hz, respectively. The scaled gains were assigned as R iinverter = R isym /r and K vinverter = K vsym /r. The MISO-PBC system is robust against a decrease in serial equivalent resistance. As such, this paper presents no further research on the subject.

The Theoretical Influence of Equivalent Serial Resistance Influence on the SISO-CDM Control Loop
A schematic of the SISO system is presented in Figure 3 [23][24][25][26]. Kvsym/r. The MISO-PBC system is robust against a decrease in serial equivalent resistance. As such, this paper presents no further research on the subject.

The Theoretical Influence of Equivalent Serial Resistance Influence on the SI-SO-CDM Control Loop
A schematic of the SISO system is presented in Figure 3 [23][24][25][26].  (20): where S includes the additional loop delay Ts measured from the Bode plots of the loop. The characteristic equation of a closed-loop system in Manabe standard form is given by Equation (21): The VSI is initially modeled as an output LFCF filter, and described by the state equations The state equations are solved for a single k-th switching period Ts, for double edge 3-level PWM, with a switching-on time period TONk. The dependence of xk+1 on TONk is described by linearized exponential function Equations (25)-(28) [21]:  (20): where S includes the additional loop delay T s measured from the Bode plots of the loop. The characteristic equation of a closed-loop system in Manabe standard form is given by Equation (21): The VSI is initially modeled as an output L F C F filter, and described by the state equations The state equations are solved for a single k-th switching period T s , for double edge 3-level PWM, with a switching-on time period T ONk . The dependence of x k+1 on T ONk is described by linearized exponential function Equations (25)-(28) [21]: where The gain of the VSI, with double edge PWM and a digital modulator inserting a switching period delay T s , is given by Equation (29): where In our system, the load current I OUT was treated as an independent disturbance, although it can be treated as a state variable. For a system with a disturbance, the degrees of R and S are greater than or equal to n − 1, where n is the degree of D. The second degree of S and the third degree of R were assumed because of the additional loop delay in Equation (30): Equation (21) is Diophantine; to obtain equal r i and s i coefficients for equal degrees of z, the following equation should be solved with r 0 = p 0 = 1 Equation (31): The coefficients p i of Manabe standard form for a continuous system are required for the 6th degree of P(s). They are given by: Using the zero-order hold method, let us define a discrete-time transfer function using the c2d MATLAB function with a discretization cycle T s = 1/25600 s [14] (32): Consider the case for which τ = 8T s ( T s = 1/25600 s): The final calculation enables v OUT = v REF to hold in the steady state if the following condition is met (33): For our experimental model, L F = 2 mH, C F = 51 µF, and R se = 1 Ω was assumed. Using these values, and with τ = 8T s , the solutions of Equation (31)  The coefficient t 0 can be adjusted individually. The resultant difference control law is: Figure 4 shows the shifts in the poles of the closed-loop CDM system (with L F = 2 mH, C F = 51 µF, and τ = 8T s ) caused by changes in R se . Figure 4a,b shows a system that was configured for R CDM = R se = 2 Ω, before R se was decreased to 0.4 Ω. Figure 4c,d shows a system that was configured for R CDM = 0.4 Ω, before R se resistance was increased to 2 Ω.

The Difference in the Static and Dynamic Equivalent Serial Resistance of the Same VSI When Using Si and WBG Switches
As shown in Figure 5, the elementary VSI model is based on the output filter transfer function and the PWM modulator transfer function. The output filter transfer function is given by Equation (35): showing (a,b) a system configured for R CDM = R se = 2 Ω (black circles) subjected to a decrease in R se to 0.4 Ω (red crosses), and (c,d) a system configured for R CDM = R se = 0.4 Ω (red circles) subjected to an increase in R se to 2 Ω (black crosses); (a) S(z −1 ) order 2, R(z −1 ) order 2, P z (z −1 ) order 5; (b) S(z −1 ) order 2, R(z −1 ) order 3, P z (z −1 ) order 6 (given additional plant delay); (c) S(z −1 ) order 2, R(z −1 ) order 2, P z (z −1 ) order 5; (d) S(z −1 ) order 2, R(z −1 ) order 3, P z (z −1 ) order 6 (given additional plant delay).

The Difference in the Static and Dynamic Equivalent Serial Resistance of the Same VSI When Using Si and WBG Switches
As shown in Figure 5, the elementary VSI model is based on the output filter transfer function and the PWM modulator transfer function. The output filter transfer function is given by Equation (35): where where A digital PWM modulator introduces a single switching period delay because the pulse width data that are calculated and stored during the current period will be in its output in the next switching period: An additional delay can be introduced by double edge modulation [27]. The sum of these delays is relevant for control system design if the switching frequency fs is insufficiently high. However, as shown by Equations (4) and (11), the delay is compensated for during the relative measurement [13] of the control transfer function of the bridge and filter KCTRL, because a delay of period nTs concerns both the fundamental harmonic and the excitation. As presented, the relative appointment of the magnitude and phase cancels this delay.
The equivalent serial resistance of the VSI [25,28] is measured using the resultant power conversion losses. The static and dynamic power losses in the switches and the filter coil core can be measured from the magnitude of a Bode plot of the inverter (operating with the assigned switching frequency fs), within the range of frequencies where a maximum magnitude is located Equation (38): Switching frequencies fs of 12,800 Hz, 25,600 Hz, or 51,200 Hz were used for the test inverter. However, the frequency of the coil voltage pulses was double that of fs in the first PWM scheme [29]. The basic sinusoidal waveform had a fundamental frequency fm = 50 Hz. The excitation sinusoidal waveforms had variable frequencies. The load resistance RLOAD and the DC supply voltage VDC were then set for the selected operating point. The generated test signal VCTRL Equation (39) was the sum of the fundamental harmonic and the n-th harmonic [13,28]. For k = 1, …, (fs/fm), A digital PWM modulator introduces a single switching period delay because the pulse width data that are calculated and stored during the current period will be in its output in the next switching period: An additional delay can be introduced by double edge modulation [27]. The sum of these delays is relevant for control system design if the switching frequency f s is insufficiently high. However, as shown by Equations (4) and (11), the delay is compensated for during the relative measurement [13] of the control transfer function of the bridge and filter K CTRL , because a delay of period nT s concerns both the fundamental harmonic and the excitation. As presented, the relative appointment of the magnitude and phase cancels this delay.
The equivalent serial resistance of the VSI [25,28] is measured using the resultant power conversion losses. The static and dynamic power losses in the switches and the filter coil core can be measured from the magnitude of a Bode plot of the inverter (operating with the assigned switching frequency f s ), within the range of frequencies where a maximum magnitude is located Equation (38): Switching frequencies f s of 12,800 Hz, 25,600 Hz, or 51,200 Hz were used for the test inverter. However, the frequency of the coil voltage pulses was double that of f s in the first PWM scheme [29]. The basic sinusoidal waveform had a fundamental frequency f m = 50 Hz. The excitation sinusoidal waveforms had variable frequencies. The load resistance R LOAD and the DC supply voltage V DC were then set for the selected operating point. The generated test signal V CTRL Equation (39) was the sum of the fundamental harmonic and the n-th harmonic [13,28]. For k = 1, . . . , (f s /f m ), where M is the modulation depth (typically M ≤ 1, e.g., M = 0.9 to avoid distortions of the fundamental harmonic), f PWMINPUT is the microprocessor PWM unit comparator input frequency (84 MHz for the STM32F407VG), and A is the relative amplitude of the fundamental harmonic (A < 1, typically A = 0.8-0.9 depending on the dumping).
In the case for which the switching frequency f s = nf m , there are f s /50 samples of the sinusoidal reference during the fundamental period T m = 20 ms. From Equation (10), the number of samples of the n-th harmonic during this period is f s /(n50). The value n max = 100 was used for both f s = 25,600 Hz and f s = 51,200 Hz to provide a minimum of five and 10 samples per harmonic period, respectively. The possible distortion of the n max harmonics was not important because of damping for harmonics above the output filter resonance frequency, which was adjusted below the 20th harmonic. Precise measurement of the magnitude of the harmonics was not required across the range of frequencies defined by the filter resonant frequency, where ω F0 = 475 or ω F0 = 498 Hz for the used filter coil inductance of L F = 2 mH or 2.2 mH, although these values can vary by several percent [28] for the coil core consisting of the low power loss materials Super MSS and FluxSan [5]. An MKP C F = 51 µF filter capacitor was used. The filter resonant frequency ω F0 , as defined by Equation (36), was calibrated to be much lower than 2πn max 50 Hz.
The accuracy of the search for maximum gain was dependent on the frequency step grid. A low level of damping increases the error caused by the frequency step grid, causing difficulty in finding the exact maximum magnitude between the two measured points. However, a high level of damping can also cause ambiguity in the measurement of the maximum on the Bode plot. The L F and R se parameters can be calculated directly only when the maximum of the damping coefficient can be found: ξ F 2 < (1 + R se /R LOAD )/2, where R LOAD >> R se . The measured fundamental harmonic amplitude should be equal to 50-75% of the ADC range. Given that a 13-bit bipolar ADC with a range of -4093-4093 units was used, the required amplitude was 2000-3000 units. The excitation amplitude |h nIN | = 1-A was set to the highest possible value (typically 10-20%) that did not cause the output voltage for the filter resonant frequency to exceed the range of the ADC.
The complex test signal v CTRL , defined by Equation (39), has an amplitude of floor(0.5 f PWMINPUT /f s ). A higher value of f PWMINPUT corresponds to a more accurate synthesis of the control signal waveform by the STM32F407VG. A frequency f PWMINPUT = 84 MHz is sufficient for f s = 25,600 Hz. It was assumed that the fundamental harmonic is not damped within the inverter, and is delayed by T s or 2T s within the PWM modulator, as all components of the control signal are delayed. Hence, this delay is not present in the relevant calculations. Comparison of the output and input signals presents a problem, as the output voltage is measured in volts or ADC units, and the input control voltage is measured in PWM modulator comparator units. This problem is overcome by comparing the input and output excitations relative to the fundamental harmonics of the input and output, respectively. However, this approach is predicated upon the 50 Hz component not being damped. The amplitudes and phases of the harmonic components of the complex input and output signals are calculated using the fast Fourier transform [25]. For n = 1, . . . , n max , The magnitude Bode plot is then The phase Bode plot is not required for further calculations.
The measuring trace of the system influences the signal. As such, the trace characteristics (both magnitude and phase) were measured and subtracted from the corresponding initially measured data. The trace was subjected to negligible damping of less than 0.5 dB in the range of up to 500 Hz, with a phase shift corresponding to a delay of approximately 2T s . The corrected data of the control transfer function magnitude and phase were then plotted on a PC using MATLAB. The maximum values of the function |K CTRL | and the frequency ω max for which |K CTRL | max = |K CTRL (ω max )| can then be identified to calculate the damping coefficient ζ F Equation (43), and the serial equivalent resistance R se (44) [25,28]. The real value of L F can also be measured; however, this is not necessary for our pur- poses. Under the assumption that R LOAD >> R se , ζ F and R se can be calculated as follows Equations (43) and (44): Using a 50 Hz grid (∆ω = 25 Hz), the frequency ω max can be approximated as Equation (45): It was assumed that this approximation is the primary source of error in the calculation of R se . The error Equation (46) in the calculation of the damping coefficient ξ F is caused by the ∆ω max error associated with appointing ω max : The error presented in Equations (47) and (48) is larger for low-load currents because such conditions hamper the determination of a maximum when compared to the two closest measured points. Typically, this error causes higher measured resistance for lowload currents. Another source of error when using a high-load current is a Bode plot magnitude with an insufficiently steep gradient. This makes determining the maximum difficulty. Equations (47) and (48) show that the error of the serial equivalent resistance measurement increases with the damping coefficient, and depends on the test signal frequency grid. As described by Equation (39), the lowest grid frequency used for the generation of the test signal was 50 Hz, which corresponded to ∆ω = 25 Hz.
At the outset of the experiments, the magnitude and phase Bode plots of the experimental VSI were measured. A digital-to-analogue converter (DAC) was used to generate the test signal connected to the input of the measuring trace. Figure 6 presents the magnitude and phase Bode plots K TRACE (s) of this trace, which can be approximated by the second-order transfer function with an additional 2T s delay: The delay of the DAC is equivalent to that of the PWM modulator. As such, the pure trace has a delay of a single T s . The corner frequency of the output filter for L F = 2 mH and C F = 51 µF is 498 Hz, allowing K TRACE Equation (50) to be approximated in the range up to 1000 Hz, using only the delay 2T s and omitting the second-order transfer function. All the measured signal traces are identical outside of the voltage and current inputs; these measurements are provided by the isolated amplifier and the AC current transducer, respectively. However, across the restricted frequency range, all traces are approximately identical.
K TRACE (s) ≈ e −s2T s for ω < 2π1000 1/s. Three switching frequencies were implemented in the test system: 12,800 Hz, 25,600 Hz, and 51,200 Hz. Three types of transistors were used: the Si-based IRFP360, the SiC-based AIMW120R060M1H, and the GaN-based Cascode Device Structure GAN041-650WSB. Five resistive loads were used in the range of 12.5-100 Ω. This gave us a total of (transistors of 3 types) × (3 switching frequencies) × (5 load resistances) × (2 magnetic materials) = 90 different combinations of variables, and therefore 90 magnitude and phase Bode plots. Figures 7 and 8 present selected examples of the Bode plots. The selection of the examples has to show the influence of the transistor technology on the inverter Bode plots (Figure 7a,b) and finally on the dynamic serial resistances R se for the two coil core materials (Figure 7c,d). Figure 7a shows that the Si transistors have lower damping than the SiC transistors for R LOAD = 50 Ω and a FluxSan coil core. The same result was observed for the Super MSS core. It was assumed that this was caused by higher power losses in the coil for faster SiC switches. The resultant equivalent resistances are shown in Figure 7c,d for the Super MSS core and FluxSan core, respectively. Figure 7 shows that the lowest equivalent serial resistance R se was obtained for GaN transistors. However, the differences between the three transistor types are small for the chosen switching frequencies when using the same coil core material and load current. Figure 8a presents the exemplary influence of the load current on the magnitude Bode plot of the inverter with GaN transistors, and Figure 8b shows the exemplary influence of the switching frequency.
Using Equations (43) and (44), the equivalent serial resistances can be calculated from the magnitude Bode plots as a function of the VSI inductor current. The inductor current is higher than the load current, and flows through the bridge switches. The accuracy of the calculations is limited by the resolution by which the maximum magnitude can be found. This is demonstrated in Figure 8a; for the lowest load resistance of 12.5 Ω, the curve maximum is difficult to locate precisely via interpolation between the measured points. The amplitude of the test signal relative to the fundamental must be carefully selected. Figure 9 presents the serial equivalent resistance measurements for test signal amplitudes of 10% and 20% for f s = 12,800 Hz, GaN transistors, and a Super MSS core. All presented calculations used a 10% test signal.
Measurement of the serial resistance R se is based on the invariability of the fundamental 50 Hz harmonic of both the input and output control trace signals. As such, static serial resistance was not measured. The efficiency of the experimental VSI was measured directly to calculate serial resistance R LOSSES . Figure 10 shows the exemplary measurements of R LOSSES as a function of load current for both core types at f s = 25,600 Hz. This resistance comprises the full losses from the DC source in addition to the dynamic losses and, as such, should be higher than the previously measured dynamic serial resistance R se of the control trace. It can be assumed that R LOSSES = R 50Hz + R se , where R 50Hz represents the losses of the fundamental harmonic at 50 Hz in addition to the static losses.  can be found. This is demonstrated in Figure 8a; for the lowest load resistance of 12.5 Ω, the curve maximum is difficult to locate precisely via interpolation between the measured points. The amplitude of the test signal relative to the fundamental must be carefully selected. Figure 9 presents the serial equivalent resistance measurements for test signal amplitudes of 10% and 20% for fs = 12,800 Hz, GaN transistors, and a Super MSS core. All presented calculations used a 10% test signal. Figure 9. The influence of the relative test signal amplitude on the equivalent serial resistance measurement.
Measurement of the serial resistance Rse is based on the invariability of the fundamental 50 Hz harmonic of both the input and output control trace signals. As such, static serial resistance was not measured. The efficiency of the experimental VSI was measured directly to calculate serial resistance RLOSSES. Figure 10 shows the exemplary measurements of RLOSSES as a function of load current for both core types at fs = 25,600 Hz. This resistance comprises the full losses from the DC source in addition to the dynamic losses and, as such, should be higher than the previously measured dynamic serial resistance Rse of the control trace. It can be assumed that RLOSSES = R50Hz + Rse, where R50Hz represents the losses of the fundamental harmonic at 50 Hz in addition to the static losses.  Figures 11 and 12 show all the measurements of the serial resistances R se and R LOSSES for the Super MSS and FluxSan core materials, respectively. The resistances were measured from the magnitude Bode plots or input and output powers for each transistor type. The dynamic serial resistance R se shows a slight dependence on transistor type at a given switching frequency and load current. However, the R se values are similar for both coil core The results of the two approaches to measure the equivalent serial resistance of the VSI are demonstrated in Figures 11 and 12. The first is based on measuring the magnitude Bode plot of the control transfer function of the VSI ( Figure 5). This method is ideal for the estimation of the control loop parameters but has one disadvantage: it requires that the 50 Hz signal-the fundamental harmonic-is subjected to no damping. To correct the row measurements, the Bode plots of the measuring trace must be known ( Figure 6). Figures 11 and 12 show that no substantial difference (less than 0.2 Ω) exists between the R se values of different transistor types at the same switching frequency when using the same coil core material. However, GaN-based transistors always produce the lowest R se .
The complex equivalent resistance R LOSSES can be calculated from the power losses of the VSI (Figure 10). However, this resistance can include the component of the equivalent resistance that is outside the control loop and does not influence the quality of the output voltage. Both equivalent serial resistances R se and R LOSSES depend on the type of transistor used (Si, SiC, and GaN), their static and dynamic losses, switching frequency, and the coil core material (Super MSS and FluxSan).

Tests of the VSI Using CDM Control for Different Switch Types and Coil Core Materials
The experimental VSI was used to validate the effect of implementing the correct equivalent resistance within the controller. Figure 4b,d shows that for f s = 25,600 Hz and a time constant τ = 8T s , for the changes of the equivalent serial resistance, when the resistance R CDM in the CDM control law is the same, the system is stable, but the poles of the closed loop system are shifted. For the lower time constant, measuring the unstable system (Figure 4a) is impossible. It is possible to show that keeping the same resistance R CDM in the control law for different transistor technology in the bridge for the same output filter coil core material can increase distortions of the output voltage. The idea behind the experimental verification of the previous theoretical considerations (Section 3) is to find the resistance R CDM in the SISO-CDM control law for which there are the lowest distortions of the output voltage and to show that it is connected with the equivalent serial resistance of the bridge (dependent on the type of switching transistors).
The various resistances R CDM were used in the control law of the CDM controller for the different equivalent serial resistances of the VSI when using the nonlinear rectifier RC load defined in IEC 62040-3 (PF = 0.7) [1]. The THD of the output voltages was measured for SiC transistors at f s = 25,600 Hz using Super MSS coil core material, with both open-loop control and CDM control with τ = 8T s . Figure 13 shows the output voltage and current.
tions of the output voltage and to show that it is connected with the equivalent serial resistance of the bridge (dependent on the type of switching transistors).
The various resistances RCDM were used in the control law of the CDM controller for the different equivalent serial resistances of the VSI when using the nonlinear rectifier RC load defined in IEC 62040-3 (PF = 0.7) [1]. The THD of the output voltages was measured for SiC transistors at fs = 25,600 Hz using Super MSS coil core material, with both open-loop control and CDM control with τ = 8Ts. Figure 13 shows the output voltage and current.   Table 2 presents the RLOSSES resistances for IOUTRMS ≈ 0.5 A at the THDVOUT minima, for the Si, SiC, and GaN transistors, and the Super MSS and FluxSan core materials. Figure 14 shows that for the high time constant when the system is stable, no matter whether the serial resistance in the control law is, the choice of the proper resistance RCDM for the particular type of transistors and the coil core material improves the quality of the output voltage.   Table 2 presents the R LOSSES resistances for I OUTRMS ≈ 0.5 A at the THD VOUT minima, for the Si, SiC, and GaN transistors, and the Super MSS and FluxSan core materials. Figure 14 shows that for the high time constant when the system is stable, no matter whether the serial resistance in the control law is, the choice of the proper resistance R CDM for the particular type of transistors and the coil core material improves the quality of the output voltage.     When changing transistors, gate-driving circuits should be checked for oscillations. WBG transistors can oscillate due to associated parasitic elements. Switching oscillations can be damped using RC snubbers, ferrite beads, a reduction in di/dt, or novel gate driver designs [30]. Printed circuit boards (PCBs), which feature long traces between the gate driver output and the gate source terminal, can lead to high parasitic inductance in the gate loop and cause damage to SiC transistors [31]. Moreover, SiC-MOSFETs are sensitive When changing transistors, gate-driving circuits should be checked for oscillations. WBG transistors can oscillate due to associated parasitic elements. Switching oscillations can be damped using RC snubbers, ferrite beads, a reduction in di/dt, or novel gate driver designs [30]. Printed circuit boards (PCBs), which feature long traces between the gate driver output and the gate source terminal, can lead to high parasitic inductance in the gate loop and cause damage to SiC transistors [31]. Moreover, SiC-MOSFETs are sensitive to parasitic components in the measurement probe. Measuring certain values (e.g., the gate-source voltage) can introduce parasitic inductance between the test point and the ground lead of the probe, thereby decreasing the stability of the SiC-MOSFET. However, if drain-source oscillations are noticed in a previously designed PCB, the simplest solution is often to increase the value of the serial resistor in the gate-driving circuit [32]. Table 2 shows that the R CDM resistance for which THD VOUT was minimal was of comparable size to R LOSSES and was higher than R se . The relative change in THD VOUT for different values of R CDM was small-between 5 and 10%. GaN and SiC transistors produce the THD VOUT minimum at the same R CDM resistance for both coil core materials. The Si transistors produce the THD VOUT minimum at different R CDM resistance. These results demonstrate that SiC and GaN transistors can be mutually replaced without requiring any change in control, but that the replacement of Si transistors requires the control value of R CDM to be adjusted.

Results
The initial theoretical calculations showed that the value of the serial resistance in the control law did not seriously influence the controller gains when using the MISO-PBC control ( Figure 2). When using SISO-CDM control and measuring only the output voltage, the difference between the value of R CDM used in the control law and the real value of serial equivalent resistance causes changes in the assigned roots of the closed-loop system characteristic equation (Figure 4). The static R LOSSES and dynamic R se equivalent serial resistances were measured (Figures 11 and 12) for different types of transistors used (Si, SiC, and GaN), switching frequencies (12,800 Hz, 25,600 Hz, 51,200 Hz), and two coil core materials (Super MSS and FluxSan).
The system SISO-CDM for S(z −1 ) order 2, R(z −1 ) order 3, P z (z −1 ) order 6, τ = 8T s (Figure 4b,d) was tested by means of changing the used R CDM value (the equivalent serial resistance used in the control law) to get the lowest THD of the output voltage for the  Table 2) that it is possible to get the minimum THD for the adjusted R CDMmin that depends on the type of transistors and the coil core material. This adjusted value is higher than R se (Figures 11 and 12) and closer to R LOSSES . However, the adjustments R CDMmin for both WBG transistors were the same but different than for Si transistors. According to the theoretical prediction shown in Figure 4b,d, the system was stable for the different R CDM .

Conclusions
This paper showed how changing the type of transistor used in a VSI bridge can change the results produced by the controller. Two equivalent serial resistances were measured-the dynamic R se and the complex R LOSSES . Dynamic R se was found to be lowest for GaN-based transistors. However, different transistor types show only small differences of approximately 0.2 Ω, at the same switching frequency, load current, and coil core material. Much higher differences were observed in the measurement of R LOSSES . The measurements showed that changes between WBG transistors-SiC and GaN-can be made without any adjustment of the control. However, changing between Si and WBG transistors requires such an adjustment. The best control results were produced for the SiC transistors. However, these superior results could have been due to the driving circuits used. The adjustment of the R CDM resistance to a value close to R LOSSES in the control law of the SISO-CDM controller can slightly reduce the output voltage THD. Oscillations can occur in the transistor gate-driving circuit. For certain values of the additional serial resistance R G , there are oscillations in the gate circuit when using WBG transistors, while no oscillations are present for Si transistors. For the R G = 10 Ω resistor chosen for the Si transistors, the VSI with GaN transistors was oscillated in the experimental model. Increasing the value of the resistor was sufficient to prevent oscillations.