An DPWM for Active DC-Link Type Quasi-Z-Source Inverter to Reduce Component Voltage Rating

: The conventional DC-link type quasi-Z-source inverter has been known as a buck–boost inverter with a low component voltage rating. This paper proposes an active DC-link type quasi-Z-source inverter by adding one active switch and one diode to the impedance-source network to enhance the voltage gain of the inverter. As a result, the component voltage rating of the inverter is signiﬁcantly reduced, which is demonstrated through some comparisons between the proposed topology and others. A discontinuous pulse width modulation (DPWM) scheme is proposed to control the inverter, which reduces the number of commutations compared to the traditional strategy. Under this approach, the insertion of a shoot-through state does not cause any extra commutations compared to the conventional voltage-source inverter. Details about control implementation, steady-state analysis, and design guidelines are also presented in this paper. Simulation and a laboratory prototype have been built to test the proposed inverter. Both buck and boost operations of the proposed inverter are implemented to validate the performance of the inverter.


Introduction
Presently, inverters that convert energy from a DC input source to AC output voltage play an important role in the renewable energy system. Because of their simple structure, low component utilization, and high power density, conventional two-level inverters are used in a wide range of industrial applications [1][2][3][4]. Two forms of traditional twolevel inverters are voltage source inverters (VSI) and current source inverters (CSI). The VSI works as a voltage buck converter, where the peak-to-peak value of the AC output phase voltage is smaller than the DC link voltage. In comparison with VSI, the CSI is known as a boost converter, which uses many extra elements such as diodes [3]. Nowadays, inverters adopting a wide range of input voltage have attracted many researchers. However, conventional VSI and CSI do not adopt a wide range of input sources. In fact, the traditional solution installs a DC-DC boost converter in front of the conventional VSI to provide buckboost characteristics in two-stage power conversion. In this way, the input voltage is enhanced before feeding to the inverter circuit. In this solution, a short-circuit current generated by activating all switches in one or more phase legs can destroy the system. This state is known as the shoot-through (ST) state and is forbidden in VSI. To avoid this dangerous situation, dead-time control is adopted to generate control signals for inverter switches [5,6]. In this case, the rising edge of the control signal is delayed to avoid the ST state. It causes distortion at output voltage and an increment in total harmonic distortion (THD) of output current. Many pulse-width modulation (PWM) methods based on the direction of output current have been explored to compensate for the negative effects of dead time [5,6]. However, these studies introduced more control complexity and required many additional current sensors. current of the inductor is kept constant and the voltage gain is increased. It results in component voltage rating reduction. A discontinuous PWM (DPWM) control method is proposed to control this topology. In this control technique, the ST state is inserted into the phase operating with the highest reference signals. It leads to reducing the number o switching commutations down to equal to conventional two-level VSI. The next parts o this paper include seven sections. The inverter structure and steady-state analysis and design guidelines of the proposed inverter are presented in Sections 2 and 3, respectively Section 4 presents the semiconductor loss calculation. The comparison study, simulation and experimental results are attached in Sections 5-7.

Proposed Active DC-Link Type Quasi-Z-Source Inverter (ADC-qZSI) Topology
Two types of proposed ADC-qZSIs have been drawn in Figure 1. Both types are constructed by an ADC-qZS network followed by a conventional two-level inverter. The impedance source network is known as the boost unit and is formed by two inductors (L and L2), two capacitors (C1 and C2), one active switch (S0), and two diodes (D1 and D2) Compared to traditional DC-link qZSI in [8], the proposed inverter has one extra active switch, S0, and one extra diode, D2. This insertion makes this topology flexible to contro and increases the boost factor and voltage gain of the inverter. The conventional two-leve inverter is responsible for buck operation. With the corresponding control method, the proposed inverter can buck and boost the output voltage from a single DC source, Vdc Each leg of the inverter side consists of two active switches, S1X and S2X, which ensures a two-level voltage at the output terminals, +VPN and zero. In general, two types of ADC qZSIs have similar operations, thus, type 1 shown in Figure 1a is selected for analysis.

Operating States
Like any single-stage inverter, the ADC-qZSI is also proposed to operate under ST mode and non-ST mode, as shown in Figure 2. The on/off states of inverter switches and diodes are listed in Table 1.

Operating States
Like any single-stage inverter, the ADC-qZSI is also proposed to operate under ST mode and non-ST mode, as shown in Figure 2. The on/off states of inverter switches and diodes are listed in Table 1. current of the inductor is kept constant and the voltage gain is increased. It results in component voltage rating reduction. A discontinuous PWM (DPWM) control method i proposed to control this topology. In this control technique, the ST state is inserted into the phase operating with the highest reference signals. It leads to reducing the number o switching commutations down to equal to conventional two-level VSI. The next parts o this paper include seven sections. The inverter structure and steady-state analysis and design guidelines of the proposed inverter are presented in Sections 2 and 3, respectively Section 4 presents the semiconductor loss calculation. The comparison study, simulation and experimental results are attached in Sections 5-7.

Proposed Active DC-Link Type Quasi-Z-Source Inverter (ADC-qZSI) Topology
Two types of proposed ADC-qZSIs have been drawn in Figure 1. Both types ar constructed by an ADC-qZS network followed by a conventional two-level inverter. Th impedance source network is known as the boost unit and is formed by two inductors (L and L2), two capacitors (C1 and C2), one active switch (S0), and two diodes (D1 and D2) Compared to traditional DC-link qZSI in [8], the proposed inverter has one extra activ switch, S0, and one extra diode, D2. This insertion makes this topology flexible to contro and increases the boost factor and voltage gain of the inverter. The conventional two-leve inverter is responsible for buck operation. With the corresponding control method, th proposed inverter can buck and boost the output voltage from a single DC source, Vd Each leg of the inverter side consists of two active switches, S1X and S2X, which ensures two-level voltage at the output terminals, +VPN and zero. In general, two types of ADC qZSIs have similar operations, thus, type 1 shown in Figure 1a is selected for analysis.

Operating States
Like any single-stage inverter, the ADC-qZSI is also proposed to operate under ST mode and non-ST mode, as shown in Figure 2. The on/off states of inverter switches and diodes are listed in Table 1.
In the ST state, as shown in Figure 2a, the inverter side is able to produce value of 0 V at three-phase output voltages by turning on two switches in one phase leg, while switch S 0 is gated off. As a result, the DC-link voltage, V PN , is shorted and has a value of zero. This ST state reverses diode D 1 and forward diode D 2 of impedance source circuit. In this mode, inductor L 1 is stored energy from DC input voltage and capacitor C 2 , while inductor L 2 is stored energy from DC input voltage and capacitor C 1 . The inductor voltages and capacitor currents are expressed as follows: where V dc is DC input source; V C1 and V C2 are capacitor C 1 and C 2 voltages; i L1 , i L2 , and i PN are instantaneous values of inductor currents and equivalent inverter side current.
In non-ST mode, the DC-link voltage obtains maximum value, which is determined by the summing DC input source and two capacitor voltages. With one extra switch, S 0 , the non-ST mode consists of two sub-modes depending on the state of S 0 . When S 0 is gated on, non-ST mode 1 shown in Figure 2b is achieved. Diode D 2 is reversed bias, whereas diode D 1 is forward bias. It results in shorting inductor L 2 and discharging capacitor C 2 . While capacitor C 1 is charged from inductor L 1 . The following equations are obtained: It can be seen that this non-ST mode maintains the energy of inductor L 2 instead of discharging like conventional ISI, which increases the boost factor of the inverter.
Non-ST mode 2 of the proposed inverter, as shown in Figure 2c, is like any single-stage inverter. Switch S 0 is gated off, whereas the inverter side switches operate like conventional inverters. Two inductors transfer energy to capacitors. The following equations are achieved:

Proposed DPWM Control Strategy
To reduce the switching commutation, the proposed method uses a DPWM strategy to generate the control signals to inverter switches. To detail this modulation method, let us first define three signals v X (X = A, B, and C) as follows: where M is modulation index; f o is fundamental frequency.
Three reference signals v * X (X = A, B, C), as shown in Figure 3, can be obtained by subtracting v X from minimum value of v A , v B , v C as follow: where M is modulation index; fo is fundamental frequency. Three reference signals * X v (X = A, B, C), as shown in Figure 3, can be obtained by subtracting vX from minimum value of vA, vB, vC as follow: These three reference signals are compared to high-frequency carrier Vtri like a conventional two-level inverter, to produce on/off switching signals for inverter side switches. In this scheme, one-third of the output period has no switching commutation in any phase leg, as shown in Figure 3. Thus, the switching loss can be reduced when compared to the conventional sinusoidal PWM method.
In the conventional PWM control method for single-stage inverters, the constant signal is used to generate the ST signal of the inverter leg. When this ST signal is inserted into the switching sequence, it produces at least two extra commutations in any phase leg. To overcome this, the proposed method uses discontinuous modulation signal vST and the maximum value of * X v to produce ST signal, as presented in Figure 3. In more detail, the ST signal is activated when Then, this ST signal is inserted into the phase which has the maximum value of reference signal * X v by triggering on both switches S1X and S2X of that phase leg. In this way, the ST insertion does not generate any These three reference signals are compared to high-frequency carrier V tri like a conventional two-level inverter, to produce on/off switching signals for inverter side switches. In this scheme, one-third of the output period has no switching commutation in any phase leg, as shown in Figure 3. Thus, the switching loss can be reduced when compared to the conventional sinusoidal PWM method.
In the conventional PWM control method for single-stage inverters, the constant signal is used to generate the ST signal of the inverter leg. When this ST signal is inserted into the switching sequence, it produces at least two extra commutations in any phase leg. To overcome this, the proposed method uses discontinuous modulation signal v ST and the maximum value of v * X to produce ST signal, as presented in Figure 3. In more detail, the ST signal is activated when max Then, this ST signal is inserted into the phase which has the maximum value of reference signal v * X by triggering on both switches S 1X and S 2X of that phase leg. In this way, the ST insertion does not generate any extra switching commutation compared to conventional two-level VSI. For example, as shown in zoom-in waveforms of switches S 1A and S 2A control signals, there are only two switching commutations for each switch, which equals the conventional two-level inverter.
Like any impedance source two-level inverter, the ST state must be inserted within zero vectors. Therefore, ST duty ratio D ST is not larger than (1 − M) and can be controlled independently by M. The v ST signal and ST duty ratio are expressed as follows: where D ST is ST duty ratio. The control signal of S 0 is generated by comparing control signal v con to carrier signal V tri , as shown in Figure 3. The v con is identified as: where D 0 is duty ratio of switch S 0 .
In order not to affect the operating modes of the inverter, v con must be satisfied with the following term:

Steady-State Analysis
independently by M. The vST signal and ST duty ratio are expressed as follows: where DST is ST duty ratio. The control signal of S0 is generated by comparing control signal vcon to carrier signal Vtri, as shown in Figure 3. The vcon is identified as: where D0 is duty ratio of switch S0.
In order not to affect the operating modes of the inverter, vcon must be satisfied with the following term:   Assuming that the equivalent inverter current, i PN , is constant, the average values of inductor currents can be approximately calculated by applying capacitor charge-balanced principle to capacitor C 1 and C 2 currents, as follows:

Steady-State Analysis
The boost factor, B, of the inverter is identified as: Energies 2022, 15, 4889 The peak value of fundamental component of output phase voltage is calculated as: wherev X is the peak value of output phase voltage. The voltage gain, G, of proposed inverter is expressed as: By setting D 0 to max value which is expressed in (8), the max voltage gain can be obtained.

Inductor and Capacitor Selection
As shown in Figure 4, the inductor current ripples are depended on the time interval of non-ST mode 2, (1 − v ST )T s . When v ST is maximum, the inductor current ripple is maximum. Based on (4)-(6), the maximum value of v ST can be calculated as: Based on (1)- (3) and (14), the maximum value of inductor current ripples can be expressed as: where ∆I Lj (j = 1, 2) is inductor L j current ripple; f s = 1/T s is switching frequency. The capacitor voltage ripples are calculated as: Based on (9), (10), (15) and (16), the inductors and capacitors are selected in terms of ∆I Lj /I Lj ≤ k 1 %, and ∆V Cj /V Cj ≤ k 2 %, where k 1 % and k 2 % are max acceptable ratios of inductor current and capacitor voltage ripples, respectively.

Semiconductor Device Selection
The maximum reversed voltage of diode D 1 is DC-link voltage, which is obtained in ST mode. The max reversed voltage of diode D 2 equals the capacitor C 2 voltage, which is achieved in non-ST mode 1.
The maximum value of diode D 2 current is equal to the maximum value of inductor L 2 current, which is obtained in non-ST mode 2, while the current through diode D 1 achieves its maximum value in non-ST modes, which is calculated as: where i Lj,max is the maximum value of inductor L j current, which can be calculated by applying (10) and (15). Switch S 0 is only installed to transfer the energy of inductor L 2 , and its current is constant when it is turned on, as shown in Figure 4. Thus, its current is the average value of the inductor L 2 current, which is expressed in (10). As shown in (9), the voltage across S 0 equals the voltage across capacitor C 2 .
The voltage across the inverter side switches is equal to the DC link voltage. The maximum current through switch S 1X is ST current, which is determined by summing two max values of two-inductor currents.

Semiconductor Loss Contribution
The power loss of semiconductor devices is classified into two groups: (1) loss of semiconductor devices of an impedance source circuit, and (2) power loss of inverter side switches. MOSFET devices are adopted for switching devices in this analysis.

Loss of Switching Devices of Impedance-Source Network
As shown in Figure 3, the S 0 switch of the intermediate circuit has one switching action per switching period, T S . The switching voltage and current of switch S 0 are capacitor C 2 voltage and inductor L 2 current, respectively. When S 0 is gated on, the current across S 0 is I L2 and the time interval of this state is D 0 T s . Therefore, the power loss of switch S 0 is calculated as: where P S0,cond and P S0,sw are conduction and switching losses of S 0 ; t ri , t fu , t ru and t fu are respectively current rise time, current fall time, voltage rise time, and voltage fall time of MOSFET. In any switching cycle, diode D 1 has two switching events when the ST state is activated. When diode D 1 is reverse biased, it blocks DC link voltage. When D 1 is forward biased, it transfers inductor L 1 current in non-ST mode two and two inductor currents in non-ST mode one. The conduction loss and reverse recovery loss of diode D 1 are expressed as: where P D1,cond and P D1,rr are conduction and reverse recovery losses of D 1 ; V F and Q rr are forward voltage and reverse recovery charge of diode, respectively. Diode D 2 has one switching action per switching cycle when the S 0 switch is turned on. The reverse voltage of diode D 2 is the capacitor C 2 voltage. When diode D 2 is forward biased in ST mode and non-ST mode two, it transfers inductor L 2 current. The power loss of this diode is calculated as follows:

Loss of Switching Devices of Inverter Side Circuit
Three phase legs of the inverter side circuit have the same operating principle. Therefore, only the S 1A and S 2A switches of the phase A leg are considered in this analysis.
From π/6 to 5π/6 of output voltage, the reference signal v * A of phase A is the maximum. Thus, the ST state is inserted into this phase. This insertion makes S 2A switch at twoinductor currents. Similar to switch S 2A, the switching current of switch S 1A is the sum of two-inductor currents and phase A load current. From 0 to π/6 and 5π/6 to π, switch S 1A is switched at phase A load current. When switch S 1A is gated on, there is one reverse recovery action generated at the anti-parallel diode of switch S 2A . From π to 7π/6 and 11π/6 to 2π, switch S 2A is switched at phase A load current while there is one switching event of the body-diode of switch S 1A . Switches S 1A and S 2A have no switching action in the time interval from 7π/6 to 11π/6. Both switches S 1A and S 2A block DC link voltage like any conventional two-level VSI. The switching losses of both S 1A and S 2A are expressed as follows: where P S1A,sw and P S2A,sw are switching losses of switches S 1A and S 2A , respectively.
The conduction losses of switches S 1A and S 2A are expressed as: where P S1A,cond and P S2A,cond are conduction losses of switches S 1A and S 2A , respectively.

Power Loss Comparison between Proposed Topology and Conventional DqZSI
The proposed ADC-qZSI is compared to conventional DqZSI in [8] for semiconductor loss. In this comparison, two inverters are designed to operate under 200 V DC input source, 220 V RMS /380 V RMS AC output voltage, and 1.5 kW. The semiconductor components and operating parameters are listed in Table 2. With these parameters, the proposed topology needs 620-V DC-link voltage to generate 220 V RMS AC output voltage. While it is 910 V DC-link voltage for conventional DqZSI. As a result, the proposed topology used 1200 V switching devices instead of 1700 V devices such as the conventional topology in [8]. In the proposed configuration, the voltage stresses of switch S 0 and diode D 2 are capacitor C 2 voltage, which is 340 V. Thus, switch S 0 and diode D 2 are 650 V switching devices. The result of the power loss comparison is shown in Figure 5. The proposed ADC-qZSI introduces two more power losses at S 0 and diode D 2 compared to the traditional DqZSI. However, the other semiconductor losses of the proposed topology are smaller than DqZSI because of having a smaller DC link voltage. As a result, the total semiconductor loss of introduced ADC-qZSI is smaller than the conventional DqZSI. than DqZSI because of having a smaller DC link voltage. As a result, the total semiconductor loss of introduced ADC-qZSI is smaller than the conventional DqZSI.

Comparison Study
The main contributions of the proposed configuration can be listed as (1) using a small number of passive components, (2) high voltage gain, and (3) low component voltage rating, which are verified by comparing to some previous single-stage inverters

Comparison Study
The main contributions of the proposed configuration can be listed as (1) using a small number of passive components, (2) high voltage gain, and (3) low component voltage rating, which are verified by comparing to some previous single-stage inverters such as conventional DqZSI in [8], SL-qZSI in [18], rSL-qZSI in [19], ASC-EqZSI in [20], ASC/SL-qZSI in [21], and HG-qSBI in [22]. The comparison study concludes three sub-sections, which are (1) the number of components comparison; (2) boost factor and voltage gain comparison, and (3) component voltage stress comparison. Note that the proposed ADC-qZSI has two coefficients (D 0 and D ST ) to control the boost factor. Their relationship is shown in (6) and (8). Thus, in this comparison study, both maximum boost and minimum boost control are considered. In detail, the maximum boost control can be obtained by setting the value √ 3(1 − D ST )/2 for D 0 , and the minimum boost control can be achieved by setting the zero value for D 0 . It is worth noting that the ST duty ratios, D ST , of these works are set as (1 − M).

Number of Components
The overall comparison between these configurations has been summarized in Table 3. Among these topologies, the conventional DqZSI topology in [8] uses the smallest number of elements compared to others. However, it makes conventional topology have lower voltage gain and higher voltage stress compared to others, which is detailed in the next section. The SL-qZSI in [18] and rSL-qZSI in [19] do not use active switching devices in impedance source networks. Instead, they use more inductors and diodes to enhance voltage gain. In detail, the SL-qZSI in [18] uses one more inductor and two more diodes, while the rSL-qZSI in [19] uses two-more inductors and five more diodes compared to the proposed ADC-qZSI. The use of active switches in intermediate network topologies like [20][21][22] and the proposed topology helps save a large number of passive components like inductors and capacitors. The work in [21] uses two fewer inductors, one fewer capacitor, and two fewer diodes than in [19]. However, it still utilizes three more diodes than the proposed ADC-qZSI. Moreover, the use of only one capacitor [21] causes high capacitor voltage stress, which is detailed in the next part of this section. The proposed topology has the same number of components as ASC-EqZSI in [20] and HG-qSBI in [22], which are two inductors, two capacitors, two diodes, and only one active semiconductor device in the impedance-source network. Note that the inverter sides of these configurations use a conventional two-level inverter, thus, the number of elements for the inverter side circuit is the same for all these topologies.

Boost Factor and Voltage Gain
The boost factor and voltage gain of these topologies are shown in Figure 6. According to some studies [18][19][20][21][22], the HG-qSBI in [22] has the largest boost factor, as presented in Figure 6a, thus it also has the largest voltage gain. When the minimum boost control is applied, the boost factor of the proposed inverter is 1/(1 − 2D ST ), which is equal to conventional qZSI in [8]. As a result, the proposed topology produces the smallest boost factor and voltage gain compared to the works in [18][19][20][21][22]. However, the boost factor of the proposed ADC-qZSI can be extended by increasing the duty ratio D 0 of switch S 0 . When the duty ratio D 0 obtains a value of 0.5, the boost factor and voltage gain of the proposed method are equal to HG-qSBI in [22] and also higher than the works in [18][19][20][21]. When the maximum value of D 0 , √ 3(1 − D ST )/2, is achieved, the boost factor and voltage gain of the proposed ADC-qZSI are the largest, which brings a benefit to the low component voltage rating, as follows. (1) DqZSI [8], (2) SL-qZSI [18], (3) rSL-qZSI [19], (4) ASC-EqZ [20], (5) ASC/SL-qZSI [21], (6) HG-qSBI [22].

Component Voltage Rating
Some investigations on capacitor, diode and switch voltage stresses have been conducted, as illustrated in Figure 7. Note that there are a lot of diodes in these topologies, which have unequal voltage stresses, as shown in Table 3. Therefore, simply, the maximum values of diode voltage stresses are only considered in this comparison study. Figure 7a,b show voltage stress comparisons for capacitors C 1 and C 2 . The max boost control of the proposed ADC-qZSI produces the smallest capacitors C 1 and C 2 voltage rating compared to others, as shown in Figure 7a,b. Among these topologies, the impedance-source switch voltage stress is equal to the capacitor voltage. Thus, having a lower capacitor voltage rating causes a lower switch voltage rating, as shown in Figure 7c. (1) DqZSI [8], (2) SL-qZSI [18], (3) rSL-qZSI [19], (4) ASC-EqZSI [20], (5) ASC/SL-qZSI [21], (6) HG-qSBI [22].
Having a higher voltage gain makes the proposed ADC-qZSI able to use a higher modulation index compared to other topologies, as shown in Figure 6b. On the other hand, the boost factor can be calculated as follows: From (23), it can be seen that the proposed topology with the introduced DPWM method uses a higher modulation index, which leads to requiring a lower boost factor. The max value of diode voltage stress equals the boost factor, as shown in Table 3. Moreover, it is clear that the inverter side switch voltage rating is also equal to the boost factor. As a result, the proposed ADC-qZSI has the lowest diode and inverter side switch voltage stresses among these configurations, as presented in Figure 7d.

Simulation Results
The boost operation of the proposed ADC-qZSI has been tested in this section. Both 56 Ω resistive load and 45 Ω-100 mH resistive-inductive load are installed at the output of the inverter for testing. The parameters used in the simulation are listed in Table 4. The inverter is fed by a 150 V DC input voltage which is used to generate 110 V RMS AC output load voltage. The modulation index M, ST duty ratio D ST , and extra duty ratio D 0 are 0.81, 0.19, and 0.5, respectively. With these controlling parameters, two capacitor voltages, V C1 and V C2 are boosted to 66 V and 132 V for both loads, as shown in Figure 8. As a result, the peak value of DC-link voltage V PN is 350V, approximately. For resistive load, two inductor currents, I L1 and I L2 , are continuous, and their values are 4.85 A and 9.57 A, respectively. While they are 3.96 A and 7.83 A because the real power of 45 Ω-100 mH resistive-inductive load is smaller than 56 Ω resistive load for the same 110 V RMS AC output voltage. The output line-to-line voltage has three voltage levels, which vary from −V PN to +V PN . The output load current amplitudes of these loads are the same which is 2.06 A RMS . However, the current of the resistive-inductive load is a 30-degree lag compared to the current othe f resistive load. Having a higher voltage gain makes the proposed ADC-qZSI able to use a higher modulation index compared to other topologies, as shown in Figure 6b. On the other hand, the boost factor can be calculated as follows: From (23), it can be seen that the proposed topology with the introduced DPWM method uses a higher modulation index, which leads to requiring a lower boost factor. The max value of diode voltage stress equals the boost factor, as shown in Table 3. Moreover, it is clear that the inverter side switch voltage rating is also equal to the boost factor. As a result, the proposed ADC-qZSI has the lowest diode and inverter side switch voltage stresses among these configurations, as presented in Figure 7d.

Simulation Results
The boost operation of the proposed ADC-qZSI has been tested in this section. Both 56 Ω resistive load and 45 Ω-100 mH resistive-inductive load are installed at the output of the inverter for testing. The parameters used in the simulation are listed in Table 4. The inverter is fed by a 150 V DC input voltage which is used to generate 110 VRMS AC output load voltage. The modulation index M, ST duty ratio DST, and extra duty ratio D0 are 0.81, 0.19, and 0.5, respectively. With these controlling parameters, two capacitor voltages, VC1 and VC2 are boosted to 66 V and 132 V for both loads, as shown in Figure 8. As a result, the peak value of DC-link voltage VPN is 350V, approximately. For resistive load, two inductor currents, IL1 and IL2, are continuous, and their values are 4.85 A and 9.57 A, respectively. While they are 3.96 A and 7.83 A because the real power of 45 Ω-100 mH resistiveinductive load is smaller than 56 Ω resistive load for the same 110 VRMS AC output voltage. The output line-to-line voltage has three voltage levels, which vary from −VPN to +VPN. The output load current amplitudes of these loads are the same which is 2.06 ARMS. However, the current of the resistive-inductive load is a 30-degree lag compared to the current othe f resistive load.

Experimental Results
A laboratory prototype based on DSP TMS320F28335 has been built to verify the operation of the proposed inverter, as shown in Figure 9. Module six IGBTs SKMGD123D is utilized for the inverter-side circuit. Impedance source network is based on MOSFET 60R060P7, diode VS-60APF12-M3, 1 mF capacitors, and 3 mH inductors. A 56 Ω threephase output resistive load is considered to test the proposed inverter, which is fed through the tLC filter (3 mH and 10 µF) to mitigate the high-frequency component of the output voltage. The system parameters are listed in Table 4. The proposed ADC-qZSI is verified under buck and boost modes with the range of input DC voltage from 150 V to 400 V. In both cases, the parameters of the inverter are selected to generate 110 V rms at the output load voltage, in theory.
A laboratory prototype based on DSP TMS320F28335 has been built to verify operation of the proposed inverter, as shown in Figure 9. Module six IGBTs SKMGD1 is utilized for the inverter-side circuit. Impedance source network is based on MOS 60R060P7, diode VS-60APF12-M3, 1 mF capacitors, and 3 mH inductors. A 56 Ω th phase output resistive load is considered to test the proposed inverter, which is through the tLC filter (3 mH and 10 µ F) to mitigate the high-frequency component o output voltage. The system parameters are listed in Table 4. The proposed ADC-qZ verified under buck and boost modes with the range of input DC voltage from 150 400 V. In both cases, the parameters of the inverter are selected to generate 110 Vrms a output load voltage, in theory.
Firstly, a 150-volt input source is applied to test the inverter in boost mode. experimental results for the 150-volt input voltage are shown in Figure 10. The imped source network is utilized to boost the DC-link voltage, VPN. In this case, the ST duty DST, S0 duty ratio, D0 and modulation index, M are set as 0.19, 0.5 and 0.81, respecti With these parameters, the voltages of two capacitors, VC1 and VC2 are boosted to 55 V 105 V, respectively, as shown in Figure 10a. It results in 310 V of the peak value of link voltage, VPN, and output line-to-line voltage, VAB, as shown in Figure 10b. As sh in Figure 10a,b, the input current is discontinuous and has an average value of 4.0 whereas the two inductor currents, IL1 and IL2, are continuous and have average valu 4.08 A and 8.85 A, respectively. The zoom-in waveforms of two inductor currents, sw S0 drain-source voltage and DC-link voltage are shown in Figure 10c. It shows that inductor currents are increased linearly in the ST state, which is represented by the value of DC link voltage. When S0 is turned on, the inductor L2 current is kept cons The voltage stress of S0 is equal to the capacitor C2 voltage. The output load voltage In buck mode, a 400-volt DC input source is applied to test the inverter, the results are shown in Figure 11. The ST duty ratio D ST , S 0 duty ratio, D 0 and modulation index, M are set as 0, 0.5 and 0.68, respectively. The input voltage is now high enough to produce 110 V RMS at output load voltage. Therefore, two capacitor voltages are kept at 0 V, approximately, as illustrated in Figure 11a. The DC link voltage is equal to the input voltage. It also results in a 400-volt peak value of output line-to-line voltage, V AB , as shown in Figure 11b  In buck mode, a 400-volt DC input source is applied to test the inverter, the results are shown in Figure 11. The ST duty ratio DST, S0 duty ratio, D0 and modulation index, M are set as 0, 0.5 and 0.68, respectively. The input voltage is now high enough to produce 110 VRMS at output load voltage. Therefore, two capacitor voltages are kept at 0 V, approximately, as illustrated in Figure 11a. The DC link voltage is equal to the input voltage. It also results in a 400-volt peak value of output line-to-line voltage, VAB, as shown in Figure 11b. The waveforms of two inductor currents, switch S0 drain-source voltage and DC-link voltage are shown in Figure 11c. The voltage stress of S0 is 40 V, whereas the average values of two inductor L1 and L2 currents are 1.43 A and 1.94 A. The DC link voltage is equal to the input voltage. RMS values of output load voltage and current are 109 VRMS and 1.92 ARMS, respectively. Figure 12 shows the experimental results of the proposed inverter under variation of load in two cases: (1) the three-phase load change from 72 Ω to 40 Ω, and (2) the threephase load change from 40 Ω to 72 Ω. Both cases cause a small effect on capacitor voltages and output load voltages. It is clear that the 40 Ω load causes higher load and device currents than the 72 Ω load. It results in more device loss for case one than for case two, which reduces capacitor voltages, as shown in Figure 12.    Figure 12 shows the experimental results of the proposed inverter under variation of load in two cases: (1) the three-phase load change from 72 Ω to 40 Ω, and (2) the three-phase load change from 40 Ω to 72 Ω. Both cases cause a small effect on capacitor voltages and output load voltages. It is clear that the 40 Ω load causes higher load and device currents than the 72 Ω load. It results in more device loss for case one than for case two, which reduces capacitor voltages, as shown in Figure 12.

Conclusions
This paper proposed a new topology of ADC-qZSI by adding one active switch and one diode into the impedance source network. With these devices, one more operating mode is introduced for the proposed inverter besides the conventional ST and non-ST modes. During this extra mode, one inductor voltage is shorted. As a result, the energy of this inductor is maintained, which helps to increase the boost factor and voltage gain of the inverter compared to previous studies of single-stage inverters. Having higher voltage gain leads to the lower voltage rating of capacitors and switching devices. A DPWM control strategy reducing the number of commutations is presented to control this proposed inverter. Under this PWM method, the ST state insertion does not generate any extra commutations and the total switching commutations of the inverter are equal to conventional two-level VSI. Some comparisons between the proposed inverter and other previous single-stage inverters have been conducted to demonstrate these advantages.

Conclusions
This paper proposed a new topology of ADC-qZSI by adding one active switch and one diode into the impedance source network. With these devices, one more operating mode is introduced for the proposed inverter besides the conventional ST and non-ST modes. During this extra mode, one inductor voltage is shorted. As a result, the energy of this inductor is maintained, which helps to increase the boost factor and voltage gain of the inverter compared to previous studies of single-stage inverters. Having higher voltage gain leads to the lower voltage rating of capacitors and switching devices. A DPWM control strategy reducing the number of commutations is presented to control this proposed inverter. Under this PWM method, the ST state insertion does not generate any extra commutations and the total switching commutations of the inverter are equal to conventional two-level VSI. Some comparisons between the proposed inverter and other previous single-stage inverters have been conducted to demonstrate these advantages. The simulation and experimental results have been presented to verify the operation of the proposed inverter. Both buck and boost modes are considered to test the inverter.
Author Contributions: This article has received the same contributions from the authors. which include writing the paper and experiment implementation. This manuscript has been received agreement from all authors. This paper was a collaborative effort among all authors. D.-T.D., V.-T.T. and K.N. conceived the methodology, conducted the performance tests and wrote the paper. All authors have read and agreed to the published version of the manuscript.