Pulse-Amplitude-Modulation Full-Bridge Diode-Clamped Multilevel LLC Resonant Converter Using Multi-Neighboring Reference Vector Discontinuous PWM

: A full-bridge diode-clamped multilevel LLC resonant converter suitable for power conversion systems that use high input voltage, such as railway vehicles, is proposed in this paper. In order to eliminate the voltage deviations of the capacitors connected in series to the high voltage input DC link, a novel modulation strategy referred to as multi-neighboring reference vector discontinuous pulse-width modulation (MNRV DPWM) is proposed. Unlike the existing two-level resonant converter that varies the operating frequency to hold the output voltage constant, the proposed multilevel resonant converter modulates the amplitude of the fundamental wave input to a resonance tank while ﬁxing the operating frequency at the resonance point. Therefore, the design of passive elements becomes easier, and stable operation is possible over a wide operating range with only one power conversion stage. In this paper, the control algorithm and operation characteristics of the newly proposed full-bridge diode-clamped four-level LLC resonant converter are analyzed in detail and design guidelines are presented. The feasibility of the proposed converter is veriﬁed through a simulation and an experiment with a prototype converter.


Introduction
Due to excellent soft switching characteristics such as primary-side zero-voltage switching (ZVS) and secondary-side zero-current switching (ZCS), LLC resonant converters are widely used in many areas such as electric vehicles, servers, uninterruptible power supplies, and TV power adapters.Furthermore, with regard to an LLC resonant converter operating at a high switching frequency, the power density can be greatly improved due to the reduction in the size of the passive element [1,2].However, because the output voltage is controlled through frequency variations, a wide range of frequency sweeps is required in a wide input/load variation system, making it difficult to design optimal passive devices [3].In addition, because most resonant converters developed thus far are based on a frequency-controlled two-level topology, they are not widely used in high-power systems with very high input voltages, such as railroad vehicles, due to the limited endurance voltage of the switching devices.Currently, as part of the effort to replace the existing lowfrequency transformers, resonance topology-based power converters are widely applied to the auxiliary power systems of railway vehicles, with most being composed of two stages.One type is an LLC resonant converter controlled in an open loop with a fixed operating frequency, and the other is a constant-voltage regulator connected before or after the LLC converter, which also serves to provide proper voltage for the normal operation of the LLC resonant converter.This complicates the overall system configuration [4,5].
Meanwhile, multilevel converters have been studied extensively in an effort to overcome the limitations of the two-level topology [6][7][8][9][10].The multilevel converter, as exemplified by the diode-clamped method, the flying capacitor method, and the cascaded H-bridge, Energies 2022, 15, 4045 2 of 26 can be applied to a high-voltage, high-power system with devices with low withstand voltages.It also has the advantage of a low harmonic content and low dv/dt generation.Among these three, in a system that receives power from a single external power supply line such as a railroad vehicle, the diode-clamped topology with a simple power stage configuration is suitable.However, with diode-clamped topologies, it is not easy to balance the DC link capacitor voltages to ensure equal voltage sharing and good performance, especially for level four and higher.Over the past three decades, numerous researchers have attempted to find appropriate modulation strategies to solve the voltage balance problem in a three-phase diode-clamped multilevel converter [11][12][13][14].The addition of an external circuit to compensate for voltage deviations and a hybrid method that utilizes a diode-clamped circuit and a flying capacitor together both complicate the system and are not cost effective [15][16][17].Recently, the voltage imbalance problem of a three-phase diode-clamped DC/AC inverter with three or more levels was resolved using a virtual vector scheme [18][19][20].The voltage imbalance was eliminated by combining reference vectors whose associated current sum is zero with the aid of a virtual reference vector.However, in a three-phase system, the amount of calculation is increased because the phase angle as well as the magnitude of the reference voltage must be considered.In addition, it is not easy to find an optimal switching pattern due to the considerable redundancy of the switching pairs.The increased switching loss compared to the general space vector pulse-width modulation (SVPWM) scheme is another issue.Recently, carrier-overlapped PWM (COPWM) applicable to diode-clamped multilevel inverters was proposed [21].With multiple carrier-based modulation, it can control capacitor voltage deviation while maintaining volt-second balance in a diode-clamped multilevel inverter with four or more levels.However, this method is effective under ideal conditions and requires a little complex closed-loop control under non-ideal conditions and increases switching losses compared to the conventional single-carrier method [22].As previously discussed, most of the multilevel topologies known to date have been applied to three-phase inverter systems.Therefore, in order to apply the diode-clamped multilevel topology to the single-phase DC/DC converter, a new switching modulation technique is required that can effectively eliminate voltage deviations in series-connected DC link capacitors while simultaneously controlling the output voltage simply in a closed-loop control manner.
A multi-phase, multi-level LLC converter with a two-level topology-based modular structure has been proposed for high-voltage and high-power systems [23].Because it is based on the existing frequency modulation method, it is difficult to optimally design passive components under wide input/load variation conditions.Additionally, a separate resonance tank is required for each sub-module, increasing the required number of passive elements.A suitable solution for voltage deviation between series-connected DC link capacitors has not been proposed.Input-series-output-parallel (ISOP) topology based on a two-level DAB converter can handle high voltage and high power [24].However, the ISOP topology requires an additional passive element for each sub-module, which complicates the overall system.An additional control algorithm to guarantee a stable operation and an adequate input voltage distribution is also mandatory.
On the other hand, a fixed-frequency three-level full-bridge LLC resonant converter has been proposed [25].The output voltage can be controlled by modulating the magnitude of the fundamental wave component of the voltage input to the resonance tank.However, since it does not operate as a typical diode-clamped topology, it is difficult to control because each switch must be duty-controlled separately.In addition, there is no mention of a DC link voltage deviation problem.Although various modulation techniques have been proposed for the LLC resonant converter, a suitable method for a diode-clamped multilevel converter with four levels or more has not yet been reported [26].
Meanwhile, single-phase diode-clamped multilevel AC/DC and DC/AC converters based on MNRV DPWM were proposed recently [27,28].This MNRV DPWM is characterized by the presence of several adjacent reference vectors with different capacitor charging/discharging characteristics depending on the position of the command voltage in Energies 2022, 15, 4045 3 of 26 order to offset the voltage deviation of series-connected DC link capacitors and to match the magnitude of the command voltage on average.However, because AC/DC and DC/AC converters use a relatively low fundamental frequency to utilize a commercial grid or drive a motor, they use a relatively high frequency modulation index (m f ) to reduce capacitor voltage fluctuations due to the limited capacitance.To apply this MNRV DPWM to a DC/DC converter, some modifications of the modulation strategy are required, as in [29].
Based on [29], this paper presents a novel switching modulation scheme suitable for single-phase full-bridge diode-clamped multilevel LLC resonant converters with an addition of detailed circuit analysis, various types according to the carrier deformation, loss analysis, and experimental results.By using the linear amplitude modulation characteristics of the proposed diode-clamped multilevel converter, an LLC resonant converter based on voltage amplitude modulation with a fixed switching frequency at the resonant point is proposed, thus enabling an optimal passive device design and ensuring stable operation over a wide operating range.In addition, capacitor voltage deviation compensation is implemented using only m f = 2 owing to the high fundamental switching frequency of the DC/DC converter.The proposed method utilizes only the clamped switching pair based on DPWM to facilitate the design of the switching pattern and reduce the switching losses.This paper briefly introduces a modified MNRV DPWM suitable for DC/DC converters, analyzes the operating characteristics of the proposed voltage-magnitude-modulationbased diode-clamped multilevel LLC resonant converter, and presents design guidelines.In addition, various types of LLC resonant converters are examined according to the deformation of the carrier.The performance and feasibility of the proposed converter are verified through simulations and experiments.

General Approach: Multi-Neighboring Reference Vector Discontinuous PWM (MNRV DPWM)
Figure 1 shows the circuit diagram of the single-phase diode-clamped four-level PWM converter.The AC voltage source V S supplies input power to the full-bridge switching stack through boost inductor L B with an equivalent series resistance of R B .The full-bridge switching stage is composed of the switches Q A1 ~QA6 and Q B1 ~QB6 and the clamping diodes D A1 ~DA6 and D B1 ~DB6 .The output DC link stage consists of three series-connected capacitors, C dc1 , C dc2 , and C dc3 .R L implies output load resistance.
the magnitude of the command voltage on average.However, because AC/D DC/AC converters use a relatively low fundamental frequency to utilize a comm grid or drive a motor, they use a relatively high frequency modulation index (mf) to capacitor voltage fluctuations due to the limited capacitance.To apply this MNRV D to a DC/DC converter, some modifications of the modulation strategy are require [29].
Based on [29], this paper presents a novel switching modulation scheme suita single-phase full-bridge diode-clamped multilevel LLC resonant converters with a tion of detailed circuit analysis, various types according to the carrier deformatio analysis, and experimental results.By using the linear amplitude modulation char tics of the proposed diode-clamped multilevel converter, an LLC resonant converte on voltage amplitude modulation with a fixed switching frequency at the resonan is proposed, thus enabling an optimal passive device design and ensuring stable op over a wide operating range.In addition, capacitor voltage deviation compensatio plemented using only mf = 2 owing to the high fundamental switching frequency DC/DC converter.The proposed method utilizes only the clamped switching pai on DPWM to facilitate the design of the switching pattern and reduce the switching This paper briefly introduces a modified MNRV DPWM suitable for DC/DC conv analyzes the operating characteristics of the proposed voltage-magnitude-modu based diode-clamped multilevel LLC resonant converter, and presents design guid In addition, various types of LLC resonant converters are examined according to formation of the carrier.The performance and feasibility of the proposed conver verified through simulations and experiments.

General Approach: Multi-Neighboring Reference Vector Discontinuous PWM (MNRV DPWM)
Figure 1 shows the circuit diagram of the single-phase diode-clamped fou PWM converter.The AC voltage source VS supplies input power to the full-bridge ing stack through boost inductor LB with an equivalent series resistance of RB.T bridge switching stage is composed of the switches QA1~QA6 and QB1~QB6 and the cla diodes DA1~DA6 and DB1~DB6.The output DC link stage consists of three series-con capacitors, Cdc1, Cdc2, and Cdc3.RL implies output load resistance.Figure 2a shows the switching pairs of A and B legs and the capacitor charging/discharging status according to the position of the command voltage V C * of the single-phase diodeclamped four-level PWM converter.In the full-bridge four-level topology, 0, E, 2E, and 3E imply reference vectors representing each step voltage that can be output as a leg-toleg voltage.The numbers in parentheses refer to switching pairs (AB) that can express the reference vectors, and C and D positioned to the right of them are the charging and discharging states of the capacitor, respectively.For example, if V C * is located at 2 , in carrier-based sinusoidal pulse-width modulation (CB-SPWM), adjacent reference vectors are E and 2E, and (AB) expressing E has redundancy via (10), (21), and (32).With regard to (10), the charging/discharging state of the three capacitors connected in series as the top capacitor (C dc1 ), intermediate capacitor (C dc2 ), and bottom capacitor (C dc3 ) is DDC, which means that that C dc1 and C dc2 are discharging and C dc3 is charging.For CB-PWM, which is widely used in single-phase AC/DC converters, two reference vectors adjacent to V C * are selected and their duration is adjusted to satisfy the magnitude of V C * and generate a symmetrical PWM pattern to minimize the ripple, as shown in Figure 2b.However, from level 4 or higher, a voltage imbalance inevitably occurs due to the limited selectable reference vectors capable of actively controlling the charging/discharging state of the capacitors.In particular, when the unity power factor is controlled as in the PWM converter, the voltage of the middle capacitor among the capacitors constituting the DC link stage is excessively charged compared to the other capacitors.This occurs because the charging/discharging behavior cannot be actively controlled with only two adjacent reference vectors.Figure 2a shows the switching pairs of A and B legs and the capacitor charging/discharging status according to the position of the command voltage VC * of the single-phase diode-clamped four-level PWM converter.In the full-bridge four-level topology, 0, E, 2E, and 3E imply reference vectors representing each step voltage that can be output as a legto-leg voltage.The numbers in parentheses refer to switching pairs (AB) that can express the reference vectors, and C and D positioned to the right of them are the charging and discharging states of the capacitor, respectively.For example, if VC * is located at ②, in carrier-based sinusoidal pulse-width modulation (CB-SPWM), adjacent reference vectors are E and 2E, and (AB) expressing E has redundancy via (10), (21), and (32).With regard to (10), the charging/discharging state of the three capacitors connected in series as the top capacitor (Cdc1), intermediate capacitor (Cdc2), and bottom capacitor (Cdc3) is DDC, which means that that Cdc1 and Cdc2 are discharging and Cdc3 is charging.For CB-PWM, which is widely used in single-phase AC/DC converters, two reference vectors adjacent to VC * are selected and their duration is adjusted to satisfy the magnitude of VC * and generate a symmetrical PWM pattern to minimize the ripple, as shown in Figure 2b.However, from level 4 or higher, a voltage imbalance inevitably occurs due to the limited selectable reference vectors capable of actively controlling the charging/discharging state of the capacitors.In particular, when the unity power factor is controlled as in the PWM converter, the voltage of the middle capacitor among the capacitors constituting the DC link stage is excessively charged compared to the other capacitors.This occurs because the charging/discharging behavior cannot be actively controlled with only two adjacent reference vectors.When (AB) is ( 20), (30), and (31), the capacitor charging/discharging states are DCC, CCC, and CCD, respectively, and it can be confirmed that Cdc2 is always in the charged state.In particular, for a PWM converter in which the phase difference between VC * and the input current is small, the capacitor charging current is largest when VC * is located in ① (large vector region (LRV)); moreover, even if VC * is located in different regions such as ② and ③ (the small vector region (SVR)), this overcharged state is not overcome, and the voltage deviation intensifies.Due to the characteristics of the diode-clamped multilevel converter, if the switching state is implemented by selecting two adjacent vectors as in the conventional CB-SPWM, the voltage deviation of the capacitor cannot be eliminated.Figure 3 shows the voltage imbalance problem of the PWM converter when applying CB-SPWM.VS is the input voltage source; IS is the input current; and Vdc1, Vdc2, and Vdc3 are the terminal voltages of Cdc1, Cdc2, and Cdc3, respectively.VAB is the switching leg voltage.As expected, the middle capacitor voltage Vdc2 increases continually after applying CB-SPWM.
Meanwhile, total harmonic distortion (THD) of the switching leg voltage VAB was analyzed under the following conditions of VS = 220Vrms(60Hz ac), output voltage Vdc = 500 V,   When (AB) is ( 20), (30), and (31), the capacitor charging/discharging states are DCC, CCC, and CCD, respectively, and it can be confirmed that C dc2 is always in the charged state.In particular, for a PWM converter in which the phase difference between V C * and the input current is small, the capacitor charging current is largest when V C * is located in 1 (large vector region (LRV)); moreover, even if V C * is located in different regions such as 2 and the proposed method.However, the CB-SPWM-based multilevel converter corresponds to an ideal case that is difficult to implement in practice due to a voltage imbalance problem.When compared with the existing two-level converter, the THD value of MNRV DPWM was reduced by 0.15.On the other hand, the multilevel topology enables the use of the low withstand voltage devices with lower switching losses than higher withstand voltage devices.Therefore, in the proposed method, switching frequency can be further increased, thereby reducing the size of filter for harmonic reduction and facilitating its design.
alyzed under the following conditions of VS = 220Vrms(60 Hz ac), output voltage V V, output power PO = 30 kW, source frequency fS = 60 Hz, mf = 55, LB = 4 mH, and mΩ.THD results were 0.23 and 0.43 for the CB-SPWM and the proposed MNRV D respectively, which reveals the much-increased high-frequency harmonic compon VAB in the proposed method.However, the CB-SPWM-based multilevel converter sponds to an ideal case that is difficult to implement in practice due to a voltage imb problem.When compared with the existing two-level converter, the THD value of DPWM was reduced by 0.15.On the other hand, the multilevel topology enables of the low withstand voltage devices with lower switching losses than higher wit voltage devices.Therefore, in the proposed method, switching frequency can be increased, thereby reducing the size of filter for harmonic reduction and facilita design.In order to solve the voltage deviation problem of the single-phase diode-cl multilevel converter, MNRV DPWM was proposed [27].Figure 2c shows the re vectors selected according to the location of VC * and the switching pairs that can rep them, also showing the capacitor charging and discharging states according to the ing mode (CM).When VC * is located in LVR, E, 2E, and 3E are selected as reference v If E is selected, which was not chosen in CB-SPWM, (10) and (32) can be utilized, an switching pairs can serve to discharge C2 (DDC, CDD).Therefore, if E is used as a re vector along with 2E and 3E, the voltage increase of C2 can be suppressed, and if ration times of reference vectors E, 2E, and 3E are properly adjusted, the magnitud can be tracked on average.In this paper, to reduce the switching redundancy and mize the switching loss, the clamped switching states in ±180° DPWM are employe This means that only (3×), (×3), (0×), and (×0) are used among all switching pairs t represent the reference vectors.(3×) and (×3) indicate that legs A or B, respective clamped with a positive DC rail, called the upper clamping mode (UCM), where C Similarly, (0×) and (×0) indicate the clamping of legs A or B, respectively, to the n DC rail, called the lower clamping mode (LCM), where CM = −1.The generation o tiple references to eliminate voltage deviations among DC link capacitors in [21] is to the proposed method.However, MNRV DPWM is used, since VC * is clamped positive or negative DC rail during every half cycle, resulting in the advantage of re the switching redundancy and minimizing the switching loss.Meanwhile, in the and LCM, the symmetry of the charging and discharging patterns for the same re vector are horizontally opposite to each other.For example, (31) and (20) are sw pairs expressing reference vector 2E in the UCM and LCM, respectively, but the ca charging/discharging patterns are symmetric in those opposite to each other as CC DCC.As a symmetrical characteristic, the charging/discharging characteristics wh is negative are identical to the case when VC * is positive.In order to solve the voltage deviation problem of the single-phase diode-clamped multilevel converter, MNRV DPWM was proposed [27].Figure 2c shows the reference vectors selected according to the location of V C * and the switching pairs that can represent them, also showing the capacitor charging and discharging states according to the clamping mode (CM).When V C * is located in LVR, E, 2E, and 3E are selected as reference vectors.If E is selected, which was not chosen in CB-SPWM, (10) and (32) can be utilized, and these switching pairs can serve to discharge C 2 (DDC, CDD).Therefore, if E is used as a reference vector along with 2E and 3E, the voltage increase of C 2 can be suppressed, and if the duration times of reference vectors E, 2E, and 3E are properly adjusted, the magnitude of V C * can be tracked on average.In this paper, to reduce the switching redundancy and minimize the switching loss, the clamped switching states in ±180 • DPWM are employed [30].This means that only (3×), (×3), (0×), and (×0) are used among all switching pairs that can represent the reference vectors.(3×) and (×3) indicate that legs A or B, respectively, are clamped with a positive DC rail, called the upper clamping mode (UCM), where CM = 1.Similarly, (0×) and (×0) indicate the clamping of legs A or B, respectively, to the negative DC rail, called the lower clamping mode (LCM), where CM = −1.The generation of multiple references to eliminate voltage deviations among DC link capacitors in [21] is similar to the proposed method.However, MNRV DPWM is used, since V C * is clamped to the positive or negative DC rail during every half cycle, resulting in the advantage of reducing the switching redundancy and minimizing the switching loss.Meanwhile, in the UCM and LCM, the symmetry of the charging and discharging patterns for the same reference vector are horizontally opposite to each other.For example, (31) and (20) are switching pairs expressing reference vector 2E in the UCM and LCM, respectively, but the capacitor charging/discharging patterns are symmetric in those opposite to each other as CCD and DCC.As a symmetrical characteristic, the charging/discharging characteristics when V C * is negative are identical to the case when V C * is positive.
The procedure for calculating the duration time of the MNRV based on the reduced capacitor voltage deviation is as follows.First, V dc1 , V dc2 , and V dc3 are input.Between V dc1 and V dc3 , which are the top and bottom capacitor voltages, respectively, we select a voltage with a large absolute difference from the reference value, V dc_ref /3, which is the target voltage of the unit capacitor.If the selected voltage is V dc1 and V dc_ref /3 − V dc1 is greater than zero, the UCM is selected.On the other hand, if the difference is less than zero, the LCM is selected.If the selected voltage is V dc3 and V dc_ref /3 − V dc3 is greater than zero, we select the LCM, and if the difference is less than zero, we select the UCM, because when the charging/discharging behavior of the capacitor according to CM is analyzed, for the UCM, V dc1 tends to increase and V dc3 decrease, and vice versa in the LCM.When CM is selected, the compensation controller calculates the duty compensation values for the reference vectors proportional to the voltage deviations among the capacitors.In a four-level converter, three capacitors and two voltage-deviation compensators are needed.There are several methods for configuring the controllers implementing the two voltage deviation compensators.Here, two controllers, one compensating for the difference between (V dc1 + V dc2 )/2 and V dc3 and the other compensating for that between V dc1 and (V dc2 + V dc3 )/2, are used.These design methods are natural charging/discharging characteristics of reference voltage vectors and easy to expand to a general high-dimensional multilevel converter.
As shown in Equation ( 1), the two compensation controllers output d comp12_3 and d comp1_23 , which are used to compensate for the voltage difference between (V dc1 + V dc2 )/2 and V dc3 and the voltage difference between V dc1 and (V dc2 + V dc3 )/2, respectively.In Equation ( 1), K P and K I mean the proportional and integral gains of the PI controller, respectively.According to the position of V C * and CM, the duties of the each MNRV are calculated as follows.If V C * belongs to the LVR, we select E, 2E, and 3E as the MNRV.Here, with E as a basic vector for the duty calculation, the duties of the E, 2E, and 3E vectors are calculated as Equation ( 2).Here, d E , d 2E , and d 3E are the duties of E, 2E, and 3E, respectively.V E , V 2E , and V 3E are the voltage levels of E, 2E, and 3E, respectively, meaning V dc_ref /3, V dc_ref •2/3, and V dc_ref .Equation ( 2) is applied differently depending on CM, and its meaning is as follows.The duties of the MNRVs must basically satisfy the magnitude of V C * .At the same time, the voltage deviations among all capacitors are reduced by applying two controller outputs (d comp12_3 and d comp1_23 ) differently according to CM.For example, if (V dc1 + V dc2 )/2 > V dc3 in the UCM, d comp12_3 increases and d 2E decreases.In the UCM, d 2E is the duty of the switching pair (31), which serves to increase V dc1 and V dc2 and decrease V dc3 .Therefore, V dc1 and V dc2 decrease and V dc3 increases due to the reduced d 2E .According to the negative feedback, d comp12_3 is stabilized and the capacitor voltage deviations are also reduced.The same can be explained in the LCM.Using the previously calculated duties of each reference vector, the PWM command values of each of the switches in the LRV are determined via Equation (3).Here, N max refers to the maximum value at the period of a single carrier considering the DSP implementation.For a positive V C * , leg A is clamped to the positive DC rail in the UCM and leg B is clamped to the negative DC rail in the LCM. (1) Energies 2022, 15, 4045 On the other hand, when V C * is located in the SVR, 0, E, 2E, and 3E are selected as reference vectors for a similar principle.To achieve a smooth transition at the moment of a region change, the range of the reference vectors in SVR must be wider than that of the LVR to increase the common reference vectors between the LVR and SVR.Each duty is calculated as in Equation ( 4).Here, d 0 is the duty of the 0 vector.Using the calculated duties of each reference vector, the PWM command values of each of the switches in the SRV are determined as in Equation (5).
Using the symmetric characteristic of the full-bridge topology, the duties of the MNRVs when V C * is negative are determined to be identical to those in the positive V C * case except for the interchange of legs A and B.
The MNRV DPWM applied to a single-phase diode-clamped four-level converter can be expanded to a general diode-clamped N-level converter as follows.Based on the analysis of the voltage fluctuation characteristics of the DC link capacitors of the reference step voltage vectors, appropriate MNRVs are selected according to the position of V C * and the capacitor voltage deviation compensation parameters are designed.MNRV selections applied to the five-level, six-level, and general N-level diode-clamped topologies are shown in Figure 4.The general rule for selecting MNRVs according to the VC * position is as foll Compensation parameters for controlling the voltage deviations of capacitors are N the N−level case.First, the charging/discharging states of the capacitors according t reference step voltage are analyzed as follows.In the N-level case, the maximum step age is (N−1)•E, and the capacitor charging/discharging state is CC…CC regardless of Because all capacitors are charged with the same amount of current, there is no vo deviation.The step voltage one step lower is (N−2)•E and the capacitor charging/disch ing states are CC…CD and DC…CC in the UCM and LCM, respectively.The outer capacitor is changed to the discharge mode.In the UCM, the capacitor located at the tom of the DC link stage, and in the LCM, the capacitor located at the top of the DC stage, change from charging to discharging mode.The next step voltage is ... The general rule for selecting MNRVs according to the V C * position is as follows.Compensation parameters for controlling the voltage deviations of capacitors are N − 2 in the N − level case.First, the charging/discharging states of the capacitors according to the reference step voltage are analyzed as follows.In the N-level case, the maximum step voltage is (N − 1)•E, and the capacitor charging/discharging state is CC . . .CC regardless of CM.Because all capacitors are charged with the same amount of current, there is no voltage deviation.The step voltage one step lower is (N − 2)•E and the capacitor charging/discharging states are CC . . .CD and DC . . .CC in the UCM and LCM, respectively.The outermost capacitor is changed to the discharge mode.In the UCM, the capacitor located at the bottom of the DC link stage, and in the LCM, the capacitor located at the top of the DC link stage, change from charging to discharging mode.The next step voltage is (N − 3)•E, and the capacitor charging/discharging states are CC . . .CDD and DDC . . .CC in the UCM and LCM, respectively.That is, whenever the step voltage decreases by one step, it can be seen that the capacitor charging/discharging states change from charging to discharging from the lower end of the DC link stage in the UCM and from the upper end of the DC link stage in the LCM.Applying this to all step voltages, the following rule can be found.The total number of different charging/discharging states of capacitors is 2(N − 2).At this time, there are step voltage pairs in which the sum of two step voltages is (N − 1)•E, and the capacitor charging/discharging states in the UCM and LCM of these two step voltages are related to the same capacitor voltage compensation parameters with opposite signs.The two step voltages in this case are cross oppositely coupled to each other; therefore, there are N−2 independent capacitor charging/discharging states in the overall step voltage.Thus, N−2 independent d comp parameters can be generated, i.e., d comp1_2...(N−1) , d comp12_3...(N−1) ,..., d comp1...(N−2)_(N−1) .In order to control the capacitor voltage deviation completely regardless of the position of V C * , the MNRV should be selected so that all independent compensation parameters are included.For every V C * location, it is sufficient to set the MNRV such that N−2 independent duty compensation parameters are included in order to eliminate the voltage deviations of all capacitors.However, large fluctuations in the duty compensation value may adversely affect normal operation; i.e., the duty of a particular reference vector can be negative or greater than one due to the addition of duty-compensation parameters.Accordingly, it is better to include all different charging/discharging states of the capacitors for more reliable operation by limiting the duty-compensation effort.Including all capacitor charging and discharging states is good for stable operation but increases the switching losses.However, as will be described later, by designing an appropriate carrier, a voltage-deviation-compensation operation may occur in the ZVS region, thereby minimizing an increase in the switching loss.Because the outermost vectors (0, (N − 1)•E) do not affect the capacitor voltage deviation, the capacitor-voltage-deviation-compensation parameters are designed from independent capacitor charging/discharging states of the remaining intermediate reference vectors.
In the five-level case, for example, there are three independent charging/discharging states: CDDD(DCCC), CCDD(DDCC), and CCCD(DDDC).The capacitor charging/discharging states of the reference voltages E in the UCM and 3E in the LCM are CDDD and DCCC, respectively.They both can be used to control the voltage deviation between V dc1 and (V dc2 + V dc3 + V dc4 )/3.It can be seen that the charging/discharging states of 2E in the UCM and LCM are CCDD and DDCC, respectively, and are related to the voltage deviations between (V dc1 + V dc2 )/2 and (V dc3 + V dc4 )/2.Similarly, the charge/discharge states of 3E in the UCM and E in the LCM are CCCD and DDDC, respectively, and they can be utilized to control the voltage deviation between (V dc1 + V dc2 + V dc3 )/3 and V dc4 with opposite signs.Therefore, in the five-level case, three independent compensation parameters are required to control the capacitor voltage deviation: d comp1_234 , d comp12_34 , and d comp123_4 .They are related to the voltage differences between V dc1 and (V dc2 + V dc3 + V dc4 )/3, (V dc1 + V dc2 )/2 and (V dc3 + V dc4 )/2, and (V dc1 + V dc2 + V dc3 )/3 and V dc4 , respectively.Therefore, if V C * belongs to the LVR, the range of the MNRV should be E ~4E in order to utilize all six different charging/discharging states of the capacitors.On the other hand, if V C * is located in the SVR, the MNRV range should be 0 ~3E for the same reason.In addition, when V C * moves between the LVR and SVR, the duties of the reference voltage vectors may suddenly change, which is a factor that degrades the linearity of the output voltage.Therefore, in order to minimize duty changes of the reference voltage vectors and thus ensure smooth transitions between the LRV and SRV, the minimum reference voltage in the LVR and the maximum reference voltage in the SVR should be selected as the basic vector for the MNRV.In this way, by selecting the MNRV according to the positions of V C * and designing compensation parameters for the deviations of the capacitor voltages, extension to a high-dimensional N-level diode-clamped converter is possible.For a general N-level case, the LRV and SRV range from roundup{(N − 1)/2}•E to (N − 1)•E and from 0 to roundup{(N − 1)/2}•E, respectively.The corresponding MNRVs are from E to (N − 1)•E and from 0 to (N − 2)•E, as shown in Figure 4.It should be noted that thus far MNRV DPWM has been described based on the incoming current to the switching legs, as in a PWM converter.Therefore, the charging/discharging states and CM selection should be reversed in DC/DC owing to the reversed reference current direction.AC/DC or DC/AC converters have a relatively high mf to reduce the harmonic c ponents and to control the fundamental component on average during one fundame period.However, in a DC/DC converter, it is desirable to increase the frequency of the switching pulse until it is within an acceptable switching loss range to reduce the siz the passive element.Given that such a high fundamental frequency increases the num of compensations for capacitor voltage deviation during the unit time, MNRV DPWM a DC/DC converter can be implemented with small mf, i.e., mf = 2.A DC/DC converte which MNRV DPWM is applied can also linearly modulate the magnitude of the refere voltage akin to a multilevel inverter.Therefore, when applied to a resonant converter output voltage can be controlled by modulating the magnitude of VC * while fixing frequency to the resonance point.This simplifies the design of the passive compon compared to those in conventional frequency-swept resonant converters.

Proposed Full-Bridge
The control block diagram of the proposed MNRV DPWM-based diode-clam four-level LLC resonant converter is shown in Figure 6.The output Vampl of the const voltage controller is multiplied by a pulse that swings between 1 and −1 at a rate of with switching frequency fsw to obtain pulse-shaped command voltage VC * .Here, fsw is AC/DC or DC/AC converters have a relatively high m f to reduce the harmonic components and to control the fundamental component on average during one fundamental period.However, in a DC/DC converter, it is desirable to increase the frequency of the AC switching pulse until it is within an acceptable switching loss range to reduce the size of the passive element.Given that such a high fundamental frequency increases the number of compensations for capacitor voltage deviation during the unit time, MNRV DPWM for a DC/DC converter can be implemented with small m f , i.e., m f = 2.A DC/DC converter to which MNRV DPWM is applied can also linearly modulate the magnitude of the reference voltage akin to a multilevel inverter.Therefore, when applied to a resonant converter, the output voltage can be controlled by modulating the magnitude of V C * while fixing the frequency to the resonance point.This simplifies the design of the passive components compared to those in conventional frequency-swept resonant converters.
The control block diagram of the proposed MNRV DPWM-based diode-clamped four-level LLC resonant converter is shown in Figure 6.The output V ampl of the constantvoltage controller is multiplied by a pulse that swings between 1 and −1 at a rate of 50% with switching frequency f sw to obtain pulse-shaped command voltage V C * .Here, f sw is designed as the resonance frequency (f r = 1/[2π•(L r C r ) 0.5 ]) for maximum efficiency.CM is set to be between 1 and −1, referring to the UCM and LCM, respectively, according to V dc1 and V dc3 .In order to remove the voltage deviations among the capacitors, V dc1 , V dc2 , and V dc3 are input to the PI controller to calculate the duty compensation parameters (d comp1_23 , d comp12_3 ).According to the position of V C * , appropriate MNRVs are selected and the duration times of each reference vectors are calculated, with the PWM CMDs of the A and B legs finally output.These values are compared to the triangular carrier to determine the on/off status of every upper switch in the A and B legs.According to the complementary rule of the diode-clamped topology, the on/off statuses of the lower switches are determined as opposite to the corresponding upper switches' on/off states in the same leg.Q A1 and Q A4 , Q A2 and Q A5 , and Q A3 and Q A6 are the complementary switch pairs in leg A. The same applies to leg B.

Overall Operation Characteristics of the Proposed Converter
In this section, we analyze the operation mode of the proposed diode-clamped four level resonant LLC converter.The operation state of the circuit is largely classified accord ing to CM. Figure 7 shows the circuit operation status in the UCM and LCM, and (AB) on the right side of each circuit represents the switching status of the A and B phases.Th shaded red line in the figure represents the current path flowing through the channel o body diode of the conducting switches.Except for (30), (03), (33), and (00), the magnitud and direction of the current flowing through the series-connected capacitors Cdc1, Cdc2, and Cdc3 differ depending on the switching pattern as follows.In the switching pairs of (31 and (13), the charging/discharging state is DDC, and in (32) and (23) the charging/dis charging state is DCC.In ( 20) and (02) the charging/discharging state is CDD, and in (10 and (01) the charging/discharging state is CCD.Therefore, it is expected that a voltag deviation will occur because the charging/discharging patterns of each capacitor diffe depending on the duration of the specific switching pair.Here, the amount of charg ing/discharging current flowing through each capacitor is related to ILr.If there are tw capacitors connected in series, the charging/discharging current becomes 1/3 × ILr, and i there is one capacitor, it becomes 2/3 × ILr.For example, for (32), Cdc1 is discharged with current of 2/3 × ILr and Cdc2 and Cdc3 are charged with 1/3 × ILr.The core principle of MNRV DPWM is to set several reference vectors, including all independent charging/discharging

Overall Operation Characteristics of the Proposed Converter
In this section, we analyze the operation mode of the proposed diode-clamped fourlevel resonant LLC converter.The operation state of the circuit is largely classified according to CM. Figure 7 shows the circuit operation status in the UCM and LCM, and (AB) on the right side of each circuit represents the switching status of the A and B phases.The shaded red line in the figure represents the current path flowing through the channel or body diode of the conducting switches.Except for (30), (03), (33), and (00), the magnitude and direction of the current flowing through the series-connected capacitors C dc1 , C dc2 , and C dc3 differ depending on the switching pattern as follows.In the switching pairs of (31) and ( 13), the charging/discharging state is DDC, and in (32) and ( 23) the charging/discharging state is DCC.In ( 20) and (02) the charging/discharging state is CDD, and in (10) and (01) the charging/discharging state is CCD.Therefore, it is expected that a voltage deviation will occur because the charging/discharging patterns of each capacitor differ depending on the duration of the specific switching pair.Here, the amount of charging/discharging current flowing through each capacitor is related to I Lr .If there are two capacitors connected in series, the charging/discharging current becomes 1/3 × I Lr , and if there is one capacitor, it becomes 2/3 × I Lr .For example, for (32), C dc1 is discharged with a current of 2/3 × I Lr and C dc2 and C dc3 are charged with 1/3 × I Lr .The core principle of MNRV DPWM is to set several reference vectors, including all independent charging/discharging characteristics of DC link capacitors depending on the location of V C * , and adjust their duration time to reduce the voltage deviations of the capacitors and to satisfy the magnitude of V C * on average at the same time.Based on this circuit operation state, Figure 9 shows the main operating waveforms of the proposed full-bridge diode-clamped four-level LLC resonant converter.CM is de- Figure 8 depicts the equivalent circuit of the resonance tank at the resonance point.Regardless of CM, when V C * > 0, one from among V dc , 2/3 × V dc , and 1/3 × V dc is applied to V leg , and nV O is applied to the magnetizing inductor L m .When the voltage of V leg − nV O is supplied to L r -C r , I Lr and I Lm increase in the positive direction.Meanwhile, when V C * < 0, one from among −V dc , −2/3 × V dc , and −1/3 × V dc is applied to V leg and −nV O is applied to L m .I Lr and I Lm decrease by V leg + nV O supplied to L r -C r .
Based on this circuit operation state, Figure 9 shows the main operating waveforms of the proposed full-bridge diode-clamped four-level LLC resonant converter.CM is determined as the UCM or LCM according to the characteristics of the capacitor voltage deviation at the start of one switching period.Here, it is assumed that the converter is operated in the UCM for one cycle and operated in the LCM during the next cycle in a steady state.The operation during one cycle is a series of symmetrical half-cycle operations, and the operation during the half-cycle is divided into six modes.Based on this circuit operation state, Figure 9 shows the main operating waveforms of the proposed full-bridge diode-clamped four-level LLC resonant converter.CM is determined as the UCM or LCM according to the characteristics of the capacitor voltage deviation at the start of one switching period.Here, it is assumed that the converter is operated in the UCM for one cycle and operated in the LCM during the next cycle in a

Operation under the UCM
Mode 1 [t0,t1]: At t0, CM is changed from the LCM to the UCM; the A leg upper switches QA1, QA2, and QA3 are all turned on with the ZVS condition owing to the negative current of ILr, and the B leg upper switches QB1, QB2, and QB3 are all turned off.Vleg with Vdc is input to the resonance tank stage, and the resonance current ILr formed by Lr and Cr is transferred to the secondary side of the transformer; DO1 then conducts, and the output voltage VO multiplied by the turn ratio of n is applied to Lm.At this time, the switching state is (30), and the currents flowing through Cdc1, Cdc2, and Cdc3 are all identical to Idc−ILr; here, Idc is the outgoing current of Vdc such that voltage deviations do not occur in the capacitor.This mode is terminated at t1 when QB6 turns off (when QB3 turns on).In mode

Operation under the UCM
Mode 1 [t 0 ,t 1 ]: At t 0 , CM is changed from the LCM to the UCM; the A leg upper switches Q A1 , Q A2 , and Q A3 are all turned on with the ZVS condition owing to the negative current of I Lr , and the B leg upper switches Q B1 , Q B2 , and Q B3 are all turned off.V leg with V dc is input to the resonance tank stage, and the resonance current I Lr formed by L r and C r is transferred to the secondary side of the transformer; D O1 then conducts, and the output voltage V O multiplied by the turn ratio of n is applied to L m .At this time, the switching state is (30), and the currents flowing through C dc1 , C dc2 , and C dc3 are all identical to I dc −I Lr ; here, I dc is the outgoing current of V dc such that voltage deviations do not occur in the capacitor.This mode is terminated at t 1 when Q B6 turns off (when Q B3 turns on).In mode 1, resonant current I Lr and resonant voltage V Cr are determined by Equation ( 6).Here, V leg is V dc and I Lr (0) and V Cr (0) refer to the initial values of I Lr and V Cr at t 0 , respectively.The characteristic impedance Z equals (L r /C r ) 0.5 , and the angular frequency ω is 2πf r .
Mode 2 [t 1 ,t 2 ]: When Q B6 is off at t 1 , the switching state becomes (31), and C dc1 and C dc2 are discharged with a current of 1/3 × I Lr and C dc3 is charged with a current of 2/3 × I Lr .V leg becomes 2/3 × V dc , and the voltage applied to L r -C r is changed from V dc to 2/3 × V dc ; thus, the slope of I Lr changes.L m is still charged with nV O due to the conduction of D O1 .This mode continues until Q B5 turns off at t 2 .In mode 2, I Lr and V Cr are also determined by Equation ( 6), except for V leg = 2/3 × V dc , and I Lr (0) and V Cr (0) are changed to I Lr (t 1 ) and V Cr (t 1 ), respectively.
Mode 3 [t 2 ,t 3 ]: When Q B5 is turned off at t 2 , the switching state is (32); accordingly, C dc1 is discharged with a current of 2/3 × I Lr , and C dc2 and C dc3 are charged with a current of 1/3 × I Lr .Because V leg is changed from 2/3 × V dc to 1/3 × Vdc, the slope of the I Lr also changes.L m is still charged with nV O .This mode ends when Q B5 is turned on at t 3 .In mode 3, I Lr and V Cr are also determined by Equation ( 6), except for V leg = 1/3 × V dc , and I Lr (0) and V Cr (0) are changed to I Lr (t 2 ) and V Cr (t 2 ), respectively.
Mode 4 [t 3 ,t 4 ]: When Q B5 is turned on at t 3 , the switching state is (31) again, and operation in this mode is identical to that in mode 2. This mode ends when Q B6 turns on at t 4 .
Mode 5 [t 4 ,t 5 ]: When Q B6 is turned on at t 4 , the switching state is (30), and operation in this mode is identical to that in mode 1.This mode is terminated when I Lr equals I Lm at t 5 .At the end of this mode, D O1 is turned off with the ZCS condition.
Mode 6 [t 5 ,t 6 ]: At t 5 , I Lr = I Lm , the primary and the secondary sides of the transformer are separated, and the resonance period becomes longer due to the large inductance of L m contributing to the resonance.This mode continues until the polarity of V C * becomes negative.In mode 6, I Lr and V Cr are determined by Equation (7).Here, V leg is V dc and I Lr (0) and V Cr (0) refer to the initial values of I Lr and V Cr at t 5 , respectively.The characteristic impedance Z' equals [(L r + L m )/C r ] 0.5 , and the angular frequency ω' is 1/[(L r + L m )•C r ] 0.5 .
Due to the symmetry of the DC/DC converter, operation during the remaining half cycle where V C * is negative can easily be inferred from the previous positive half cycle of V C * ; accordingly, a description thereof will be omitted.Regarding the capacitor charging and discharging status, in the UCM, V dc1 continues to discharge and V dc3 continues to charge regardless of the polarity of V C * .Therefore, under actual operating conditions, the UCM is selected when V dc1 > V dc3 .

Operation under the LCM When V C
* changes from negative to positive again, one cycle of LCM operation begins.Operation in the LCM has cross-symmetric duality with that of the UCM as follows.When Q A(m) /Q B(m) is turned on/off in the UCM, Q B(7-m) /Q A(7-m) is turned on/off in the LCM at the same timing, where m = 1, 2, ..., 6.That is, the turn on/off timing of switch pairs Q A1 and Q B6 , Q A2 and Q B5 , Q A3 and Q B4 , Q A4 and Q B3 , Q A5 and Q B2 , and Q A6 and Q B1 , located in cross-opposite directions, are correspondingly matched.Thus, when the A/B leg is clamped to the positive DC rail in the UCM, the B/A leg is clamped to the negative DC rail in the LCM at the same timing.This duality can be confirmed by examining Figures 7 and 9, and thus a detailed description of operation in the LCM is skipped here to save space.
In the LCM, V dc3 continues to discharge and V dc1 continues to charge regardless of the polarity of V C * .Therefore, under actual operating conditions, the LCM is selected when V dc1 < V dc3 .

Voltage Transfer Gain
In this section, the input-output voltage transfer gain M is derived through a fundamental harmonic analysis (FHA) [31].Figure 10 shows the V leg waveform when For convenience of the calculation, the original sag-type V leg is divided into a square-wave swinging at ±V dc with full duty and three square waves with the opposite phase, swinging at ±V dc /3 during angular sections [π/2 ± α], [π/2 ± β], and [π/2 ± γ], respectively.The fundamental component is analyzed as Equation ( 8).
The fundamental component is reduced compared to the full duty square wave due to the voltage sag section, as shown in Equation (10).Here, k = L m /L r , Q = Z/R ac , and R ac = 8n 2 R L /π 2 .The length of the sag section is related to the duty of the MNRV, which is also related to V C * .This means that even if the frequency is fixed, the output voltage can be adjusted by changing V C * .This is a distinguishing feature of the voltage modulation method used in MNRV DPWM compared to the conventional two-level resonant converter using the frequency modulation method.

Design of the Resonant Tank
The proposed converter regulates the output voltage by modulating the magnitude of Vleg while fixing the operating frequency to the resonance point.Therefore, the voltage gain range can be determined from the length of the voltage sag section in the normal operating range as shown in Equation (10).If the load increases while the output voltage

Design of the Resonant Tank
The proposed converter regulates the output voltage by modulating the magnitude of V leg while fixing the operating frequency to the resonance point.Therefore, the voltage gain range can be determined from the length of the voltage sag section in the normal operating range as shown in Equation (10).If the load increases while the output voltage is fixed, the DC link capacitors' charging/discharging current increases and the duty compensation effort must be increased.Therefore, the period of the voltage sag section may be out of the normal range and may no longer be able to undertake voltage compensation.With fixed V dc and V O values, d E decreases as n increases.At this time, if the load increases, d E may have an abnormal value due to the increased duty compensation parameters; therefore, n must be appropriately designed considering the sag section under the maximum load condition.When n is determined, a Q factor must be selected.A high Q implies a large L r and small C r , leading to a large reactor size and increased withstand voltage in C r .On the other hand, if Q is decreased, the shape of the resonance current deviates from a sinusoidal wave, increasing the root mean square (RMS) value of I Lr .Thus, an appropriate value must be selected.C r is determined as L m is selected by determining the ratio k between L m and L r .Reducing L m ensures ZVS operation while increasing circulating current and switch losses.Conversely, a large L m reduces circulating current and switch losses, but ZVS operation may not be guaranteed.In addition, L m affects the voltage gain in the region other than the resonance point.Therefore, an appropriate value of L m must be selected.

Resonant Current and Voltage
In this section, the peak resonant current I Lr_pk and voltage V Cr_pk are calculated in order to select an appropriate device by determining the rated switch current and the withstand voltage of the resonance capacitor.When operating at the resonance point, I Lr and I Lm are in a steady state, as shown in Figure 11.Here, it is assumed that I Lr and V Cr are sinusoidal for convenience of calculation, as in Equation (11).The initial phase difference φ between the I Lr and V leg waveforms is determined as Equation (12).From the observation that the difference between I Lr and I Lm during a half cycle is equal to the output current divided by n, I Lr_pk is determined to be Equation ( 13) [2].I Lr_pk is proportional to the load current and inversely proportional to L m .This is consistent with the fact that as the L m value decreases, the RMS value of I Lr increases with the increased circulating current.From the energy balance principle, V Cr_pk is calculated as Equation ( 14).

Input and Output Capacitances
The input DC link capacitances can be calculated from rent of the capacitor and the duration time of the voltage sa termines the duration time of the reference vector to satisfy age during the unit switching period, as shown in Figure 1 among α, β, and VC * can be derived as in Equation (15) (assu Vdc).
In addition, given that the duty compensation paramete small, we can assume that dE = d2E and α = 2β.The input-o Equation (10) at the resonance point can be simplified as Eq

Input and Output Capacitances
The input DC link capacitances can be calculated from the charging/discharging current of the capacitor and the duration time of the voltage sag period.MNRV DPWM determines the duration time of the reference vector to satisfy the magnitude of V C * on average during the unit switching period, as shown in Figure 12.Therefore, the relationship among α, β, and V C * can be derived as in Equation ( 15) (assuming γ = 0 when In addition, given that the duty compensation parameters in the steady state are very small, we can assume that d E = d 2E and α = 2β.The input-output voltage relationship of Equation ( 10) at the resonance point can be simplified as Equation ( 16) in a high V C * case where α and β are small, and α can be expressed as Equation (17).Thus, d E can be derived via Equation (18).

2, 15, x FOR PEER REVIEW
where α and β are small, and α can be expressed as Equ via Equation (18). 1)

  
(1 Figure 13 describes the characteristics of the volta pacitors in the LCM.From Equation (19), the incremen which equals decrement ΔVdc3, is related to Cdc, fsw, ILr_pk age fluctuation amount ΔVdc,target is determined, the Cdc using the previously obtained values of ILr_pk, α, β, an Relationship between V C * and V leg .
Figure 13 describes the characteristics of the voltage change of the input DC link capacitors in the LCM.From Equation (19), the increment ∆V dc1 during the unit half cycle, which equals decrement ∆V dc3 , is related to C dc , f sw , I Lr_pk , α, β, and φ.When the target voltage fluctuation amount ∆V dc,target is determined, the C dc value is given as in Equation ( 20) using the previously obtained values of I Lr_pk , α, β, and φ.If CM alternates between the UCM and LCM at every resonant period in a steady state, the total voltage change per unit capacitor becomes 2 × ∆V dc .
nergies 2022, 15, x FOR PEER REVIEW The output capacitor current ICO in the steady state, assuming a conti mode, is shown in Figure 14.Because ICO equals the output diode curren minus IO, the net charge increment of CO and QCO from t1 and t2, respectively using Equation (21).Here, t1 = sin −1 (2/π)/ω, t2 = [π-sin −1 (2/π)]/ω.Thus, to sat output voltage fluctuation range ΔVCo,target, CO is determined by Equation ( 2π ω  The output capacitor current I CO in the steady state, assuming a continuous current mode, is shown in Figure 14.Because I CO equals the output diode current (I DO1 or I DO2 ) minus I O , the net charge increment of C O and Q CO from t 1 and t 2 , respectively, is calculated using Equation (21).Here, t 1 = sin −1 (2/π)/ω, t 2 = [π-sin −1 (2/π)]/ω.Thus, to satisfy the target output voltage fluctuation range ∆V Co,target , C O is determined by Equation (22).

Four Representative Sag Types of Vleg According to the Carrie
For stable operation of the MNRV DPWM-based full-bridg level resonant converter as described thus far, an appropriate ca In DC/DC converters, it is important to maintain the symmetry o the transformer.In order to maintain the symmetry of Vleg, which put voltage, the carrier counting direction and initial value must cording to CM. Figure 15 shows the representative Vleg that can be to the carrier deformation.Vleg basically takes the shape of a squ power transfer.Additionally, at the middle, edge, or rear of the wa of a stepped sag, i.e., Vdc→2/3 × Vdc→1/3 × Vdc→2/3 × Vdc→Vdc, Vleg again.Compensation for the voltage deviations of the DC link ca that sag section.Depending on the location of the sag, we refer edge, rear, and end sags, where sag sections occur respectively a and end of Vleg.In fact, the type described and interpreted thus middle sag.

Four Representative Sag Types of V leg According to the Carrier Deformation
For stable operation of the MNRV DPWM-based full-bridge diode-clamped multilevel resonant converter as described thus far, an appropriate carrier design is required.In DC/DC converters, it is important to maintain the symmetry of the voltage applied to the transformer.In order to maintain the symmetry of V leg , which is the resonant tank input voltage, the carrier counting direction and initial value must be set appropriately according to CM. Figure 15 shows the representative V leg that can be implemented according to the carrier deformation.V leg basically takes the shape of a square wave for maximum power transfer.Additionally, at the middle, edge, or rear of the waveform, taking the form of a stepped sag, i.e., V dc →2/3 × V dc →1/3 × V dc →2/3 × V dc →V dc , V leg decreases and increases again.Compensation for the voltage deviations of the DC link capacitors is performed in that sag section.Depending on the location of the sag, we refer to these as the middle, edge, rear, and end sags, where sag sections occur respectively at the middle, edge, rear, and end of V leg .In fact, the type described and interpreted thus far corresponds to the middle sag.
V leg sag types are determined by the initial value and the counting direction of the carrier at the time the UCM and LCM start [29].For example, when the UCM starts, if the carrier decreases from its maximum value and the carrier increases from its minimum value at the moment the LCM starts, it becomes a middle sag type with a dip in the middle.The remaining sag types can also be implemented by properly designing the initial value and the counting direction of the carrier.In addition to these four types, various V leg waveforms can be created depending on the shape of the carrier.Each sag type has distinct characteristics.For the middle sag, the compensation ability for voltage deviation is excellent because the voltage-deviation-compensation operation occurs near the peak value of the resonance current, while the switching losses are greatest due to the large switching current.In addition, the sag occurs in the middle of the square wave, which has the greatest influence on the fundamental component of V leg , meaning that the input C O output voltage transfer gain is low.However, given that the period in which the output diode conducts is the longest, the RMS values of the output diode current and the resonance current are smallest, which is advantageous when conducting a large current.Regarding the edge sag, because the sag section appears at the edge, the ability to compensate for voltage deviations is somewhat lower, but the fundamental component of V leg is larger than that in the middle sag case.In addition, unlike the middle sag, where all compensation operations for voltage deviation occur under hard switching conditions, the edge sag case can reduce the switching losses because part of the compensation operations for voltage deviation may occur in the ZVS region.The rear sag is characterized as intermediate between the middle sag and the edge sag.All three of these types utilize up and down carriers.On the other hand, the end sag shows the highest efficiency because the number of switching operations is reduced compared to other types because the sag occurs only at the end of the square wave and uses up or down carriers.
than that in the middle sag case.In addition, unlike the middle sag, where all compensation operations for voltage deviation occur under hard switching conditions, the edge sag case can reduce the switching losses because part of the compensation operations for voltage deviation may occur in the ZVS region.The rear sag is characterized as intermediate between the middle sag and the edge sag.All three of these types utilize up and down carriers.On the other hand, the end sag shows the highest efficiency because the number of switching operations is reduced compared to other types because the sag occurs only at the end of the square wave and uses up or down carriers.

Simulation
To verify the operation of the proposed four-level LLC resonant converter, a simulation was conducted with the conditions shown in Table 1.

Simulation
To verify the operation the proposed four-level LLC resonant converter, a simulation was conducted with the conditions shown in Table 1. Figure 16 presents the simulation results in a steady state for the middle, edge, rear, and end sags.From the top are V C * , CM, GateA, GateB, V dc , I Cdc , I Lr , I Lm , I DO , V A , V B , I QA_upper , I QA_lower , and I DA .Here, I Cdc is the current flowing through each DC link capacitor, and I QA_upper , I QA_lower , and I DA are the upper and lower switch currents and the clamping diode currents for leg A, respectively.Although the currents of the switches and clamping diodes for leg B are not shown here, their characteristics are symmetric with those of leg A.
All four results are consistent with those described above.In a steady state, CM alternates between the UCM and LCM for every cycle.For every half cycle, one leg is clamped with a positive or negative DC rail, and the switch gates of the other leg that is not clamped are turned on/off in a specific pattern determined by the PWM_CMDs and pre-defined carrier according to the sag types.The resonance current generated according to the magnitude of the fundamental component of the V leg input to the resonance tank is transferred to the secondary side for constant control of the output voltage.In the sag section, voltage deviations among input DC link capacitors are reduced, and when the load or input voltage source changes, instead of sweeping f sw , V ampl changes to control the fundamental component of V leg .
The voltage transfer gain decreased in the order of the edge, end, rear, and middle sag types.Therefore, the magnitude of V C * required to maintain a constant output voltage under identical conditions was found to be largest at the middle sag, as expected.On the other hand, the RMS values of the output diode and the resonance currents increased in the order of the middle, rear, end, and edge sag types.Owing to the reduced switching number in the end sag case, the overall efficiency was largest for the end sag.The compensation operation for the deviation of the capacitor voltage was performed in three steps during one cycle on average, and the switching step voltage of the four-level converter was lower by one third compared to that of a two-level converter.Therefore, the switching loss of the end sag type was expected to be nearly identical to that of the conventional two-level converter.
Energies 2022, 15, 4045 20 of 26 number in the end sag case, the overall efficiency was largest for the end sag.The compensation operation for the deviation of the capacitor voltage was performed in three steps during one cycle on average, and the switching step voltage of the four-level converter was lower by one third compared to that of a two-level converter.Therefore, the switching loss of the end sag type was expected to be nearly identical to that of the conventional two-level converter.Figure 17 shows the loss analysis result of the switching devices according to the sag types when PO = 1000 W. Losses were calculated by means of thermal loss modeling with PLECS software, utilizing the datasheets of the actual devices mentioned in Section 7.2 [32].Here, Pcond,Q and Psw,Q are conduction and switching losses of the main switches, respectively.Pcond,D and Psw,D are the conduction and switching losses of the clamping diodes, Figure 17 shows the loss analysis result of the switching devices according to the sag types when P O = 1000 W. Losses were calculated by means of thermal loss modeling with PLECS software, utilizing the datasheets of the actual devices mentioned in Section 7.2 [32].Here, P cond,Q and P sw,Q are conduction and switching losses of the main switches, respectively.P cond,D and P sw,D are the conduction and switching losses of the clamping diodes, respectively.Lastly, P Cond,DO denotes the conduction losses of the output diodes.As expected, the middle sag had largest switching losses compared to the other types while also showing the smallest conduction losses.Considering the winding losses of the magnetic material, it is predicted that the middle sag type would be more advantageous under a heavy load condition.Figure 17 shows the loss analysis result of the switching devices according to types when PO = 1000 W. Losses were calculated by means of thermal loss modeli PLECS software, utilizing the datasheets of the actual devices mentioned in Sec [32].Here, Pcond,Q and Psw,Q are conduction and switching losses of the main switc spectively.Pcond,D and Psw,D are the conduction and switching losses of the clamping respectively.Lastly, PCond,DO denotes the conduction losses of the output diodes pected, the middle sag had largest switching losses compared to the other types wh showing the smallest conduction losses.Considering the winding losses of the m material, it is predicted that the middle sag type would be more advantageous heavy load condition.

Experiments
A prototype circuit (Figure 18) was designed to confirm the operation of t posed converter and to compare the performance outcomes according to the volt

Experiments
A prototype circuit (Figure 18) was designed to confirm the operation of the proposed converter and to compare the performance outcomes according to the voltage sag types.The experimental conditions are identical to those in Table 1, except that here P O varied between 500 W and 1500 W. The following devices were used in this experiment.The main switches were Fuji-Electric FGW35N60HD, the clamping diodes were ST-Microelectronic STTH15RQ06-Y, and the output diodes were Vishay VS-HFA06TB120S-M3.The centertapped transformer had four stacked ferrite cores of the EE6565S with an air gap, and its turn ratio was 47:28:28.The resonant inductor consisted of four stacked ferrite cores of the EE4242S with an air gap.The controller was implemented using TI TMS320F28377D.Increased active switch control, voltage balancing of DC link capacitors, and CM selection increased the amount of computation in the MNRV DPWM compared to conventional two-level converters.Extra logic was also added to handle the clamped PWM CMDs every half cycle and the carrier whose phase is inverted whenever CM changes.It takes a lot of interrupt service routine (ISR) time to set and change the relevant registers of every switching pair that is different from each other.This increased ISR time limits the increase in the switching frequency.In this paper, the PWM switching part was implemented using the embedded ePWM module of the DSP due to the laboratory limitations.In order to overcome this limitation of increasing the switching frequency, it is necessary to implement a PWM switching part by using an FPGA with a parallel operation function and fast processing speed.This allows for a much higher switching frequency than in this experiment.
Figure 19 shows the V A , V B , V leg , V O , and I Lr waveforms according to the voltage sag types when P O = 1500 W. It can be seen that the output voltages held constant at 350 V in all four voltage sag types and that the V leg values input to the resonance tank differed depending on the sag type, showing unique resonance current shapes.In addition, the selection of CM differed according to the magnitudes of V dc1 and V dc3 .On the other hand, the RMS value of I Lr was lowest in the middle sag case because the conduction time of the output diode was longest for that sag type.However, because the voltage transfer gain was Energies 2022, 15, 4045 22 of 26 lowest in the middle sag case, the length of d 3E was longest for the middle sag at a higher V ampl , whereas for the edge and end sags, it was conversely short.
Figures 20 and 21 show the waveforms when P O = 1000 W and 500 W, respectively, showing results similar to those in the previous analysis.As the load decreased, it can be seen that conduction time of the output diode was shortened as the magnitude of the resonance current decreased.Figure 22 confirms the DC link capacitor voltage balancing capability for each voltage sag type.As described above, the voltage imbalance was eliminated by changing the CM based on the voltage deviation of the upper and lower capacitors.Meanwhile, the d comp parameters in Equation ( 1) had the smallest value in the middle sag case, where the sag operation was performed at the peak point of the resonance current.
Figure 19 shows the VA, VB, Vleg, VO, and ILr waveforms according to the voltage sag types when PO = 1500W.It can be seen that the output voltages held constant at 350V in all four voltage sag types and that the Vleg values input to the resonance tank differed depending on the sag type, showing unique resonance current shapes.In addition, the selection of CM differed according to the magnitudes of Vdc1 and Vdc3.On the other hand, the RMS value of ILr was lowest in the middle sag case because the conduction time of the output diode was longest for that sag type.However, because the voltage transfer gain was lowest in the middle sag case, the length of d3E was longest for the middle sag at a higher Vampl, whereas for the edge and end sags, it was conversely short.
Figures 20 and 21 show the waveforms when PO = 1000 W and 500 W, respectively, showing results similar to those in the previous analysis.As the load decreased, it can be seen that conduction time of the output diode was shortened as the magnitude of the resonance current decreased.Figure 22 confirms the DC link capacitor voltage balancing capability for each voltage sag type.As described above, the voltage imbalance was eliminated by changing the CM based on the voltage deviation of the upper and lower capacitors.Meanwhile, the dcomp parameters in Equation ( 1) had the smallest value in the middle sag case, where the sag operation was performed at the peak point of the resonance current.Using a Yokogawa WT333E power meter, the power conversion efficiencies for each sag type were measured and compared as shown in Figure 23.When the load was small the middle sag type with large switching loss showed the lowest efficiency (91.1% effi ciency at PO = 500 W), but as the load increased, the middle sag type with the smallest RMS values of the resonance current and output diode current showed the highest efficiency (95.2% efficiency at PO = 1500 W).In fact, in this experiment, because the transformer turn ratio was designed to be small considering the middle sag with a small voltage transfe gain, the period of resonance section was reduced in the edge, rear, and end sag cases Thus, the resonance currents and the output diode currents of edge, rear, and end sag types became large, resulting in high conduction losses of switches and high copper losse of the transformer and inductor.Therefore, if optimally designed for each sag type, the efficiency rate of the edge, rear, and end sag types can be improved compared to those in this experiment.With an optimal design of the transformer turn ratio for each sag type the VC * should be placed at a high level of LVR in its normal operating range.Using a Yokogawa WT333E power meter, the power conversion efficiencies for each sag type were measured and compared as shown in Figure 23.When the load was small, the middle sag type with large switching loss showed the lowest efficiency (91.1% efficiency at P O = 500 W), but as the load increased, the middle sag type with the smallest RMS values of the resonance current and output diode current showed the highest efficiency (95.2% efficiency at P O = 1500 W).In fact, in this experiment, because the transformer turn ratio was designed to be small considering the middle sag with a small voltage transfer gain, the period of resonance section was reduced in the edge, rear, and end sag cases.Thus, the resonance currents and the output diode currents of edge, rear, and end sag types became large, resulting in high conduction losses of switches and high copper losses of the transformer and inductor.Therefore, if optimally designed for each sag type, the efficiency rate of the edge, rear, and end sag types can be improved compared to those in this experiment.With an optimal design of the transformer turn ratio for each sag type, the V C * should be placed at a high level of LVR in its normal operating range.

Conclusions
In this paper, we proposed an amplitude-modulating full-bridge diode-clamped multilevel LLC resonant converter suitable for power conversion systems that use high input voltages.A new modulation scheme called MNRV DPWM was applied to eliminate voltage deviations in DC link capacitors connected in series.The proposed multilevel resonant converter operates by modulating the magnitude of the fundamental wave input to the resonant tank while fixing the operating frequency at the resonant point.The fixed operating point facilitates the design of passive devices and enables stable operation over a wide operating range with just one power conversion stage.In this paper, we proposed a control algorithm and analyzed the operating characteristics of the proposed diodeclamped four-level LLC resonant converter and presented design guidelines.The feasibility and effectiveness of the proposed converter were verified through a simulation and via experimentation with the prototype converter.

Conclusions
In this paper, we proposed an amplitude-modulating full-bridge diode-clamped multilevel LLC resonant converter suitable for power conversion systems that use high input voltages.A new modulation scheme called MNRV DPWM was applied to eliminate voltage deviations in DC link capacitors connected in series.The proposed multilevel resonant converter operates by modulating the magnitude of the fundamental wave input to the resonant tank while fixing the operating frequency at the resonant point.The fixed operating point facilitates the design of passive devices and enables stable operation over a wide operating range with just one power conversion stage.In this paper, we proposed a control algorithm and analyzed the operating characteristics of the proposed diode-

Figure 2 .
Figure 2. Implementation example of MNRV DPWM for a single-phase diode-clamped four-level PWM converter: (a) selection of MNRVs according to the VC * position, (b) switching patterns of the conventional CB-SPWM, and (c) those of the proposed MNRV DPWM.

Figure 2 .
Figure 2. Implementation example of MNRV DPWM for a single-phase diode-clamped four-level PWM converter: (a) selection of MNRVs according to the V C * position, (b) switching patterns of the conventional CB-SPWM, and (c) those of the proposed MNRV DPWM.

Figure 3 .
Figure 3. Voltage imbalance problem of a diode-clamped four-level PWM converter us SPWM.

Figure 3 .
Figure 3. Voltage imbalance problem of a diode-clamped four-level PWM converter using CB-SPWM.

Figure 4 .
Figure 4. MNRV selection rule according to the VC * position in single-phase full-bridge d clamped multilevel topologies.

Figure 4 .
Figure 4. MNRV selection rule according to the V C * position in single-phase full-bridge diodeclamped multilevel topologies.

Figure 5 .
Figure 5 shows the circuit of the proposed full-bridge diode-clamped four-level LLC resonant converter.The voltage source V dc supplies input power through the DC link stage composed of three series-connected capacitors, C dc1 , C dc2 , and C dc3 .The full-bridge switching stage is composed of the switches Q A1 ~QA6 and Q B1 ~QB6 , and the clamping diodes D A1 ~DA6 and D B1 ~DB6 that connect the unit step capacitor voltages of the DC link stage to each switching node.The resonance tank stage composed of resonant inductor L r , resonant capacitor C r , and magnetizing inductor L m receives voltage amplitude modulated sag-type voltage with a fixed frequency from switching leg voltage V leg (=V AB = V A − V B ).The resonant current I Lr charges the output capacitor C O through an n:1:1 center-tapped transformer and the output rectification stage composed of diodes D O1 and D O2 and supplies power to the load R L .Energies 2022, 15, x FOR PEER REVIEW 10

Figure 5 .
Figure 5. Circuit diagram of the proposed full-bridge diode-clamped four-level LLC converter.

Figure 8
Figure 8 depicts the equivalent circuit of the resonance tank at the resonance point.Regardless of CM, when VC * > 0, one from among Vdc, 2/3 × Vdc, and 1/3 × Vdc is applied to Vleg, and nVO is applied to the magnetizing inductor Lm.When the voltage of Vleg−nVO is supplied to LrCr, ILr and ILm increase in the positive direction.Meanwhile, when VC * < 0, one from among −Vdc, −2/3 × Vdc, and −1/3 × Vdc is applied to Vleg and −nVO is applied to Lm. ILr and ILm decrease by Vleg+nVO supplied to Lr-Cr.

Figure 8 .
Figure 8. Equivalent circuit of the resonant tank at the resonance point.

Figure 7 .
Figure 7. Operating circuit states when (a) V C * > 0 and (b) V C * < 0 in the UCM and when (c) V C * > 0 and (d) V C * < 0 in the LCM.

Figure 8
Figure8depicts the equivalent circuit of the resonance tank at the resonance point.Regardless of CM, when VC * > 0, one from among Vdc, 2/3 × Vdc, and 1/3 × Vdc is applied to Vleg, and nVO is applied to the magnetizing inductor Lm.When the voltage of Vleg−nVO is supplied to LrCr, ILr and ILm increase in the positive direction.Meanwhile, when VC * < 0, one from among −Vdc, −2/3 × Vdc, and −1/3 × Vdc is applied to Vleg and −nVO is applied to Lm. ILr and ILm decrease by Vleg+nVO supplied to Lr-Cr.

Figure 8 .
Figure 8. Equivalent circuit of the resonant tank at the resonance point.

*Figure 8 .
Figure 8. Equivalent circuit of the resonant tank at the resonance point.

Figure 9 .
Figure 9. Operating mode analysis of the proposed converter.

Figure 9 .
Figure 9. Operating mode analysis of the proposed converter.

Figure 10 .
Figure 10.Decomposition of Vleg according to the voltage sag range.

Figure 10 .
Figure 10.Decomposition of V leg according to the voltage sag range.

Figure 11 .
Figure 11.Resonant current waveform at f sw = f r .

Figure 13 .
Figure 13.Voltage change characteristics of DC link capacitors in the LCM.

Figure 13 .
Figure 13.Voltage change characteristics of DC link capacitors in the LCM.

Figure 14 .
Figure 14.Current waveform of the output capacitor.

Figure 14 .
Figure 14.Current waveform of the output capacitor.

3 Figure 15 .
Figure 15.Four typical V leg waveforms depending on the carrier wave shape: (a) middle, (b) edge, (c) rear, and (d) end sag types.

Figure 17 .
Figure 17.Switches loss analysis for the middle, edge, rear, and end sag types when PO = 1

Figure 23 .
Figure 23.Efficiency comparison for the middle, edge, rear, and end sags.

Figure 23 .
Figure 23.Efficiency comparison for the middle, edge, rear, and end sags.