Current Sharing Control of an Interleaved Three-Phase Series-Resonant Converter with Phase Shift Modulation

: Recently, three-phase series-resonant converters (SRCs) have been proposed for high power applications. Three-phase SRCs can achieve zero-voltage-switching (ZVS) of the primary power switches and regulate the output voltage by pulse-frequency modulation. The interleaving technique is also a conventional method for DC-DC converters to achieve a high power level, reducing the output voltage ripples due to operating out of phase at the same frequency between the two converters. However, an interleaved three-phase SRC cannot easily synchronize switching instants between the two modules due to the component tolerances of circuits. In the proposed control method, phase shift modulation (PSM) is used to solve the output current imbalance caused by component tolerances. The power switches of the converter can also maintain synchronizing switching instants between the two modules. Therefore, the lower output voltage ripple can be achieved. A detailed analysis and design of this new control method for interleaved three-phase SRCs are described. Finally, prototype converters with a 2.4 kW total output were built and successfully tested to verify the feasibility of the current sharing modulation.


Introduction
In the past decades, the resonant converter has been widely used in many applications such as laptop adapters, server power supply units and battery chargers. The reason for its wide use is its many advantages such as zero-voltage-switching (ZVS) at primary-side power switches, zero-current-switching at secondary-side rectifiers and a high conversion efficiency. However, the resonant converter is not suitable in high power and large output current applications because the secondary-side rectifiers do not use stored energy inductors such as an LLC resonant converter; thus, the secondary-side current is larger compared with other DC-DC converters. Therefore, many output capacitors are needed to parallel with the output side to satisfy the rated ripple voltage. The interleaved technique has been widely used for the high output power level. This technique can divide load current into each module and reduce output current ripple and voltage ripple. However, the conventional interleaving control for pulse-width modulation (PWM) cannot be directly applied to the resonant converters because they use pulse-frequency modulation (PFM) to regulate output voltage and the operational frequency of each module must be synchronized for the interleaved operations. However, when component tolerance occurs between the two modules, different gain characteristics will arise at a synchronized operational frequency. Thus, it will lose the advantage of interleaving control and will cause large output voltage ripples. Many studies have proposed an interleaving method of resonant converters. The influence of parameter mismatch of a resonant circuit and the improvement of current balancing are discussed in [1][2][3][4][5][6][7][8][9][10][11]. In [12], the output voltage of power-factor correction (PFC) was used to compensate for the parameter of the resonant circuit mismatch between the two modules. The PFC had to be placed in front of each module of the resonant converters. In [13], the switch-controlled capacitor method was used to control output current sharing on each module. However, extra power switches had to be added, increasing the cost and volume of the converter. In [14], the current sharing method needed an additional power stage to regulate the output voltage but this method caused a lower conversion efficiency because the additional power stage caused other power losses. Three-phase series-resonant converters (SRCs) have been proposed for high power level applications. In comparison with other approaches, these SRCs can achieve better power loss distributions, excellent thermal distribution and much lower output voltage ripples. The three-phase SRC, three-phase LCC resonant converter and three-phase LLC resonant converter were proposed in [15][16][17][18]. These studies discussed the principle of operations about three-phase resonant converters. Similar to ordinary single-phase resonant converters, the output voltage of the three-phase SRC is regulated by a PFM control so that the interleaving technique is also difficult to use on three-phase SRCs.
In this paper, an interleaved structure of the three-phase SRC is proposed. In the proposed method, the three-phase SRC operates at a PFM control for regulated output voltage. Moreover, the influence of circuit parameter mismatch is compensated by a PSM control to achieve current balance. The proposed method does not require any auxiliary circuits and switching instants between modules can achieve synchronization. Section 2 describes the operation principle of an interleaved structure of a three-phase SRC with PSM. Section 3 provides an analysis and design for this proposed method. Section 4 demonstrates the experimental results of a 2.4 kW prototype. Section 5 concludes the paper.

Operation Principle of a Three-Phase Series-Resonant Converters (SRC)
The three-phase SRC schematic is shown in Figure 1. The circuit on the primary-side consists of three switch legs and three resonant tanks. The control signal is shown in Figure 2. Switches S 1 -S 6 are controlled at a 0.5 duty ratio and three legs exhibit phase shifts at 0 • , 120 • and 240 • , respectively. The secondary-side transformers consist of three switch legs; switches S a -S f are also controlled at a 0.5 duty ratio and three legs exhibit phase shifts at 120 • and 240 • . The phase shift degree ϕ between the primary-side and secondary-side is for output power control. Therefore, switches S 1 and S a represent phase shift degree ϕ, as do switches S 3 and S c as well as S 5 and S e . was used to control output current sharing on each module. However, extra pow switches had to be added, increasing the cost and volume of the converter. In [14], t current sharing method needed an additional power stage to regulate the output volta but this method caused a lower conversion efficiency because the additional power sta caused other power losses. Three-phase series-resonant converters (SRCs) have been p posed for high power level applications. In comparison with other approaches, these SR can achieve better power loss distributions, excellent thermal distribution and much low output voltage ripples. The three-phase SRC, three-phase LCC resonant converter a three-phase LLC resonant converter were proposed in [15][16][17][18]. These studies discuss the principle of operations about three-phase resonant converters. Similar to ordinary s gle-phase resonant converters, the output voltage of the three-phase SRC is regulated a PFM control so that the interleaving technique is also difficult to use on three-pha SRCs.
In this paper, an interleaved structure of the three-phase SRC is proposed. In the pr posed method, the three-phase SRC operates at a PFM control for regulated output vo age. Moreover, the influence of circuit parameter mismatch is compensated by a PSM co trol to achieve current balance. The proposed method does not require any auxiliary c cuits and switching instants between modules can achieve synchronization. Section 2 d scribes the operation principle of an interleaved structure of a three-phase SRC with PS Section 3 provides an analysis and design for this proposed method. Section 4 demo strates the experimental results of a 2.4 kW prototype. Section 5 concludes the paper.

Operation Principle of a Three-Phase Series-Resonant Converters (SRC)
The three-phase SRC schematic is shown in Figure 1. The circuit on the primary-si consists of three switch legs and three resonant tanks. The control signal is shown in F ure 2. Switches S1-S6 are controlled at a 0.5 duty ratio and three legs exhibit phase shi at 0°, 120° and 240°, respectively. The secondary-side transformers consist of three swit legs; switches Sa-Sf are also controlled at a 0.5 duty ratio and three legs exhibit phase shi at 120° and 240°. The phase shift degree φ between the primary-side and secondary-si is for output power control. Therefore, switches S1 and Sa represent phase shift degree as do switches S3 and Sc as well as S5 and Se.      Figure 3 shows the key waveforms of the three-phase SRC in one switching cycle. A complete half positive switching cycle comprises five states because the inductor current can be iLrα = iLrβ = iLrγ with phase shifts of 120° and 240°, which can only use one phase to analyze simplified calculations. The basic idea about the three-phase SRC has been discussed in many studies [19,20]. The resonant frequency fr and the power transfer of a three-phase SRC has been expressed as:   Figure 3 shows the key waveforms of the three-phase SRC in one switching cycle. A complete half positive switching cycle comprises five states because the inductor current can be i Lrα = i Lrβ = i Lrγ with phase shifts of 120 • and 240 • , which can only use one phase to analyze simplified calculations. The basic idea about the three-phase SRC has been discussed in many studies [19,20]. The resonant frequency f r and the power transfer of a three-phase SRC has been expressed as:   Figure 3 shows the key waveforms of the three-phase SRC in one switching cycle. A complete half positive switching cycle comprises five states because the inductor current can be iLrα = iLrβ = iLrγ with phase shifts of 120° and 240°, which can only use one phase to analyze simplified calculations. The basic idea about the three-phase SRC has been discussed in many studies [19,20]. The resonant frequency fr and the power transfer of a three-phase SRC has been expressed as:  Equation (2) can explain the elements that can use the phase shift degree ϕ and switching frequency f sw to regulate output power P o . Figure 4 depicts the relationship between the phase shift degree ϕ and output power P o . The phase shift degree ϕ must be limited between 30 • and 60 • to transform the power into the output load side. In addition, the specifications in Figure 5 are used except for frequency f sw , which is defined as 125 kHz. To explain the relationship among the voltage gain, phase shift degree ϕ and switching frequency f sw ,the voltage gain is defined as nV o /V in and Equation (3) can be derived from Equation (2) where n is the turn ratio of the primary-side to the secondary-side of the transformers, assuming a voltage gain nV o /V in = 0.56, V in = 400 V DC , V o = 48 V DC and I o = 25 A. Therefore, R L is equal to 1.92 Ω, the resonant inductor L r is 18 µH, the resonant capacitor C r is 141 nF and the switching frequency f sw is limited between 100 and 200 kHz to normalize the frequency f sw . The gain curve diagram is shown in Figure 5. The frequency f sw is normalized as f n by dividing the resonant frequency f r , which is 100 kHz. As the color changes from blue to yellow, this indicates that the gain is from low to high. The output voltage can be regulated by the phase shift degree ϕ and normalized frequency f n . Furthermore, when increasing the phase shift degree ϕ or decreasing the normalized frequency f n , the voltage gain obviously rises.
where R L = V o /I o and n = N p /N s . Equation (2) can explain the elements that can use the phase shift degree φ and switching frequency fsw to regulate output power Po. Figure 4 depicts the relationship between the phase shift degree φ and output power Po. The phase shift degree φ must be limited between 30° and 60° to transform the power into the output load side. In addition, the specifications in Figure 5 are used except for frequency fsw, which is defined as 125 kHz. To explain the relationship among the voltage gain, phase shift degree φ and switching frequency fsw, the voltage gain is defined as nVo/Vin and Equation (3) can be derived from Equation (2) where n is the turn ratio of the primary-side to the secondary-side of the transformers, assuming a voltage gain nVo/Vin = 0.56, Vin = 400 VDC, Vo = 48 VDC and Io = 25 A. Therefore, RL is equal to 1.92 Ω, the resonant inductor Lr is 18 μH, the resonant capacitor Cr is 141 nF and the switching frequency fsw is limited between 100 and 200 kHz to normalize the frequency fsw. The gain curve diagram is shown in Figure 5. The frequency fsw is normalized as fn by dividing the resonant frequency fr, which is 100 kHz. As the color changes from blue to yellow, this indicates that the gain is from low to high. The output voltage can be regulated by the phase shift degree φ and normalized frequency fn. Furthermore, when increasing the phase shift degree φ or decreasing the normalized frequency fn, the voltage gain obviously rises.  Equation (2) can explain the elements that can use the phase shift degree φ and switching frequency fsw to regulate output power Po. Figure 4 depicts the relationship between the phase shift degree φ and output power Po. The phase shift degree φ must be limited between 30° and 60° to transform the power into the output load side. In addition, the specifications in Figure 5 are used except for frequency fsw, which is defined as 125 kHz. To explain the relationship among the voltage gain, phase shift degree φ and switching frequency fsw, the voltage gain is defined as nVo/Vin and Equation (3) can be derived from Equation (2) where n is the turn ratio of the primary-side to the secondary-side of the transformers, assuming a voltage gain nVo/Vin = 0.56, Vin = 400 VDC, Vo = 48 VDC and Io = 25 A. Therefore, RL is equal to 1.92 Ω, the resonant inductor Lr is 18 μH, the resonant capacitor Cr is 141 nF and the switching frequency fsw is limited between 100 and 200 kHz to normalize the frequency fsw. The gain curve diagram is shown in Figure 5. The frequency fsw is normalized as fn by dividing the resonant frequency fr, which is 100 kHz. As the color changes from blue to yellow, this indicates that the gain is from low to high. The output voltage can be regulated by the phase shift degree φ and normalized frequency fn. Furthermore, when increasing the phase shift degree φ or decreasing the normalized frequency fn, the voltage gain obviously rises.

Design of Phase Lagging Degree and Phase Shift Degree
The interleaved three-phase SRC schematic is shown in Figure 6. The SRC consists of two modules of a three-phase SRC, which are divided into modules A and B. C r is  Figure 7. The phase shift degree ϕ A is module A between the primary-and secondary-sides. The phase shift degree ϕ B is module B between the primary-and secondary-sides. The phase shift degrees ϕ A and ϕ B are separately independent to control modules A and B for output power, respectively. Moreover, to achieve a minimum total output ripple current I o_pp , module B control signals will be lagging the ϕ AB degree of module A. The phase lagging degree ϕ AB can be calculated as Equation (4) is drawn in Figure 8, which is normalized by i o_ppmax . When the phase lagging ϕ AB is 30 • , the converter will have a minimum total output ripple current i o_pp . Therefore, module B control signals will be set to lagging module A by 30 • .

Design of Phase Lagging Degree and Phase Shift Degree
The interleaved three-phase SRC schematic is shown in Figure 6. The SRC consists of two modules of a three-phase SRC, which are divided into modules A and B. Cr is the resonant capacitor. LrA is the resonant inductor of module A and LrB is the resonant inductor of module B. In ideal conditions, the LrA and LrB have equivalent values. The key waveforms of the interleaved three-phase SRC are shown in Figure 7. The phase shift degree φA is module A between the primary-and secondary-sides. The phase shift degree φB is module B between the primary-and secondary-sides. The phase shift degrees φA and φB are separately independent to control modules A and B for output power, respectively. Moreover, to achieve a minimum total output ripple current Io_pp, module B control signals will be lagging the φAB degree of module A. The phase lagging degree φAB can be calculated as Equation (4) is drawn in Figure 8, which is normalized by io_ppmax. When the phase lagging φAB is 30°, the converter will have a minimum total output ripple current io_pp. Therefore, module B control signals will be set to lagging module A by 30°.

Current Sharing Control of PSM
The digital control block diagram of the interleaved three-phase SRC is shown in Figure 9. To achieve output voltage stabilization and current sharing under all load ranges, the control method combines a PFM control to regulate the output voltage and a PSM control to achieve current sharing.

Closed Loop Design
As the state-space averaging method can maintain an accuracy under 1/5 of fsw [21], the simplified small-signal model of the proposed converter as shown in Figure 11 is used for the closed loop design [22]. The expressions of the small-signal value of the output current io can be derived by taking the partial derivative of Equation (2) with respect to fsw and φ as follows.  is entered into a compensator. The frequency is then controlled through a voltage-control oscillator as a PFM control. The error between reference current I ref , which is half of the total output current, and either I oA [k] or I oB [k] is entered into a compensator to control the phase shift angle ∆ϕ and as a PSM control. The initial phase angle ϕ i is calculated through Equation (6) with I ref and f sw . Finally, 12 enhanced pulsewidth modulator (ePWM) modules with desired periods and phases are used to generate the 24 signals to control the circuit.
The program is implemented by a digital signal processor (DSP), namely, TMS320F28379. The main control flow chart is shown in Figure 10. The cycled steps of the proposed modulation are shown as follows.

•
To achieve the above functions, three ADC inputs are needed to convert the sampled signals into digital values after interruption.

•
The same operating frequency of modules A and B are determined by the output voltage feedback with a proportional-integral (PI) controller.

•
For the ϕ i calculation and average current sharing control, a reference current I ref set as half of the total output current is needed. • ϕ i is calculated through Equation (6), which is derived from Equation (2) with I ref and f sw .

Closed Loop Design
As the state-space averaging method can maintain an accuracy under 1/5 of fsw [21], the simplified small-signal model of the proposed converter as shown in Figure 11 is used for the closed loop design [22]. The expressions of the small-signal value of the output current io can be derived by taking the partial derivative of Equation (2) with respect to fsw and φ as follows.

Closed Loop Design
As the state-space averaging method can maintain an accuracy under 1/5 of f sw [21], the simplified small-signal model of the proposed converter as shown in Figure 11 is used for the closed loop design [22]. The expressions of the small-signal value of the output current i o can be derived by taking the partial derivative of Equation (2) with respect to f sw and ϕ as follows.
As the digital sample and delay cause a phase margin drop, the crossover frequency needs to be designed smaller than analog. The PI controller is designed with a crossover frequency of 5 kHz and a phase margin of 96° for output voltage stabilization and a fast load transient. The integral controllers are designed with a crossover frequency of 500 Hz and a phase margin of 91° for a current sharing feedback loop. The Bode plots of the compensated loop gain for both functions are shown in Figure 12. As the digital sample and delay cause a phase margin drop, the crossover frequency needs to be designed smaller than analog. The PI controller is designed with a crossover frequency of 5 kHz and a phase margin of 96 • for output voltage stabilization and a fast    Table 1. In general, 130 kHz was the maximum limit of the switching frequency f sw for the power density and the high conversion efficiency. The phase shift degree ϕ A and ϕ B were limited to a maximum of 40 • and the lagging degree ϕ AB was set at 30 • for the minimum output ripple voltage. Equation (3) shows that the voltage gain was 0.56. The equivalent output resistances of the single module R L were 7.38 Ω at 25% load condition, 3.84 Ω at the 50% load condition and 1.92 Ω at the 100% load condition. Therefore, the resonant inductor followed Equation (1) and it could be obtained at approximately 18 µH.  Figure 13 shows the simulation results of the ideal interleaved three-phase SRC. The resonant inductors L rA and L rB were equal to 18 µH. When the output load from 25% increased to the full load, modules A and B showed that switching frequency f sw changed from 130 kHz to 121 kHz and the phase shift degree ϕ A and ϕ B changed from 32.8 • to approximately 40 • . By contrast, the module cause of the imbalanced condition was the tolerance in the resonant inductor values of the converter. Generally, a 10% change in the magnetic component values could be expected, causing an imbalanced output current between modules A and B. Figures 14-16 show the simulation results of the imbalanced conditions when L rA was 20 µH and L rB was 16 µH. Figure 12 shows 25% output power load conditions. To maintain a voltage gain at 0.56 for regulated output voltage and interleaved operation, the switching frequency f sw of modules A and B operated at 130 kHz. The phase shift degree ϕ A of module A and the phase shift degree ϕ B of module B were 33.1 • and 32.5 • , respectively. In Figure 15, when the output load condition was at 50%, the switching frequency f sw operated at 127 kHz, the phase shift degree ϕ A of module A operated at 36.1 • and the phase shift degree ϕ B operated at 34.9 • . Figure 14 shows the output power at full load. The switching frequency f sw was at 121 kHz and the phase shift degree ϕ A and ϕ B operated at 41.7 • and 39.3 • , respectively.      respectively. In Figure 17a, the gate signal V gsBa lagged V gsAa by approximately 30 • so that the output ripple voltage V oac could be decreased. By contrast, because the PSM control was disabled, the phase shift degree ϕ A and the phase shift degree ϕ B were the same at 40.5 • so the output current I oA and I oB were imbalanced. In Figure 17b, the PSM control was used for the output current balance. The switching frequency was approximately 121.2 kHz, the phase shift degree ϕ A was 41.8 • and ϕ B was 39.2 • . These simulation results corresponded with those in Figure 16.

Experimental Results
To verify the theoretical analysis, a 2.4 kW prototype was designed and built as shown in Figure 18. Its key parameters are shown in Table 1. The component values are listed in Table 2. The PQ-4040 core was used for isolation transformers T1, T2, T3, T4, T5 and T6, the resonant inductor core was CH330060 and the power switches were IPL60R199CP and IPB020N08N5.

Experimental Results
To verify the theoretical analysis, a 2.4 kW prototype was designed and built as shown in Figure 18. Its key parameters are shown in Table 1. The component values are listed in Table 2. The PQ-4040 core was used for isolation transformers T 1 , T 2 , T 3 , T 4 , T 5 and T 6 , the resonant inductor core was CH330060 and the power switches were IPL60R199CP and IPB020N08N5.    Figure 19 shows the ZVS waveform measured by the primary-and secondary-side power switches at a 25% load. The power switch was turned on after the Vds of the power switch dropped to a zero level, achieving ZVS.

Component Part Number
MOSFETs (primary-side) IPL60R199CP MOSFETs (secondary-side) IPB020N08N5 Transformer core (T 1~T6 ) PQ-4040 Resonant inductor core (L rA , L rB ) CH330060 DSP controller TMS320F28379 Figure 19 shows the ZVS waveform measured by the primary-and secondary-side power switches at a 25% load. The power switch was turned on after the V ds of the power switch dropped to a zero level, achieving ZVS.

Component
Part Number MOSFETs (primary-side) IPL60R199CP MOSFETs (secondary-side) IPB020N08N5 Transformer core (T1~T6) PQ-4040 Resonant inductor core (LrA, LrB) CH330060 DSP controller TMS320F28379 Figure 19 shows the ZVS waveform measured by the primary-and secondary-side power switches at a 25% load. The power switch was turned on after the Vds of the power switch dropped to a zero level, achieving ZVS.      The values of resonant inductors LrA and LrB were set at different values to test imbalanced current conditions. LrA was designed as 20 μH and LrB was 16 μH. Figure 22 shows the output current waveforms of the two modules in parallel at a 25% load conduction. Figure 22a,b show without and with a current sharing control. When the function of the current sharing control was disabled, the current was imbalanced due to component mismatch. With a PSM control, the imbalanced current was improved. Both ripple current frequencies of ioA and ioB were six times larger than the switching frequency. Furthermore, with phase lagging φAB at 30°, the ripple current frequency of io was twelve times larger than the switching frequency, achieving a minimum output ripple current io_pp. The trend of switching frequency and phase shift changing was the same as Figure  13 in that when the load was increased, the switching frequency fsw decreased and the phase shift degree φA increased.   Figure 21 shows typical waveforms at a single module. The resonant inductor LrA was equal to 18 μH and had different output load conditions (6.25, 12.5, 18.75 and 25 A). The measured waveforms were the waveforms of Vgs2 and Vds2 of the primary-side low-bridge switch S2, the resonant inductor current iLrα and the Vgsb of the secondary-side switch Sb.
The values of resonant inductors LrA and LrB were set at different values to test imbalanced current conditions. LrA was designed as 20 μH and LrB was 16 μH. Figure 22 shows the output current waveforms of the two modules in parallel at a 25% load conduction. Figure 22a,b show without and with a current sharing control. When the function of the current sharing control was disabled, the current was imbalanced due to component mismatch. With a PSM control, the imbalanced current was improved. Both ripple current frequencies of ioA and ioB were six times larger than the switching frequency. Furthermore, with phase lagging φAB at 30°, the ripple current frequency of io was twelve times larger than the switching frequency, achieving a minimum output ripple current io_pp. The trend of switching frequency and phase shift changing was the same as Figure  13 in that when the load was increased, the switching frequency fsw decreased and the phase shift degree φA increased. The values of resonant inductors L rA and L rB were set at different values to test imbalanced current conditions. L rA was designed as 20 µH and L rB was 16 µH. Figure 22 shows the output current waveforms of the two modules in parallel at a 25% load conduction. Figure 22a,b show without and with a current sharing control. When the function of the current sharing control was disabled, the current was imbalanced due to component mismatch. With a PSM control, the imbalanced current was improved. Both ripple current frequencies of i oA and i oB were six times larger than the switching frequency. Furthermore, with phase lagging ϕ AB at 30 • , the ripple current frequency of i o was twelve times larger than the switching frequency, achieving a minimum output ripple current i o_pp .  Figure 22. Output current waveforms of two modules in parallel at a 25% load:(a) without a current sharing control, (b) with a current sharing control. Figure 23 shows the current sharing waveforms of the two modules with the current sharing phase shift control at 50%, 75% and 100% load conditions. The output currents were balanced at different loads. Table 3 shows the output current error of the two modules and the current sharing error ratio was under 3%. Figure 24 shows the phase shift waveforms of modules A and B at different load conditions. The phase lagging was approximately 30°. When the load was increased, the phase shift degree φA and φB increased and the switching frequency decreased to regulate the output voltage. In addition, the phase shift degree φA and φB operated in different degrees to balance the output current between modules A and B. The measurement results were identical to the simulation results in Figures 14-16.  The trend of switching frequency and phase shift changing was the same as Figure 13 in that when the load was increased, the switching frequency f sw decreased and the phase shift degree ϕ A increased. Figure 23 shows the current sharing waveforms of the two modules with the current sharing phase shift control at 50%, 75% and 100% load conditions. The output currents were balanced at different loads. Table 3 shows the output current error of the two modules and the current sharing error ratio was under 3%.  Figure 22. Output current waveforms of two modules in parallel at a 25% load:(a) without a current sharing control, (b) with a current sharing control. Figure 23 shows the current sharing waveforms of the two modules with the current sharing phase shift control at 50%, 75% and 100% load conditions. The output currents were balanced at different loads. Table 3 shows the output current error of the two modules and the current sharing error ratio was under 3%. Figure 24 shows the phase shift waveforms of modules A and B at different load conditions. The phase lagging was approximately 30°. When the load was increased, the phase shift degree φA and φB increased and the switching frequency decreased to regulate the output voltage. In addition, the phase shift degree φA and φB operated in different degrees to balance the output current between modules A and B. The measurement results were identical to the simulation results in Figures Figure 24 shows the phase shift waveforms of modules A and B at different load conditions. The phase lagging was approximately 30 • . When the load was increased, the    Figure 25 shows the output ripple voltage waveform at a 100% load and with the interleaved two modules, which achieved a minimum output ripple current io_pp to reduce the volume of the output capacitor. In addition, Figure 26 shows the result of the dynamic load from 10 A to 50 A. The overshoot and undershoot of the output voltage were about 4 V. The efficiency curve of the converter was measured with a power meter and is shown in Figure 27. The highest efficiency could reach 94.5%.   Figure 25 shows the output ripple voltage waveform at a 100% load and with the interleaved two modules, which achieved a minimum output ripple current i o_pp to reduce the volume of the output capacitor. In addition, Figure 26 shows the result of the dynamic load from 10 A to 50 A. The overshoot and undershoot of the output voltage were about 4 V. The efficiency curve of the converter was measured with a power meter and is shown in Figure 27. The highest efficiency could reach 94.5%.    Figure 25 shows the output ripple voltage waveform at a 100% load and with the interleaved two modules, which achieved a minimum output ripple current io_pp to reduce the volume of the output capacitor. In addition, Figure 26 shows the result of the dynamic load from 10 A to 50 A. The overshoot and undershoot of the output voltage were about 4 V. The efficiency curve of the converter was measured with a power meter and is shown in Figure 27. The highest efficiency could reach 94.5%.    Figure 27. Efficiency of an interleaved three-phase SRC with phase shift modulation.

Conclusions
To solve the current imbalance between two modules, this paper presented the PSM control for an interleaved three-phase SRC. The component mismatch of the resonant inductor was made to verify the validity of the proposed method. Using the proposed method achieved a current sharing function and synchronized switching frequencies. Thus, the proposed method is important in decreasing the output ripple voltage and equally distributing conduction losses between modules A and B. The experimental results on a 2.4 kW prototype were recorded to verify the theoretical analysis. The results showed that the PSM control could achieve the current sharing The phase lagging of 30° could achieve the minimized output ripple voltage.    Figure 27. Efficiency of an interleaved three-phase SRC with phase shift modulation.

Conclusions
To solve the current imbalance between two modules, this paper presented the PSM control for an interleaved three-phase SRC. The component mismatch of the resonant inductor was made to verify the validity of the proposed method. Using the proposed method achieved a current sharing function and synchronized switching frequencies. Thus, the proposed method is important in decreasing the output ripple voltage and equally distributing conduction losses between modules A and B. The experimental results on a 2.4 kW prototype were recorded to verify the theoretical analysis. The results showed that the PSM control could achieve the current sharing The phase lagging of 30° could achieve the minimized output ripple voltage.

Conclusions
To solve the current imbalance between two modules, this paper presented the PSM control for an interleaved three-phase SRC. The component mismatch of the resonant inductor was made to verify the validity of the proposed method. Using the proposed method achieved a current sharing function and synchronized switching frequencies. Thus, the proposed method is important in decreasing the output ripple voltage and equally distributing conduction losses between modules A and B. The experimental results on a 2.4 kW prototype were recorded to verify the theoretical analysis. The results showed that the PSM control could achieve the current sharing The phase lagging of 30 • could achieve the minimized output ripple voltage.